commit 1bbd8d5146fd8c462fd837eba317b192ca49f772 Author: Yorick Barbanneau Date: Thu Apr 15 02:13:53 2021 +0200 First commit (WIP) diff --git a/Dockerfile b/Dockerfile new file mode 100644 index 0000000..02e9e4f --- /dev/null +++ b/Dockerfile @@ -0,0 +1,22 @@ +FROM debian:bullseye-slim + +RUN apt update \ + && apt install -y --no-install-recommends gzip \ + gcc-aarch64-linux-gnu \ + make \ + bc \ + device-tree-compiler \ + qemu-system-aarch64 \ + qemu-user-static \ + build-essential \ + bison flex \ + libssl-dev \ + bash \ + git \ + ca-certificates + +COPY docker/entrypoint.sh /tmp +COPY src/ /tmp +WORKDIR /tmp +CMD /tmp/entrypoint.sh +#CMD bash diff --git a/README.md b/README.md new file mode 100644 index 0000000..87cf2b8 --- /dev/null +++ b/README.md @@ -0,0 +1,31 @@ +MNT Reform Kernel build script +------------------------------ + +Work in progress script for building Linux Kernel for the MNT Refom 2 computer. + +## Build with docker + +Build the image : + +``` +docker build -t reform_kernel_build . +``` + +Then run the container with with a directory mapped to `/output`: + +``` +docker run -v /home/docker/output:/output --env KERNEL_VERSION=5.11 --rm reform_kernel_build +``` + +You need to pass `KERNEL_VERSION` environment variable to your container do tell +`make_kernel.sh` which version to compile. + +Kernel and dtb files will be in the directory mapped to `/output` in the +container. + +## Licence + +This work is derivated from MNT script found [here][l_mnt_image] and licenced +under the GPLv3 Licence + +[l_mnt_image]:https://source.mnt.re/reform/reform-system-image/ diff --git a/docker/entrypoint.sh b/docker/entrypoint.sh new file mode 100755 index 0000000..049580f --- /dev/null +++ b/docker/entrypoint.sh @@ -0,0 +1,20 @@ +#!/bin/bash + +# Entrypoint for reform-build-kernel docker image + +if [ -f /output/Image ] +then + printf "Kernel image exist in destination aborting compilation.\n" + exit 0 +fi + +if ./make_kernel.sh +then + cp linux/arch/arm64/boot/Image /output/ + cp linux/arch/arm64/boot/dts/freescale/imx8mq-mnt-reform2.dtb /output/imx8mq-mnt-reform2-single-display.dtb + cp linux/arch/arm64/boot/dts/freescale/imx8mq-mnt-reform2-hdmi.dtb /output/imx8mq-mnt-reform2-dual-display.dtb +else + printf "Error when building Kernel\n" 1>&2 + exit 10 +fi +exit 0 diff --git a/src/dts/imx8mq-mnt-reform2-hdmi.dts b/src/dts/imx8mq-mnt-reform2-hdmi.dts new file mode 100644 index 0000000..0abcfe8 --- /dev/null +++ b/src/dts/imx8mq-mnt-reform2-hdmi.dts @@ -0,0 +1,831 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* +* Copyright 2018 Boundary Devices +* Copyright 2019-2021 MNT Research GmbH +*/ + +/dts-v1/; + +#include "dt-bindings/input/input.h" +#include "dt-bindings/pwm/pwm.h" +#include "dt-bindings/usb/pd.h" +#include "dt-bindings/gpio/gpio.h" +#include "imx8mq.dtsi" + +/ { + model = "MNT Reform 2"; + compatible = "boundary,imx8mq-nitrogen8m_som", "fsl,imx8mq"; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + // 4GB of RAM + memory@40000000 { + device_type = "memory"; + reg = <0x00000000 0x40000000 0 0xc0000000>; // TODO: confirm what this means + }; + + reg_vref_0v9: regulator-vref-0v9 { + compatible = "regulator-fixed"; + regulator-name = "vref-0v9"; + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <900000>; + regulator-always-on; + }; + + reg_vref_1v2: regulator-vref-1v2 { + compatible = "regulator-fixed"; + regulator-name = "vref-1v2"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-always-on; + }; + + reg_vref_1v8: regulator-vref-1v8 { + compatible = "regulator-fixed"; + regulator-name = "vref-1v8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + }; + + reg_vref_2v5: regulator-vref-2v5 { + compatible = "regulator-fixed"; + regulator-name = "vref-2v5"; + regulator-min-microvolt = <2500000>; + regulator-max-microvolt = <2500000>; + regulator-always-on; + }; + + reg_vref_3v3: regulator-vref-3v3 { + compatible = "regulator-fixed"; + regulator-name = "vref-3v3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + reg_vref_5v: regulator-vref-5v { + compatible = "regulator-fixed"; + regulator-name = "vref-5v"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-always-on; + }; + + backlight: backlight { + compatible = "pwm-backlight"; + pwms = <&pwm2 0 10000>; + enable-gpios = <&gpio1 10 GPIO_ACTIVE_HIGH>; + brightness-levels = <0 32 64 128 160 200 255>; + default-brightness-level = <6>; + }; + + panel { + compatible = "innolux,n125hce-gn1", "simple-panel"; + power = <®_vref_3v3>; + backlight = <&backlight>; + no-hpd; + + port@0 { + panel_in: endpoint { + remote-endpoint = <&edp_bridge_out>; + }; + }; + }; + + sound { + compatible = "simple-audio-card"; + simple-audio-card,name = "wm8960-audio"; + simple-audio-card,format = "i2s"; + simple-audio-card,frame-master = <&dai_cpu_master>; + simple-audio-card,bitclock-master = <&dai_cpu_master>; + simple-audio-card,convert-rate = <48000>; + + simple-audio-card,widgets = + "Microphone", "Mic Jack", + "Line", "Line In", + "Line", "Line Out", + "Speaker", "Speaker", + "Headphone", "Headphone Jack"; + + simple-audio-card,routing = + "Headphone Jack", "HP_L", + "Headphone Jack", "HP_R", + "Speaker", "SPK_LP", + "Speaker", "SPK_LN", + "Speaker", "SPK_RP", + "Speaker", "SPK_RN", + "Mic Jack", "MICB", + "LINPUT1", "Mic Jack", + "LINPUT2", "Line In", + "RINPUT2", "Line In"; + + dai_cpu_master: simple-audio-card,cpu { + sound-dai = <&sai2>; + }; + + dailink0: simple-audio-card,codec { + sound-dai = <&codec>; + }; + }; + + pcie0_refclk: pcie0-refclk { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <100000000>; + }; + + pcie1_refclk: pcie1-refclk { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <100000000>; + }; +}; + +&A53_0 { + cpu-supply = <®_arm_dram>; +}; + +&A53_1 { + cpu-supply = <®_arm_dram>; +}; + +&A53_2 { + cpu-supply = <®_arm_dram>; +}; + +&A53_3 { + cpu-supply = <®_arm_dram>; +}; + +/ { + soc@0 { + bus@32c00000 { + + hdmi: hdmi@32c00000 { + status = "okay"; + + compatible = "cdn,imx8mq-hdmi"; + reg = <0x32c00000 0x100000>, + <0x32e40000 0x40000>; + interrupts = , + ; + interrupt-names = "plug_in", "plug_out"; + + lane-mapping = <0xe4>; // 0=0, 1=1, 2=2, 3=3 (no swapping) + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <0>; + hdmi_in: endpoint@0 { + reg = <0>; + remote-endpoint = <&dcss_hdmi_out>; + }; + }; + }; + }; + + dcss: display-controller@32e00000 { + status = "okay"; + + compatible = "nxp,imx8mq-dcss"; + reg = <0x32e00000 0x2d000>, <0x32e2f000 0x1000>; + interrupts = <6>, <8>, <9>; + interrupt-names = "ctxld", "ctxld_kick", "vblank"; + interrupt-parent = <&irqsteer>; + clocks = <&clk IMX8MQ_CLK_DISP_APB_ROOT>, + <&clk IMX8MQ_CLK_DISP_AXI_ROOT>, + <&clk IMX8MQ_CLK_DISP_RTRM_ROOT>, + <&clk IMX8MQ_VIDEO2_PLL_OUT>, + <&clk IMX8MQ_CLK_DISP_DTRC>, + <&clk IMX8MQ_VIDEO2_PLL1_REF_SEL>, + <&clk IMX8MQ_CLK_PHY_27MHZ>; + clock-names = "apb", "axi", "rtrm", "pix", "dtrc", "pll_src", "pll_phy_ref"; + assigned-clocks = <&clk IMX8MQ_CLK_DISP_AXI>, + <&clk IMX8MQ_CLK_DISP_RTRM>, + <&clk IMX8MQ_VIDEO2_PLL1_REF_SEL>, + <&clk IMX8MQ_VIDEO_PLL1_REF_SEL>, + <&clk IMX8MQ_CLK_DC_PIXEL>; + assigned-clock-parents = <&clk IMX8MQ_SYS1_PLL_800M>, + <&clk IMX8MQ_SYS1_PLL_800M>, + <&clk IMX8MQ_CLK_27M>, + <&clk IMX8MQ_CLK_25M>, + <&clk IMX8MQ_VIDEO_PLL1_OUT>; + assigned-clock-rates = <800000000>, + <400000000>, + <27000000>, + <25000000>, + <594000000>; + + // external display (HDMI) + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <0>; + dcss_hdmi_out: endpoint@0 { + reg = <0>; + remote-endpoint = <&hdmi_in>; + }; + }; + }; + + }; + }; + }; +}; + +// internal display +&lcdif { + status = "okay"; + + port@0 { + lcdif_mipi_dsi: endpoint { + remote-endpoint = <&mipi_dsi_in>; + }; + }; +}; + +&dphy { + status = "okay"; +}; + +&fec1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_fec1>; + phy-mode = "rgmii-id"; + phy-handle = <ðphy0>; + fsl,magic-packet; + status = "okay"; + + mdio { + #address-cells = <1>; + #size-cells = <0>; + + ethphy0: ethernet-phy@4 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <4>; + interrupts = <&gpio1 11 IRQ_TYPE_LEVEL_LOW>; + reset-gpios = <&gpio1 9 GPIO_ACTIVE_LOW>; // TODO: useful? + }; + }; +}; + +&i2c1 { + clock-frequency = <400000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c1>; + status = "okay"; + + // I2C Mux on Nitrogen8M_SOM + i2cmux@70 { + compatible = "nxp,pca9546"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c1_pca9546>; + reg = <0x70>; + reset-gpios = <&gpio1 4 GPIO_ACTIVE_LOW>; + #address-cells = <1>; + #size-cells = <0>; + + i2c1a: i2c1@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <0>; + + // Regulator on Nitrogen8M_SOM + reg_arm_dram: fan53555@60 { + compatible = "fcs,fan53555"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_reg_arm_dram>; + reg = <0x60>; + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <1000000>; + regulator-ramp-delay = <8000>; + regulator-always-on; + vsel-gpios = <&gpio3 24 GPIO_ACTIVE_HIGH>; + }; + }; + + i2c1b: i2c1@1 { + reg = <1>; + #address-cells = <1>; + #size-cells = <0>; + + // Regulator on Nitrogen8M_SOM + reg_dram_1p1v: fan53555@60 { + compatible = "fcs,fan53555"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_reg_dram_1p1v>; + reg = <0x60>; + regulator-min-microvolt = <1100000>; + regulator-max-microvolt = <1100000>; + regulator-ramp-delay = <8000>; + regulator-always-on; + vsel-gpios = <&gpio2 11 GPIO_ACTIVE_HIGH>; + }; + }; + + i2c1c: i2c1@2 { + reg = <2>; + #address-cells = <1>; + #size-cells = <0>; + + // Regulator on Nitrogen8M_SOM + reg_soc_gpu_vpu: fan53555@60 { + compatible = "fcs,fan53555"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_reg_soc_gpu_vpu>; + reg = <0x60>; + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <1000000>; + regulator-ramp-delay = <8000>; + regulator-always-on; + vsel-gpios = <&gpio2 20 GPIO_ACTIVE_HIGH>; + }; + }; + + // No peripheral connected, available on DSI connector + i2c1d: i2c1@3 { + reg = <3>; + #address-cells = <1>; + #size-cells = <0>; + }; + }; +}; + +// No peripheral connected, available on CSI connector +&i2c2 { + status = "disabled"; +}; + +&i2c3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c3>; + status = "okay"; + + // Audio chip on motherboard + codec: wm8960@1a { + compatible = "wlf,wm8960"; + reg = <0x1a>; + clocks = <&clk IMX8MQ_CLK_SAI2>; + clock-names = "mclk"; + #sound-dai-cells = <0>; + }; + + // Realtime clock chip on motherboard + pcf8523: pcf8523@68 { + compatible = "nxp,pcf8523"; + reg = <0x68>; + }; +}; + +&i2c4 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c4>; + status = "okay"; + + // DSI to eDP converter on motherboard + edp_bridge: sn65dsi86@2c { + compatible = "ti,sn65dsi86"; + reg = <0x2c>; + enable-gpios = <&gpio3 20 GPIO_ACTIVE_HIGH>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + edp_bridge_in: endpoint { + remote-endpoint = <&mipi_dsi_out>; + }; + }; + + port@1 { + reg = <1>; + + edp_bridge_out: endpoint { + remote-endpoint = <&panel_in>; + }; + }; + }; + }; +}; + +// TODO: add external pin numbers +&iomuxc { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_hog>; + + pinctrl_hog: hoggrp { + fsl,pins = < + MX8MQ_IOMUXC_SAI5_RXC_GPIO3_IO20 0x19 // WL_EN on Nitrogen8M_SOM, pin 38, goes to /EN input of SN65DSI86 + MX8MQ_IOMUXC_GPIO1_IO14_GPIO1_IO14 0x56 // TODO: check pullup of usb hub reset on the board (0x40) + >; + }; + + pinctrl_fec1: fec1grp { + fsl,pins = < + MX8MQ_IOMUXC_ENET_MDC_ENET1_MDC 0x3 + MX8MQ_IOMUXC_ENET_MDIO_ENET1_MDIO 0x23 + MX8MQ_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x1f + MX8MQ_IOMUXC_ENET_TXC_ENET1_RGMII_TXC 0x1f + MX8MQ_IOMUXC_ENET_TD0_ENET1_RGMII_TD0 0x1f + MX8MQ_IOMUXC_ENET_TD1_ENET1_RGMII_TD1 0x1f + MX8MQ_IOMUXC_ENET_TD2_ENET1_RGMII_TD2 0x1f + MX8MQ_IOMUXC_ENET_TD3_ENET1_RGMII_TD3 0x1f + MX8MQ_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x91 + MX8MQ_IOMUXC_ENET_RXC_ENET1_RGMII_RXC 0x91 + MX8MQ_IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x91 + MX8MQ_IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x91 + MX8MQ_IOMUXC_ENET_RD2_ENET1_RGMII_RD2 0x91 + MX8MQ_IOMUXC_ENET_RD3_ENET1_RGMII_RD3 0x91 + MX8MQ_IOMUXC_GPIO1_IO09_GPIO1_IO9 0x19 + MX8MQ_IOMUXC_GPIO1_IO11_GPIO1_IO11 0x59 + >; + }; + + pinctrl_i2c1: i2c1grp { + fsl,pins = < + MX8MQ_IOMUXC_I2C1_SCL_I2C1_SCL 0x4000007f + MX8MQ_IOMUXC_I2C1_SDA_I2C1_SDA 0x4000007f + >; + }; + + pinctrl_i2c1_pca9546: i2c1-pca9546grp { + fsl,pins = < + MX8MQ_IOMUXC_GPIO1_IO04_GPIO1_IO4 0x46 + >; + }; + + pinctrl_i2c2: i2c2grp { + fsl,pins = < + MX8MQ_IOMUXC_I2C2_SCL_I2C2_SCL 0x4000007f + MX8MQ_IOMUXC_I2C2_SDA_I2C2_SDA 0x4000007f + >; + }; + + pinctrl_i2c3: i2c3grp { + fsl,pins = < + MX8MQ_IOMUXC_I2C3_SCL_I2C3_SCL 0x4000007f + MX8MQ_IOMUXC_I2C3_SDA_I2C3_SDA 0x4000007f + >; + }; + + pinctrl_i2c4: i2c4grp { + fsl,pins = < + MX8MQ_IOMUXC_I2C4_SCL_I2C4_SCL 0x4000007f + MX8MQ_IOMUXC_I2C4_SDA_I2C4_SDA 0x4000007f + >; + }; + + pinctrl_pcie0: pcie0grp { + fsl,pins = < + MX8MQ_IOMUXC_ECSPI1_MOSI_GPIO5_IO7 0x16 + >; + }; + + pinctrl_pcie1: pcie1grp { + fsl,pins = < + MX8MQ_IOMUXC_SAI5_RXD2_GPIO3_IO23 0x16 + >; + }; + + pinctrl_pwm2: pwm2grp { + fsl,pins = < + MX8MQ_IOMUXC_SPDIF_RX_PWM2_OUT 0x16 + >; + }; + + pinctrl_pwm3: pwm3grp { + fsl,pins = < + MX8MQ_IOMUXC_SPDIF_TX_PWM3_OUT 0x16 + >; + }; + + // Backlight + pinctrl_pwm4: pwm4grp { + fsl,pins = < + MX8MQ_IOMUXC_SAI3_MCLK_PWM4_OUT 0x16 + >; + }; + + pinctrl_reg_arm_dram: reg-arm-dram { + fsl,pins = < + MX8MQ_IOMUXC_SAI5_RXD3_GPIO3_IO24 0x16 + >; + }; + + pinctrl_reg_dram_1p1v: reg-dram-1p1v { + fsl,pins = < + MX8MQ_IOMUXC_SD1_STROBE_GPIO2_IO11 0x16 + >; + }; + + pinctrl_reg_soc_gpu_vpu: reg-soc-gpu-vpu { + fsl,pins = < + MX8MQ_IOMUXC_SD2_WP_GPIO2_IO20 0x16 + >; + }; + + pinctrl_sai2: sai2grp { + fsl,pins = < + MX8MQ_IOMUXC_SAI2_RXD0_SAI2_RX_DATA0 0xd6 /* Pin 166 */ + MX8MQ_IOMUXC_SAI2_RXFS_SAI2_RX_SYNC 0xd6 /* Pin 168 */ + MX8MQ_IOMUXC_SAI2_TXC_SAI2_TX_BCLK 0xd6 /* Pin 170 */ + MX8MQ_IOMUXC_SAI2_TXFS_SAI2_TX_SYNC 0xd6 /* Pin 172 */ + MX8MQ_IOMUXC_SAI2_RXC_SAI2_RX_BCLK 0xd6 /* Pin 174 */ + MX8MQ_IOMUXC_SAI2_MCLK_SAI2_MCLK 0xd6 /* Pin 176 */ + MX8MQ_IOMUXC_SAI2_TXD0_SAI2_TX_DATA0 0xd6 /* Pin 168 */ + >; + }; + + pinctrl_uart1: uart1grp { + fsl,pins = < + MX8MQ_IOMUXC_UART1_RXD_UART1_DCE_RX 0x45 + MX8MQ_IOMUXC_UART1_TXD_UART1_DCE_TX 0x45 + >; + }; + + pinctrl_uart2: uart2grp { + fsl,pins = < + MX8MQ_IOMUXC_UART2_RXD_UART2_DCE_RX 0x45 + MX8MQ_IOMUXC_UART2_TXD_UART2_DCE_TX 0x45 + >; + }; + + pinctrl_uart3: uart3grp { + fsl,pins = < + MX8MQ_IOMUXC_UART3_RXD_UART3_DCE_RX 0x45 + MX8MQ_IOMUXC_UART3_TXD_UART3_DCE_TX 0x45 + >; + }; + + pinctrl_usdhc1: usdhc1grp { + fsl,pins = < + MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK 0x83 + MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD 0xc3 + MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0 0xc3 + MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1 0xc3 + MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2 0xc3 + MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3 0xc3 + MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4 0xc3 + MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5 0xc3 + MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6 0xc3 + MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7 0xc3 + MX8MQ_IOMUXC_SD1_RESET_B_GPIO2_IO10 0x41 + >; + }; + + pinctrl_usdhc1_100mhz: usdhc1-100mhzgrp { + fsl,pins = < + MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK 0x8d + MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD 0xcd + MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0 0xcd + MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1 0xcd + MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2 0xcd + MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3 0xcd + MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4 0xcd + MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5 0xcd + MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6 0xcd + MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7 0xcd + >; + }; + + pinctrl_usdhc1_200mhz: usdhc1-200mhzgrp { + fsl,pins = < + MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK 0x9f + MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD 0xdf + MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0 0xdf + MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1 0xdf + MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2 0xdf + MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3 0xdf + MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4 0xdf + MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5 0xdf + MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6 0xdf + MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7 0xdf + >; + }; + + pinctrl_usdhc2: usdhc2grp { + fsl,pins = < + MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK 0x03 + MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD 0xc3 + MX8MQ_IOMUXC_SD2_DATA0_USDHC2_DATA0 0xc3 + MX8MQ_IOMUXC_SD2_DATA1_USDHC2_DATA1 0xc3 + MX8MQ_IOMUXC_SD2_DATA2_USDHC2_DATA2 0xc3 + MX8MQ_IOMUXC_SD2_DATA3_USDHC2_DATA3 0xc + >; + }; + + pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp { + fsl,pins = < + MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK 0x0d + MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD 0xcd + MX8MQ_IOMUXC_SD2_DATA0_USDHC2_DATA0 0xcd + MX8MQ_IOMUXC_SD2_DATA1_USDHC2_DATA1 0xcd + MX8MQ_IOMUXC_SD2_DATA2_USDHC2_DATA2 0xcd + MX8MQ_IOMUXC_SD2_DATA3_USDHC2_DATA3 0xcd + >; + }; + + pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp { + fsl,pins = < + MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK 0x1e + MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD 0xce + MX8MQ_IOMUXC_SD2_DATA0_USDHC2_DATA0 0xce + MX8MQ_IOMUXC_SD2_DATA1_USDHC2_DATA1 0xce + MX8MQ_IOMUXC_SD2_DATA2_USDHC2_DATA2 0xce + MX8MQ_IOMUXC_SD2_DATA3_USDHC2_DATA3 0xce + >; + }; + + pinctrl_wdog: wdoggrp { + fsl,pins = < + MX8MQ_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B 0xc6 + >; + }; +}; + +&mipi_dsi { + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + + mipi_dsi_in: endpoint@0 { + reg = <0>; + remote-endpoint = <&lcdif_mipi_dsi>; + }; + }; + port@1 { + reg = <1>; + mipi_dsi_out: endpoint { + remote-endpoint = <&edp_bridge_in>; + }; + }; + }; +}; + +&pcie0 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pcie0>; + reset-gpio = <&gpio5 7 GPIO_ACTIVE_LOW>; + internal-refclk; + + clocks = <&clk IMX8MQ_CLK_PCIE1_ROOT>, + <&clk IMX8MQ_CLK_PCIE1_AUX>, + <&clk IMX8MQ_CLK_PCIE1_PHY>, + <&pcie0_refclk>; + + clock-names = "pcie", "pcie_aux", "pcie_phy", "pcie_bus"; + + assigned-clocks = <&clk IMX8MQ_CLK_PCIE1_CTRL>, + <&clk IMX8MQ_CLK_PCIE1_PHY>; + assigned-clock-parents = <&clk IMX8MQ_SYS2_PLL_250M>, + <&clk IMX8MQ_SYS2_PLL_100M>; + + status = "okay"; +}; + +&pcie1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pcie1>; + reset-gpio = <&gpio3 23 GPIO_ACTIVE_LOW>; + + clocks = <&clk IMX8MQ_CLK_PCIE2_ROOT>, + <&clk IMX8MQ_CLK_PCIE2_AUX>, + <&clk IMX8MQ_CLK_PCIE2_PHY>, + <&pcie1_refclk>; + clock-names = "pcie", "pcie_aux", "pcie_phy", "pcie_bus"; + status = "okay"; +}; + +&pwm2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm2>; + status = "okay"; +}; + +&pwm3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm3>; + status = "okay"; +}; + +// Backlight control +&pwm4 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm4>; + status = "okay"; +}; + +&sai2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_sai2>; + assigned-clocks = <&clk IMX8MQ_CLK_SAI2>; + assigned-clock-parents = <&clk IMX8MQ_AUDIO_PLL1_OUT>; + assigned-clock-rates = <12288000>; + status = "okay"; + fsl,sai-asynchronous; +}; + +// Don't use i.MX8M internal RTC because we have a dedicated one +&snvs_rtc { + status = "disabled"; +}; + +// Console +&uart1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart1>; + status = "okay"; +}; + +// Auxiliary serial port on motherboard +&uart2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart2>; + status = "okay"; +}; + +// connected to LPC11U24 chip on the motherboard +&uart3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart3>; + status = "okay"; +}; + +&usb_dwc3_0 { + status = "okay"; + dr_mode = "host"; +}; + +&usb_dwc3_1 { + status = "okay"; + dr_mode = "host"; +}; + +&usb3_phy0 { + vbus-supply = <®_vref_5v>; + status = "okay"; +}; + +&usb3_phy1 { + vbus-supply = <®_vref_5v>; + status = "okay"; +}; + +// eMMC on Nitrogen8M_SOM +// TODO: HS currently doesn't work +&usdhc1 { + bus-width = <8>; + fsl,strobe-dll-delay-target = <5>; + fsl,tuning-start-tap = <63>; + fsl,tuning-step = <2>; + non-removable; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc1>; + vmmc-supply = <®_vref_1v8>; + vqmmc-1-8-v; + status = "okay"; +}; + +// SD Card on motherboard +// TODO: check keep-power-in-suspend, cap-sdio-irq +&usdhc2 { + assigned-clocks = <&clk IMX8MQ_CLK_USDHC2>; + assigned-clock-rates = <200000000>; + bus-width = <4>; + no-1-8-v; // We don't support 1.8V signaling + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc2>; + pinctrl-1 = <&pinctrl_usdhc2_100mhz>; + pinctrl-2 = <&pinctrl_usdhc2_200mhz>; + vmmc-supply = <®_vref_3v3>; + status = "okay"; +}; + +&wdog1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_wdog>; + fsl,ext-reset-output; // TODO check source for what this means + status = "okay"; +}; diff --git a/src/dts/imx8mq-mnt-reform2.dts b/src/dts/imx8mq-mnt-reform2.dts new file mode 100644 index 0000000..0783188 --- /dev/null +++ b/src/dts/imx8mq-mnt-reform2.dts @@ -0,0 +1,799 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* +* Copyright 2018 Boundary Devices +* Copyright 2019-2021 MNT Research GmbH +*/ + +/dts-v1/; + +#include "dt-bindings/input/input.h" +#include "dt-bindings/pwm/pwm.h" +#include "dt-bindings/usb/pd.h" +#include "dt-bindings/gpio/gpio.h" +#include "imx8mq.dtsi" + +/ { + model = "MNT Reform 2"; + compatible = "boundary,imx8mq-nitrogen8m_som", "fsl,imx8mq"; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + // 4GB of RAM + memory@40000000 { + device_type = "memory"; + reg = <0x00000000 0x40000000 0 0xc0000000>; // TODO: confirm what this means + }; + + reg_vref_0v9: regulator-vref-0v9 { + compatible = "regulator-fixed"; + regulator-name = "vref-0v9"; + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <900000>; + regulator-always-on; + }; + + reg_vref_1v2: regulator-vref-1v2 { + compatible = "regulator-fixed"; + regulator-name = "vref-1v2"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-always-on; + }; + + reg_vref_1v8: regulator-vref-1v8 { + compatible = "regulator-fixed"; + regulator-name = "vref-1v8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + }; + + reg_vref_2v5: regulator-vref-2v5 { + compatible = "regulator-fixed"; + regulator-name = "vref-2v5"; + regulator-min-microvolt = <2500000>; + regulator-max-microvolt = <2500000>; + regulator-always-on; + }; + + reg_vref_3v3: regulator-vref-3v3 { + compatible = "regulator-fixed"; + regulator-name = "vref-3v3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + reg_vref_5v: regulator-vref-5v { + compatible = "regulator-fixed"; + regulator-name = "vref-5v"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-always-on; + }; + + backlight: backlight { + compatible = "pwm-backlight"; + pwms = <&pwm2 0 10000>; + enable-gpios = <&gpio1 10 GPIO_ACTIVE_HIGH>; + brightness-levels = <0 32 64 128 160 200 255>; + default-brightness-level = <6>; + }; + + panel { + compatible = "innolux,n125hce-gn1", "simple-panel"; + power = <®_vref_3v3>; + backlight = <&backlight>; + no-hpd; + + port@0 { + panel_in: endpoint { + remote-endpoint = <&edp_bridge_out>; + }; + }; + }; + + sound { + compatible = "simple-audio-card"; + simple-audio-card,name = "wm8960-audio"; + simple-audio-card,format = "i2s"; + simple-audio-card,frame-master = <&dai_cpu_master>; + simple-audio-card,bitclock-master = <&dai_cpu_master>; + simple-audio-card,convert-rate = <48000>; + + simple-audio-card,widgets = + "Microphone", "Mic Jack", + "Line", "Line In", + "Line", "Line Out", + "Speaker", "Speaker", + "Headphone", "Headphone Jack"; + + simple-audio-card,routing = + "Headphone Jack", "HP_L", + "Headphone Jack", "HP_R", + "Speaker", "SPK_LP", + "Speaker", "SPK_LN", + "Speaker", "SPK_RP", + "Speaker", "SPK_RN", + "Mic Jack", "MICB", + "LINPUT1", "Mic Jack", + "LINPUT2", "Line In", + "RINPUT2", "Line In"; + + dai_cpu_master: simple-audio-card,cpu { + sound-dai = <&sai2>; + }; + + dailink0: simple-audio-card,codec { + sound-dai = <&codec>; + }; + }; + + pcie0_refclk: pcie0-refclk { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <100000000>; + }; + + pcie1_refclk: pcie1-refclk { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <100000000>; + }; +}; + +&A53_0 { + cpu-supply = <®_arm_dram>; +}; + +&A53_1 { + cpu-supply = <®_arm_dram>; +}; + +&A53_2 { + cpu-supply = <®_arm_dram>; +}; + +&A53_3 { + cpu-supply = <®_arm_dram>; +}; + +/ { + soc@0 { + bus@32c00000 { + dcss: display-controller@32e00000 { + status = "okay"; + + compatible = "nxp,imx8mq-dcss"; + reg = <0x32e00000 0x2d000>, <0x32e2f000 0x1000>; + interrupts = <6>, <8>, <9>; + interrupt-names = "ctxld", "ctxld_kick", "vblank"; + interrupt-parent = <&irqsteer>; + clocks = <&clk IMX8MQ_CLK_DISP_APB_ROOT>, + <&clk IMX8MQ_CLK_DISP_AXI_ROOT>, + <&clk IMX8MQ_CLK_DISP_RTRM_ROOT>, + <&clk IMX8MQ_CLK_DC_PIXEL>, + <&clk IMX8MQ_CLK_DISP_DTRC>, + <&clk IMX8MQ_VIDEO2_PLL1_REF_SEL>, + <&clk IMX8MQ_CLK_PHY_27MHZ>; + clock-names = "apb", "axi", "rtrm", "pix", "dtrc", "pll_src", "pll_phy_ref"; + assigned-clocks = <&clk IMX8MQ_CLK_DISP_AXI>, + <&clk IMX8MQ_CLK_DISP_RTRM>, + <&clk IMX8MQ_VIDEO2_PLL1_REF_SEL>, + <&clk IMX8MQ_VIDEO_PLL1_REF_SEL>, + <&clk IMX8MQ_CLK_DC_PIXEL>; + assigned-clock-parents = <&clk IMX8MQ_SYS1_PLL_800M>, + <&clk IMX8MQ_SYS1_PLL_800M>, + <&clk IMX8MQ_CLK_27M>, + <&clk IMX8MQ_CLK_25M>, + <&clk IMX8MQ_VIDEO_PLL1_OUT>; + assigned-clock-rates = <800000000>, + <400000000>, + <27000000>, + <25000000>, + <594000000>; + + // internal display (MIPI-DSI/eDP) + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <0>; + dcss_dsi_out: endpoint@0 { + reg = <0>; + remote-endpoint = <&mipi_dsi_in>; + }; + }; + }; + }; + }; + }; +}; + +// LCDIF is not used, but has to be active or DCSS won't work +&lcdif { + status = "okay"; + /delete-node/ port@0; +}; + +&dphy { + status = "okay"; +}; + +&fec1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_fec1>; + phy-mode = "rgmii-id"; + phy-handle = <ðphy0>; + fsl,magic-packet; + status = "okay"; + + mdio { + #address-cells = <1>; + #size-cells = <0>; + + ethphy0: ethernet-phy@4 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <4>; + interrupts = <&gpio1 11 IRQ_TYPE_LEVEL_LOW>; + reset-gpios = <&gpio1 9 GPIO_ACTIVE_LOW>; // TODO: useful? + }; + }; +}; + +&i2c1 { + clock-frequency = <400000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c1>; + status = "okay"; + + // I2C Mux on Nitrogen8M_SOM + i2cmux@70 { + compatible = "nxp,pca9546"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c1_pca9546>; + reg = <0x70>; + reset-gpios = <&gpio1 4 GPIO_ACTIVE_LOW>; + #address-cells = <1>; + #size-cells = <0>; + + i2c1a: i2c1@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <0>; + + // Regulator on Nitrogen8M_SOM + reg_arm_dram: fan53555@60 { + compatible = "fcs,fan53555"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_reg_arm_dram>; + reg = <0x60>; + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <1000000>; + regulator-ramp-delay = <8000>; + regulator-always-on; + vsel-gpios = <&gpio3 24 GPIO_ACTIVE_HIGH>; + }; + }; + + i2c1b: i2c1@1 { + reg = <1>; + #address-cells = <1>; + #size-cells = <0>; + + // Regulator on Nitrogen8M_SOM + reg_dram_1p1v: fan53555@60 { + compatible = "fcs,fan53555"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_reg_dram_1p1v>; + reg = <0x60>; + regulator-min-microvolt = <1100000>; + regulator-max-microvolt = <1100000>; + regulator-ramp-delay = <8000>; + regulator-always-on; + vsel-gpios = <&gpio2 11 GPIO_ACTIVE_HIGH>; + }; + }; + + i2c1c: i2c1@2 { + reg = <2>; + #address-cells = <1>; + #size-cells = <0>; + + // Regulator on Nitrogen8M_SOM + reg_soc_gpu_vpu: fan53555@60 { + compatible = "fcs,fan53555"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_reg_soc_gpu_vpu>; + reg = <0x60>; + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <1000000>; + regulator-ramp-delay = <8000>; + regulator-always-on; + vsel-gpios = <&gpio2 20 GPIO_ACTIVE_HIGH>; + }; + }; + + // No peripheral connected, available on DSI connector + i2c1d: i2c1@3 { + reg = <3>; + #address-cells = <1>; + #size-cells = <0>; + }; + }; +}; + +// No peripheral connected, available on CSI connector +&i2c2 { + status = "disabled"; +}; + +&i2c3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c3>; + status = "okay"; + + // Audio chip on motherboard + codec: wm8960@1a { + compatible = "wlf,wm8960"; + reg = <0x1a>; + clocks = <&clk IMX8MQ_CLK_SAI2>; + clock-names = "mclk"; + #sound-dai-cells = <0>; + }; + + // Realtime clock chip on motherboard + pcf8523: pcf8523@68 { + compatible = "nxp,pcf8523"; + reg = <0x68>; + }; +}; + +&i2c4 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c4>; + status = "okay"; + + // DSI to eDP converter on motherboard + edp_bridge: sn65dsi86@2c { + compatible = "ti,sn65dsi86"; + reg = <0x2c>; + enable-gpios = <&gpio3 20 GPIO_ACTIVE_HIGH>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + edp_bridge_in: endpoint { + remote-endpoint = <&mipi_dsi_out>; + }; + }; + + port@1 { + reg = <1>; + + edp_bridge_out: endpoint { + remote-endpoint = <&panel_in>; + }; + }; + }; + }; +}; + +// TODO: add external pin numbers +&iomuxc { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_hog>; + + pinctrl_hog: hoggrp { + fsl,pins = < + MX8MQ_IOMUXC_SAI5_RXC_GPIO3_IO20 0x19 // WL_EN on Nitrogen8M_SOM, pin 38, goes to /EN input of SN65DSI86 + MX8MQ_IOMUXC_GPIO1_IO14_GPIO1_IO14 0x56 // TODO: check pullup of usb hub reset on the board (0x40) + >; + }; + + pinctrl_fec1: fec1grp { + fsl,pins = < + MX8MQ_IOMUXC_ENET_MDC_ENET1_MDC 0x3 + MX8MQ_IOMUXC_ENET_MDIO_ENET1_MDIO 0x23 + MX8MQ_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x1f + MX8MQ_IOMUXC_ENET_TXC_ENET1_RGMII_TXC 0x1f + MX8MQ_IOMUXC_ENET_TD0_ENET1_RGMII_TD0 0x1f + MX8MQ_IOMUXC_ENET_TD1_ENET1_RGMII_TD1 0x1f + MX8MQ_IOMUXC_ENET_TD2_ENET1_RGMII_TD2 0x1f + MX8MQ_IOMUXC_ENET_TD3_ENET1_RGMII_TD3 0x1f + MX8MQ_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x91 + MX8MQ_IOMUXC_ENET_RXC_ENET1_RGMII_RXC 0x91 + MX8MQ_IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x91 + MX8MQ_IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x91 + MX8MQ_IOMUXC_ENET_RD2_ENET1_RGMII_RD2 0x91 + MX8MQ_IOMUXC_ENET_RD3_ENET1_RGMII_RD3 0x91 + MX8MQ_IOMUXC_GPIO1_IO09_GPIO1_IO9 0x19 + MX8MQ_IOMUXC_GPIO1_IO11_GPIO1_IO11 0x59 + >; + }; + + pinctrl_i2c1: i2c1grp { + fsl,pins = < + MX8MQ_IOMUXC_I2C1_SCL_I2C1_SCL 0x4000007f + MX8MQ_IOMUXC_I2C1_SDA_I2C1_SDA 0x4000007f + >; + }; + + pinctrl_i2c1_pca9546: i2c1-pca9546grp { + fsl,pins = < + MX8MQ_IOMUXC_GPIO1_IO04_GPIO1_IO4 0x46 + >; + }; + + pinctrl_i2c2: i2c2grp { + fsl,pins = < + MX8MQ_IOMUXC_I2C2_SCL_I2C2_SCL 0x4000007f + MX8MQ_IOMUXC_I2C2_SDA_I2C2_SDA 0x4000007f + >; + }; + + pinctrl_i2c3: i2c3grp { + fsl,pins = < + MX8MQ_IOMUXC_I2C3_SCL_I2C3_SCL 0x4000007f + MX8MQ_IOMUXC_I2C3_SDA_I2C3_SDA 0x4000007f + >; + }; + + pinctrl_i2c4: i2c4grp { + fsl,pins = < + MX8MQ_IOMUXC_I2C4_SCL_I2C4_SCL 0x4000007f + MX8MQ_IOMUXC_I2C4_SDA_I2C4_SDA 0x4000007f + >; + }; + + pinctrl_pcie0: pcie0grp { + fsl,pins = < + MX8MQ_IOMUXC_ECSPI1_MOSI_GPIO5_IO7 0x16 + >; + }; + + pinctrl_pcie1: pcie1grp { + fsl,pins = < + MX8MQ_IOMUXC_SAI5_RXD2_GPIO3_IO23 0x16 + >; + }; + + pinctrl_pwm2: pwm2grp { + fsl,pins = < + MX8MQ_IOMUXC_SPDIF_RX_PWM2_OUT 0x16 + >; + }; + + pinctrl_pwm3: pwm3grp { + fsl,pins = < + MX8MQ_IOMUXC_SPDIF_TX_PWM3_OUT 0x16 + >; + }; + + // Backlight + pinctrl_pwm4: pwm4grp { + fsl,pins = < + MX8MQ_IOMUXC_SAI3_MCLK_PWM4_OUT 0x16 + >; + }; + + pinctrl_reg_arm_dram: reg-arm-dram { + fsl,pins = < + MX8MQ_IOMUXC_SAI5_RXD3_GPIO3_IO24 0x16 + >; + }; + + pinctrl_reg_dram_1p1v: reg-dram-1p1v { + fsl,pins = < + MX8MQ_IOMUXC_SD1_STROBE_GPIO2_IO11 0x16 + >; + }; + + pinctrl_reg_soc_gpu_vpu: reg-soc-gpu-vpu { + fsl,pins = < + MX8MQ_IOMUXC_SD2_WP_GPIO2_IO20 0x16 + >; + }; + + pinctrl_sai2: sai2grp { + fsl,pins = < + MX8MQ_IOMUXC_SAI2_RXD0_SAI2_RX_DATA0 0xd6 /* Pin 166 */ + MX8MQ_IOMUXC_SAI2_RXFS_SAI2_RX_SYNC 0xd6 /* Pin 168 */ + MX8MQ_IOMUXC_SAI2_TXC_SAI2_TX_BCLK 0xd6 /* Pin 170 */ + MX8MQ_IOMUXC_SAI2_TXFS_SAI2_TX_SYNC 0xd6 /* Pin 172 */ + MX8MQ_IOMUXC_SAI2_RXC_SAI2_RX_BCLK 0xd6 /* Pin 174 */ + MX8MQ_IOMUXC_SAI2_MCLK_SAI2_MCLK 0xd6 /* Pin 176 */ + MX8MQ_IOMUXC_SAI2_TXD0_SAI2_TX_DATA0 0xd6 /* Pin 168 */ + >; + }; + + pinctrl_uart1: uart1grp { + fsl,pins = < + MX8MQ_IOMUXC_UART1_RXD_UART1_DCE_RX 0x45 + MX8MQ_IOMUXC_UART1_TXD_UART1_DCE_TX 0x45 + >; + }; + + pinctrl_uart2: uart2grp { + fsl,pins = < + MX8MQ_IOMUXC_UART2_RXD_UART2_DCE_RX 0x45 + MX8MQ_IOMUXC_UART2_TXD_UART2_DCE_TX 0x45 + >; + }; + + pinctrl_uart3: uart3grp { + fsl,pins = < + MX8MQ_IOMUXC_UART3_RXD_UART3_DCE_RX 0x45 + MX8MQ_IOMUXC_UART3_TXD_UART3_DCE_TX 0x45 + >; + }; + + pinctrl_usdhc1: usdhc1grp { + fsl,pins = < + MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK 0x83 + MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD 0xc3 + MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0 0xc3 + MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1 0xc3 + MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2 0xc3 + MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3 0xc3 + MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4 0xc3 + MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5 0xc3 + MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6 0xc3 + MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7 0xc3 + MX8MQ_IOMUXC_SD1_RESET_B_GPIO2_IO10 0x41 + >; + }; + + pinctrl_usdhc1_100mhz: usdhc1-100mhzgrp { + fsl,pins = < + MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK 0x8d + MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD 0xcd + MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0 0xcd + MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1 0xcd + MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2 0xcd + MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3 0xcd + MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4 0xcd + MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5 0xcd + MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6 0xcd + MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7 0xcd + >; + }; + + pinctrl_usdhc1_200mhz: usdhc1-200mhzgrp { + fsl,pins = < + MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK 0x9f + MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD 0xdf + MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0 0xdf + MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1 0xdf + MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2 0xdf + MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3 0xdf + MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4 0xdf + MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5 0xdf + MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6 0xdf + MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7 0xdf + >; + }; + + pinctrl_usdhc2: usdhc2grp { + fsl,pins = < + MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK 0x03 + MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD 0xc3 + MX8MQ_IOMUXC_SD2_DATA0_USDHC2_DATA0 0xc3 + MX8MQ_IOMUXC_SD2_DATA1_USDHC2_DATA1 0xc3 + MX8MQ_IOMUXC_SD2_DATA2_USDHC2_DATA2 0xc3 + MX8MQ_IOMUXC_SD2_DATA3_USDHC2_DATA3 0xc + >; + }; + + pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp { + fsl,pins = < + MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK 0x0d + MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD 0xcd + MX8MQ_IOMUXC_SD2_DATA0_USDHC2_DATA0 0xcd + MX8MQ_IOMUXC_SD2_DATA1_USDHC2_DATA1 0xcd + MX8MQ_IOMUXC_SD2_DATA2_USDHC2_DATA2 0xcd + MX8MQ_IOMUXC_SD2_DATA3_USDHC2_DATA3 0xcd + >; + }; + + pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp { + fsl,pins = < + MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK 0x1e + MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD 0xce + MX8MQ_IOMUXC_SD2_DATA0_USDHC2_DATA0 0xce + MX8MQ_IOMUXC_SD2_DATA1_USDHC2_DATA1 0xce + MX8MQ_IOMUXC_SD2_DATA2_USDHC2_DATA2 0xce + MX8MQ_IOMUXC_SD2_DATA3_USDHC2_DATA3 0xce + >; + }; + + pinctrl_wdog: wdoggrp { + fsl,pins = < + MX8MQ_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B 0xc6 + >; + }; +}; + +&mipi_dsi { + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + + // We don't want input from LCDIF + /delete-node/ endpoint@0; + + mipi_dsi_in: endpoint@1 { + reg = <1>; + remote-endpoint = <&dcss_dsi_out>; + }; + }; + port@1 { + reg = <1>; + mipi_dsi_out: endpoint { + remote-endpoint = <&edp_bridge_in>; + }; + }; + }; +}; + +&pcie0 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pcie0>; + reset-gpio = <&gpio5 7 GPIO_ACTIVE_LOW>; + internal-refclk; + + clocks = <&clk IMX8MQ_CLK_PCIE1_ROOT>, + <&clk IMX8MQ_CLK_PCIE1_AUX>, + <&clk IMX8MQ_CLK_PCIE1_PHY>, + <&pcie0_refclk>; + + clock-names = "pcie", "pcie_aux", "pcie_phy", "pcie_bus"; + + assigned-clocks = <&clk IMX8MQ_CLK_PCIE1_CTRL>, + <&clk IMX8MQ_CLK_PCIE1_PHY>; + assigned-clock-parents = <&clk IMX8MQ_SYS2_PLL_250M>, + <&clk IMX8MQ_SYS2_PLL_100M>; + + status = "okay"; +}; + +&pcie1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pcie1>; + reset-gpio = <&gpio3 23 GPIO_ACTIVE_LOW>; + + clocks = <&clk IMX8MQ_CLK_PCIE2_ROOT>, + <&clk IMX8MQ_CLK_PCIE2_AUX>, + <&clk IMX8MQ_CLK_PCIE2_PHY>, + <&pcie1_refclk>; + clock-names = "pcie", "pcie_aux", "pcie_phy", "pcie_bus"; + status = "okay"; +}; + +&pwm2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm2>; + status = "okay"; +}; + +&pwm3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm3>; + status = "okay"; +}; + +// Backlight control +&pwm4 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm4>; + status = "okay"; +}; + +&sai2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_sai2>; + assigned-clocks = <&clk IMX8MQ_CLK_SAI2>; + assigned-clock-parents = <&clk IMX8MQ_AUDIO_PLL1_OUT>; + assigned-clock-rates = <12288000>; + fsl,sai-asynchronous; + status = "okay"; +}; + +// Don't use i.MX8M internal RTC because we have a dedicated one +&snvs_rtc { + status = "disabled"; +}; + +// Console +&uart1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart1>; + status = "okay"; +}; + +// Auxiliary serial port on motherboard +&uart2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart2>; + status = "okay"; +}; + +// connected to LPC11U24 chip on the motherboard +&uart3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart3>; + status = "okay"; +}; + +&usb_dwc3_0 { + status = "okay"; + dr_mode = "host"; +}; + +&usb_dwc3_1 { + status = "okay"; + dr_mode = "host"; +}; + +&usb3_phy0 { + vbus-supply = <®_vref_5v>; + status = "okay"; +}; + +&usb3_phy1 { + vbus-supply = <®_vref_5v>; + status = "okay"; +}; + +// eMMC on Nitrogen8M_SOM +// TODO: HS currently doesn't work +&usdhc1 { + bus-width = <8>; + fsl,strobe-dll-delay-target = <5>; + fsl,tuning-start-tap = <63>; + fsl,tuning-step = <2>; + non-removable; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc1>; + vmmc-supply = <®_vref_1v8>; + vqmmc-1-8-v; + status = "okay"; +}; + +// SD Card on motherboard +// TODO: check keep-power-in-suspend, cap-sdio-irq +&usdhc2 { + assigned-clocks = <&clk IMX8MQ_CLK_USDHC2>; + assigned-clock-rates = <200000000>; + bus-width = <4>; + no-1-8-v; // We don't support 1.8V signaling + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc2>; + pinctrl-1 = <&pinctrl_usdhc2_100mhz>; + pinctrl-2 = <&pinctrl_usdhc2_200mhz>; + vmmc-supply = <®_vref_3v3>; + status = "okay"; +}; + +&wdog1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_wdog>; + fsl,ext-reset-output; // TODO check source for what this means + status = "okay"; +}; diff --git a/src/kernel-config b/src/kernel-config new file mode 100644 index 0000000..c3f9144 --- /dev/null +++ b/src/kernel-config @@ -0,0 +1,6131 @@ +# +# Automatically generated file; DO NOT EDIT. +# Linux/arm64 5.11.0-rc7 Kernel Configuration +# +CONFIG_CC_VERSION_TEXT="aarch64-linux-gnu-gcc (Debian 10.2.1-1) 10.2.1 20201207" +CONFIG_CC_IS_GCC=y +CONFIG_GCC_VERSION=100201 +CONFIG_LD_VERSION=235010000 +CONFIG_CLANG_VERSION=0 +CONFIG_LLD_VERSION=0 +CONFIG_CC_CAN_LINK=y +CONFIG_CC_CAN_LINK_STATIC=y +CONFIG_CC_HAS_ASM_GOTO=y +CONFIG_CC_HAS_ASM_INLINE=y +CONFIG_IRQ_WORK=y +CONFIG_BUILDTIME_TABLE_SORT=y +CONFIG_THREAD_INFO_IN_TASK=y + +# +# General setup +# +CONFIG_INIT_ENV_ARG_LIMIT=32 +# CONFIG_COMPILE_TEST is not set +CONFIG_LOCALVERSION="" +# CONFIG_LOCALVERSION_AUTO is not set +CONFIG_BUILD_SALT="4.20.0-trunk-amd64" +CONFIG_DEFAULT_INIT="" +CONFIG_DEFAULT_HOSTNAME="(none)" +CONFIG_SWAP=y +CONFIG_SYSVIPC=y +CONFIG_SYSVIPC_SYSCTL=y +CONFIG_POSIX_MQUEUE=y +CONFIG_POSIX_MQUEUE_SYSCTL=y +# CONFIG_WATCH_QUEUE is not set +CONFIG_CROSS_MEMORY_ATTACH=y +CONFIG_USELIB=y +CONFIG_AUDIT=y +CONFIG_HAVE_ARCH_AUDITSYSCALL=y +CONFIG_AUDITSYSCALL=y + +# +# IRQ subsystem +# +CONFIG_GENERIC_IRQ_PROBE=y +CONFIG_GENERIC_IRQ_SHOW=y +CONFIG_GENERIC_IRQ_SHOW_LEVEL=y +CONFIG_GENERIC_IRQ_EFFECTIVE_AFF_MASK=y +CONFIG_GENERIC_IRQ_MIGRATION=y +CONFIG_GENERIC_IRQ_INJECTION=y +CONFIG_HARDIRQS_SW_RESEND=y +CONFIG_GENERIC_IRQ_CHIP=y +CONFIG_IRQ_DOMAIN=y +CONFIG_IRQ_DOMAIN_HIERARCHY=y +CONFIG_GENERIC_IRQ_IPI=y +CONFIG_GENERIC_MSI_IRQ=y +CONFIG_GENERIC_MSI_IRQ_DOMAIN=y +CONFIG_IRQ_MSI_IOMMU=y +CONFIG_HANDLE_DOMAIN_IRQ=y +CONFIG_IRQ_FORCED_THREADING=y +CONFIG_SPARSE_IRQ=y +CONFIG_GENERIC_IRQ_DEBUGFS=y +# end of IRQ subsystem + +CONFIG_GENERIC_IRQ_MULTI_HANDLER=y +CONFIG_GENERIC_TIME_VSYSCALL=y +CONFIG_GENERIC_CLOCKEVENTS=y +CONFIG_ARCH_HAS_TICK_BROADCAST=y +CONFIG_GENERIC_CLOCKEVENTS_BROADCAST=y + +# +# Timers subsystem +# +CONFIG_TICK_ONESHOT=y +CONFIG_NO_HZ_COMMON=y +# CONFIG_HZ_PERIODIC is not set +CONFIG_NO_HZ_IDLE=y +# CONFIG_NO_HZ_FULL is not set +# CONFIG_NO_HZ is not set +CONFIG_HIGH_RES_TIMERS=y +# end of Timers subsystem + +# CONFIG_PREEMPT_NONE is not set +# CONFIG_PREEMPT_VOLUNTARY is not set +CONFIG_PREEMPT=y +CONFIG_PREEMPT_COUNT=y +CONFIG_PREEMPTION=y + +# +# CPU/Task time and stats accounting +# +CONFIG_TICK_CPU_ACCOUNTING=y +# CONFIG_VIRT_CPU_ACCOUNTING_GEN is not set +# CONFIG_IRQ_TIME_ACCOUNTING is not set +CONFIG_SCHED_THERMAL_PRESSURE=y +CONFIG_BSD_PROCESS_ACCT=y +CONFIG_BSD_PROCESS_ACCT_V3=y +CONFIG_TASKSTATS=y +CONFIG_TASK_DELAY_ACCT=y +CONFIG_TASK_XACCT=y +CONFIG_TASK_IO_ACCOUNTING=y +# CONFIG_PSI is not set +# end of CPU/Task time and stats accounting + +CONFIG_CPU_ISOLATION=y + +# +# RCU Subsystem +# +CONFIG_TREE_RCU=y +CONFIG_PREEMPT_RCU=y +# CONFIG_RCU_EXPERT is not set +CONFIG_SRCU=y +CONFIG_TREE_SRCU=y +CONFIG_TASKS_RCU_GENERIC=y +CONFIG_TASKS_RCU=y +CONFIG_TASKS_RUDE_RCU=y +CONFIG_TASKS_TRACE_RCU=y +CONFIG_RCU_STALL_COMMON=y +CONFIG_RCU_NEED_SEGCBLIST=y +# end of RCU Subsystem + +CONFIG_IKCONFIG=y +CONFIG_IKCONFIG_PROC=y +# CONFIG_IKHEADERS is not set +CONFIG_LOG_BUF_SHIFT=17 +CONFIG_LOG_CPU_MAX_BUF_SHIFT=12 +CONFIG_PRINTK_SAFE_LOG_BUF_SHIFT=13 +CONFIG_GENERIC_SCHED_CLOCK=y + +# +# Scheduler features +# +# CONFIG_UCLAMP_TASK is not set +# end of Scheduler features + +CONFIG_ARCH_SUPPORTS_NUMA_BALANCING=y +CONFIG_CC_HAS_INT128=y +CONFIG_ARCH_SUPPORTS_INT128=y +CONFIG_NUMA_BALANCING=y +CONFIG_NUMA_BALANCING_DEFAULT_ENABLED=y +CONFIG_CGROUPS=y +CONFIG_PAGE_COUNTER=y +CONFIG_MEMCG=y +CONFIG_MEMCG_SWAP=y +CONFIG_MEMCG_KMEM=y +CONFIG_BLK_CGROUP=y +CONFIG_CGROUP_WRITEBACK=y +CONFIG_CGROUP_SCHED=y +CONFIG_FAIR_GROUP_SCHED=y +CONFIG_CFS_BANDWIDTH=y +# CONFIG_RT_GROUP_SCHED is not set +CONFIG_CGROUP_PIDS=y +# CONFIG_CGROUP_RDMA is not set +CONFIG_CGROUP_FREEZER=y +# CONFIG_CGROUP_HUGETLB is not set +CONFIG_CPUSETS=y +CONFIG_PROC_PID_CPUSET=y +CONFIG_CGROUP_DEVICE=y +CONFIG_CGROUP_CPUACCT=y +CONFIG_CGROUP_PERF=y +CONFIG_CGROUP_BPF=y +# CONFIG_CGROUP_DEBUG is not set +CONFIG_SOCK_CGROUP_DATA=y +CONFIG_NAMESPACES=y +CONFIG_UTS_NS=y +CONFIG_TIME_NS=y +CONFIG_IPC_NS=y +CONFIG_USER_NS=y +CONFIG_PID_NS=y +CONFIG_NET_NS=y +CONFIG_CHECKPOINT_RESTORE=y +CONFIG_SCHED_AUTOGROUP=y +# CONFIG_SYSFS_DEPRECATED is not set +CONFIG_RELAY=y +CONFIG_BLK_DEV_INITRD=y +CONFIG_INITRAMFS_SOURCE="" +CONFIG_RD_GZIP=y +CONFIG_RD_BZIP2=y +CONFIG_RD_LZMA=y +CONFIG_RD_XZ=y +CONFIG_RD_LZO=y +CONFIG_RD_LZ4=y +CONFIG_RD_ZSTD=y +# CONFIG_BOOT_CONFIG is not set +CONFIG_CC_OPTIMIZE_FOR_PERFORMANCE=y +# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set +CONFIG_LD_ORPHAN_WARN=y +CONFIG_SYSCTL=y +CONFIG_HAVE_UID16=y +CONFIG_SYSCTL_EXCEPTION_TRACE=y +CONFIG_BPF=y +CONFIG_EXPERT=y +CONFIG_UID16=y +CONFIG_MULTIUSER=y +CONFIG_SGETMASK_SYSCALL=y +CONFIG_SYSFS_SYSCALL=y +CONFIG_FHANDLE=y +CONFIG_POSIX_TIMERS=y +CONFIG_PRINTK=y +CONFIG_PRINTK_NMI=y +CONFIG_BUG=y +CONFIG_ELF_CORE=y +CONFIG_BASE_FULL=y +CONFIG_FUTEX=y +CONFIG_FUTEX_PI=y +CONFIG_HAVE_FUTEX_CMPXCHG=y +CONFIG_EPOLL=y +CONFIG_SIGNALFD=y +CONFIG_TIMERFD=y +CONFIG_EVENTFD=y +CONFIG_SHMEM=y +CONFIG_AIO=y +CONFIG_IO_URING=y +CONFIG_ADVISE_SYSCALLS=y +CONFIG_MEMBARRIER=y +CONFIG_KALLSYMS=y +CONFIG_KALLSYMS_ALL=y +CONFIG_KALLSYMS_BASE_RELATIVE=y +# CONFIG_BPF_LSM is not set +CONFIG_BPF_SYSCALL=y +CONFIG_ARCH_WANT_DEFAULT_BPF_JIT=y +# CONFIG_BPF_JIT_ALWAYS_ON is not set +CONFIG_BPF_JIT_DEFAULT_ON=y +# CONFIG_BPF_PRELOAD is not set +CONFIG_USERFAULTFD=y +CONFIG_ARCH_HAS_MEMBARRIER_SYNC_CORE=y +CONFIG_RSEQ=y +# CONFIG_DEBUG_RSEQ is not set +# CONFIG_EMBEDDED is not set +CONFIG_HAVE_PERF_EVENTS=y +# CONFIG_PC104 is not set + +# +# Kernel Performance Events And Counters +# +CONFIG_PERF_EVENTS=y +# CONFIG_DEBUG_PERF_USE_VMALLOC is not set +# end of Kernel Performance Events And Counters + +CONFIG_VM_EVENT_COUNTERS=y +CONFIG_SLUB_DEBUG=y +# CONFIG_SLUB_MEMCG_SYSFS_ON is not set +# CONFIG_COMPAT_BRK is not set +# CONFIG_SLAB is not set +CONFIG_SLUB=y +# CONFIG_SLOB is not set +CONFIG_SLAB_MERGE_DEFAULT=y +# CONFIG_SLAB_FREELIST_RANDOM is not set +# CONFIG_SLAB_FREELIST_HARDENED is not set +CONFIG_SHUFFLE_PAGE_ALLOCATOR=y +CONFIG_SLUB_CPU_PARTIAL=y +CONFIG_SYSTEM_DATA_VERIFICATION=y +CONFIG_PROFILING=y +CONFIG_TRACEPOINTS=y +# end of General setup + +CONFIG_ARM64=y +CONFIG_64BIT=y +CONFIG_MMU=y +CONFIG_ARM64_PAGE_SHIFT=12 +CONFIG_ARM64_CONT_PTE_SHIFT=4 +CONFIG_ARM64_CONT_PMD_SHIFT=4 +CONFIG_ARCH_MMAP_RND_BITS_MIN=18 +CONFIG_ARCH_MMAP_RND_BITS_MAX=24 +CONFIG_ARCH_MMAP_RND_COMPAT_BITS_MIN=11 +CONFIG_ARCH_MMAP_RND_COMPAT_BITS_MAX=16 +CONFIG_STACKTRACE_SUPPORT=y +CONFIG_ILLEGAL_POINTER_VALUE=0xdead000000000000 +CONFIG_LOCKDEP_SUPPORT=y +CONFIG_TRACE_IRQFLAGS_SUPPORT=y +CONFIG_GENERIC_BUG=y +CONFIG_GENERIC_BUG_RELATIVE_POINTERS=y +CONFIG_GENERIC_HWEIGHT=y +CONFIG_GENERIC_CSUM=y +CONFIG_GENERIC_CALIBRATE_DELAY=y +CONFIG_ZONE_DMA=y +CONFIG_ZONE_DMA32=y +CONFIG_ARCH_ENABLE_MEMORY_HOTPLUG=y +CONFIG_ARCH_ENABLE_MEMORY_HOTREMOVE=y +CONFIG_SMP=y +CONFIG_KERNEL_MODE_NEON=y +CONFIG_FIX_EARLYCON_MEM=y +CONFIG_PGTABLE_LEVELS=3 +CONFIG_ARCH_SUPPORTS_UPROBES=y +CONFIG_ARCH_PROC_KCORE_TEXT=y + +# +# Platform selection +# +# CONFIG_ARCH_ACTIONS is not set +# CONFIG_ARCH_AGILEX is not set +# CONFIG_ARCH_SUNXI is not set +# CONFIG_ARCH_ALPINE is not set +# CONFIG_ARCH_BCM2835 is not set +# CONFIG_ARCH_BCM4908 is not set +# CONFIG_ARCH_BCM_IPROC is not set +# CONFIG_ARCH_BERLIN is not set +# CONFIG_ARCH_BITMAIN is not set +# CONFIG_ARCH_BRCMSTB is not set +# CONFIG_ARCH_EXYNOS is not set +# CONFIG_ARCH_SPARX5 is not set +# CONFIG_ARCH_K3 is not set +# CONFIG_ARCH_LAYERSCAPE is not set +# CONFIG_ARCH_LG1K is not set +# CONFIG_ARCH_HISI is not set +# CONFIG_ARCH_KEEMBAY is not set +# CONFIG_ARCH_MEDIATEK is not set +# CONFIG_ARCH_MESON is not set +# CONFIG_ARCH_MVEBU is not set +CONFIG_ARCH_MXC=y +# CONFIG_ARCH_QCOM is not set +# CONFIG_ARCH_REALTEK is not set +# CONFIG_ARCH_RENESAS is not set +# CONFIG_ARCH_ROCKCHIP is not set +# CONFIG_ARCH_S32 is not set +# CONFIG_ARCH_SEATTLE is not set +# CONFIG_ARCH_STRATIX10 is not set +# CONFIG_ARCH_SYNQUACER is not set +# CONFIG_ARCH_TEGRA is not set +# CONFIG_ARCH_SPRD is not set +# CONFIG_ARCH_THUNDER is not set +# CONFIG_ARCH_THUNDER2 is not set +# CONFIG_ARCH_UNIPHIER is not set +# CONFIG_ARCH_VEXPRESS is not set +# CONFIG_ARCH_VISCONTI is not set +# CONFIG_ARCH_XGENE is not set +# CONFIG_ARCH_ZX is not set +# CONFIG_ARCH_ZYNQMP is not set +# end of Platform selection + +# +# Kernel Features +# + +# +# ARM errata workarounds via the alternatives framework +# +CONFIG_ARM64_WORKAROUND_CLEAN_CACHE=y +CONFIG_ARM64_ERRATUM_826319=y +CONFIG_ARM64_ERRATUM_827319=y +CONFIG_ARM64_ERRATUM_824069=y +CONFIG_ARM64_ERRATUM_819472=y +CONFIG_ARM64_ERRATUM_832075=y +CONFIG_ARM64_ERRATUM_834220=y +CONFIG_ARM64_ERRATUM_845719=y +CONFIG_ARM64_ERRATUM_843419=y +CONFIG_ARM64_ERRATUM_1024718=y +CONFIG_ARM64_ERRATUM_1418040=y +CONFIG_ARM64_WORKAROUND_SPECULATIVE_AT=y +CONFIG_ARM64_ERRATUM_1165522=y +CONFIG_ARM64_ERRATUM_1319367=y +CONFIG_ARM64_ERRATUM_1530923=y +CONFIG_ARM64_WORKAROUND_REPEAT_TLBI=y +CONFIG_ARM64_ERRATUM_1286807=y +CONFIG_ARM64_ERRATUM_1463225=y +CONFIG_ARM64_ERRATUM_1542419=y +CONFIG_ARM64_ERRATUM_1508412=y +CONFIG_CAVIUM_ERRATUM_22375=y +CONFIG_CAVIUM_ERRATUM_23144=y +CONFIG_CAVIUM_ERRATUM_23154=y +CONFIG_CAVIUM_ERRATUM_27456=y +CONFIG_CAVIUM_ERRATUM_30115=y +CONFIG_CAVIUM_TX2_ERRATUM_219=y +CONFIG_FUJITSU_ERRATUM_010001=y +CONFIG_HISILICON_ERRATUM_161600802=y +CONFIG_QCOM_FALKOR_ERRATUM_1003=y +CONFIG_QCOM_FALKOR_ERRATUM_1009=y +CONFIG_QCOM_QDF2400_ERRATUM_0065=y +CONFIG_QCOM_FALKOR_ERRATUM_E1041=y +CONFIG_SOCIONEXT_SYNQUACER_PREITS=y +# end of ARM errata workarounds via the alternatives framework + +CONFIG_ARM64_4K_PAGES=y +# CONFIG_ARM64_16K_PAGES is not set +# CONFIG_ARM64_64K_PAGES is not set +CONFIG_ARM64_VA_BITS_39=y +# CONFIG_ARM64_VA_BITS_48 is not set +CONFIG_ARM64_VA_BITS=39 +CONFIG_ARM64_PA_BITS_48=y +CONFIG_ARM64_PA_BITS=48 +# CONFIG_CPU_BIG_ENDIAN is not set +CONFIG_CPU_LITTLE_ENDIAN=y +CONFIG_SCHED_MC=y +CONFIG_SCHED_SMT=y +CONFIG_NR_CPUS=512 +CONFIG_HOTPLUG_CPU=y +CONFIG_NUMA=y +CONFIG_NODES_SHIFT=6 +CONFIG_USE_PERCPU_NUMA_NODE_ID=y +CONFIG_HAVE_SETUP_PER_CPU_AREA=y +CONFIG_NEED_PER_CPU_EMBED_FIRST_CHUNK=y +CONFIG_HOLES_IN_ZONE=y +# CONFIG_HZ_100 is not set +CONFIG_HZ_250=y +# CONFIG_HZ_300 is not set +# CONFIG_HZ_1000 is not set +CONFIG_HZ=250 +CONFIG_SCHED_HRTICK=y +CONFIG_ARCH_SPARSEMEM_ENABLE=y +CONFIG_ARCH_SPARSEMEM_DEFAULT=y +CONFIG_ARCH_SELECT_MEMORY_MODEL=y +CONFIG_HW_PERF_EVENTS=y +CONFIG_SYS_SUPPORTS_HUGETLBFS=y +CONFIG_ARCH_WANT_HUGE_PMD_SHARE=y +CONFIG_ARCH_HAS_CACHE_LINE_SIZE=y +CONFIG_ARCH_ENABLE_SPLIT_PMD_PTLOCK=y +CONFIG_PARAVIRT=y +# CONFIG_PARAVIRT_TIME_ACCOUNTING is not set +CONFIG_KEXEC=y +CONFIG_KEXEC_FILE=y +# CONFIG_KEXEC_SIG is not set +CONFIG_CRASH_DUMP=y +CONFIG_XEN_DOM0=y +CONFIG_XEN=y +CONFIG_FORCE_MAX_ZONEORDER=11 +CONFIG_UNMAP_KERNEL_AT_EL0=y +CONFIG_RODATA_FULL_DEFAULT_ENABLED=y +# CONFIG_ARM64_SW_TTBR0_PAN is not set +CONFIG_ARM64_TAGGED_ADDR_ABI=y +CONFIG_COMPAT=y +CONFIG_KUSER_HELPERS=y +CONFIG_ARMV8_DEPRECATED=y +CONFIG_SWP_EMULATION=y +CONFIG_CP15_BARRIER_EMULATION=y +CONFIG_SETEND_EMULATION=y + +# +# ARMv8.1 architectural features +# +CONFIG_ARM64_HW_AFDBM=y +CONFIG_ARM64_PAN=y +CONFIG_AS_HAS_LDAPR=y +CONFIG_ARM64_LSE_ATOMICS=y +CONFIG_ARM64_USE_LSE_ATOMICS=y +CONFIG_ARM64_VHE=y +# end of ARMv8.1 architectural features + +# +# ARMv8.2 architectural features +# +# CONFIG_ARM64_PMEM is not set +CONFIG_ARM64_RAS_EXTN=y +CONFIG_ARM64_CNP=y +# end of ARMv8.2 architectural features + +# +# ARMv8.3 architectural features +# +CONFIG_ARM64_PTR_AUTH=y +CONFIG_CC_HAS_BRANCH_PROT_PAC_RET=y +CONFIG_CC_HAS_SIGN_RETURN_ADDRESS=y +CONFIG_AS_HAS_PAC=y +CONFIG_AS_HAS_CFI_NEGATE_RA_STATE=y +# end of ARMv8.3 architectural features + +# +# ARMv8.4 architectural features +# +CONFIG_ARM64_AMU_EXTN=y +CONFIG_AS_HAS_ARMV8_4=y +CONFIG_ARM64_TLB_RANGE=y +# end of ARMv8.4 architectural features + +# +# ARMv8.5 architectural features +# +CONFIG_AS_HAS_ARMV8_5=y +CONFIG_ARM64_BTI=y +CONFIG_ARM64_BTI_KERNEL=y +CONFIG_CC_HAS_BRANCH_PROT_PAC_RET_BTI=y +CONFIG_ARM64_E0PD=y +CONFIG_ARCH_RANDOM=y +CONFIG_ARM64_AS_HAS_MTE=y +CONFIG_ARM64_MTE=y +# end of ARMv8.5 architectural features + +CONFIG_ARM64_SVE=y +CONFIG_ARM64_MODULE_PLTS=y +# CONFIG_ARM64_PSEUDO_NMI is not set +CONFIG_RELOCATABLE=y +CONFIG_RANDOMIZE_BASE=y +CONFIG_RANDOMIZE_MODULE_REGION_FULL=y +CONFIG_CC_HAVE_STACKPROTECTOR_SYSREG=y +CONFIG_STACKPROTECTOR_PER_TASK=y +# end of Kernel Features + +# +# Boot options +# +CONFIG_CMDLINE="" +CONFIG_EFI_STUB=y +CONFIG_EFI=y +CONFIG_DMI=y +# end of Boot options + +CONFIG_SYSVIPC_COMPAT=y +CONFIG_ARCH_ENABLE_HUGEPAGE_MIGRATION=y +CONFIG_ARCH_ENABLE_THP_MIGRATION=y + +# +# Power management options +# +CONFIG_SUSPEND=y +CONFIG_SUSPEND_FREEZER=y +# CONFIG_SUSPEND_SKIP_SYNC is not set +CONFIG_HIBERNATE_CALLBACKS=y +CONFIG_HIBERNATION=y +CONFIG_HIBERNATION_SNAPSHOT_DEV=y +CONFIG_PM_STD_PARTITION="" +CONFIG_PM_SLEEP=y +CONFIG_PM_SLEEP_SMP=y +# CONFIG_PM_AUTOSLEEP is not set +CONFIG_PM_WAKELOCKS=y +CONFIG_PM_WAKELOCKS_LIMIT=100 +CONFIG_PM_WAKELOCKS_GC=y +CONFIG_PM=y +CONFIG_PM_DEBUG=y +CONFIG_PM_ADVANCED_DEBUG=y +# CONFIG_PM_TEST_SUSPEND is not set +CONFIG_PM_SLEEP_DEBUG=y +# CONFIG_DPM_WATCHDOG is not set +CONFIG_PM_CLK=y +CONFIG_PM_GENERIC_DOMAINS=y +# CONFIG_WQ_POWER_EFFICIENT_DEFAULT is not set +CONFIG_PM_GENERIC_DOMAINS_SLEEP=y +CONFIG_PM_GENERIC_DOMAINS_OF=y +CONFIG_CPU_PM=y +# CONFIG_ENERGY_MODEL is not set +CONFIG_ARCH_HIBERNATION_POSSIBLE=y +CONFIG_ARCH_HIBERNATION_HEADER=y +CONFIG_ARCH_SUSPEND_POSSIBLE=y +# end of Power management options + +# +# CPU Power Management +# + +# +# CPU Idle +# +CONFIG_CPU_IDLE=y +CONFIG_CPU_IDLE_MULTIPLE_DRIVERS=y +CONFIG_CPU_IDLE_GOV_LADDER=y +CONFIG_CPU_IDLE_GOV_MENU=y +# CONFIG_CPU_IDLE_GOV_TEO is not set +CONFIG_DT_IDLE_STATES=y + +# +# ARM CPU Idle Drivers +# +CONFIG_ARM_CPUIDLE=y +CONFIG_ARM_PSCI_CPUIDLE=y +CONFIG_ARM_PSCI_CPUIDLE_DOMAIN=y +# end of ARM CPU Idle Drivers +# end of CPU Idle + +# +# CPU Frequency scaling +# +CONFIG_CPU_FREQ=y +CONFIG_CPU_FREQ_GOV_ATTR_SET=y +CONFIG_CPU_FREQ_GOV_COMMON=y +CONFIG_CPU_FREQ_STAT=y +# CONFIG_CPU_FREQ_DEFAULT_GOV_PERFORMANCE is not set +# CONFIG_CPU_FREQ_DEFAULT_GOV_POWERSAVE is not set +# CONFIG_CPU_FREQ_DEFAULT_GOV_USERSPACE is not set +CONFIG_CPU_FREQ_DEFAULT_GOV_ONDEMAND=y +# CONFIG_CPU_FREQ_DEFAULT_GOV_CONSERVATIVE is not set +# CONFIG_CPU_FREQ_DEFAULT_GOV_SCHEDUTIL is not set +CONFIG_CPU_FREQ_GOV_PERFORMANCE=y +CONFIG_CPU_FREQ_GOV_POWERSAVE=y +CONFIG_CPU_FREQ_GOV_USERSPACE=y +CONFIG_CPU_FREQ_GOV_ONDEMAND=y +CONFIG_CPU_FREQ_GOV_CONSERVATIVE=y +CONFIG_CPU_FREQ_GOV_SCHEDUTIL=y + +# +# CPU frequency scaling drivers +# +CONFIG_CPUFREQ_DT=y +CONFIG_CPUFREQ_DT_PLATDEV=y +# CONFIG_ARM_IMX6Q_CPUFREQ is not set +CONFIG_ARM_IMX_CPUFREQ_DT=y +# end of CPU Frequency scaling +# end of CPU Power Management + +# +# Firmware Drivers +# +# CONFIG_ARM_SCMI_PROTOCOL is not set +# CONFIG_ARM_SCPI_PROTOCOL is not set +# CONFIG_ARM_SDE_INTERFACE is not set +CONFIG_FIRMWARE_MEMMAP=y +CONFIG_DMIID=y +CONFIG_DMI_SYSFS=y +# CONFIG_FW_CFG_SYSFS is not set +# CONFIG_GOOGLE_FIRMWARE is not set + +# +# EFI (Extensible Firmware Interface) Support +# +CONFIG_EFI_ESRT=y +CONFIG_EFI_VARS_PSTORE=y +# CONFIG_EFI_VARS_PSTORE_DEFAULT_DISABLE is not set +CONFIG_EFI_PARAMS_FROM_FDT=y +CONFIG_EFI_RUNTIME_WRAPPERS=y +CONFIG_EFI_GENERIC_STUB=y +CONFIG_EFI_ARMSTUB_DTB_LOADER=y +CONFIG_EFI_GENERIC_STUB_INITRD_CMDLINE_LOADER=y +CONFIG_EFI_BOOTLOADER_CONTROL=y +# CONFIG_EFI_CAPSULE_LOADER is not set +# CONFIG_EFI_TEST is not set +# CONFIG_RESET_ATTACK_MITIGATION is not set +# CONFIG_EFI_DISABLE_PCI_DMA is not set +# end of EFI (Extensible Firmware Interface) Support + +CONFIG_EFI_EARLYCON=y +# CONFIG_IMX_DSP is not set +# CONFIG_IMX_SCU is not set +CONFIG_ARM_PSCI_FW=y +# CONFIG_ARM_PSCI_CHECKER is not set +CONFIG_HAVE_ARM_SMCCC=y +CONFIG_HAVE_ARM_SMCCC_DISCOVERY=y +CONFIG_ARM_SMCCC_SOC_ID=y + +# +# Tegra firmware driver +# +# end of Tegra firmware driver +# end of Firmware Drivers + +CONFIG_ARCH_SUPPORTS_ACPI=y +# CONFIG_ACPI is not set +CONFIG_IRQ_BYPASS_MANAGER=y +CONFIG_VIRTUALIZATION=y +CONFIG_KVM=y +CONFIG_HAVE_KVM_IRQCHIP=y +CONFIG_HAVE_KVM_IRQFD=y +CONFIG_HAVE_KVM_IRQ_ROUTING=y +CONFIG_HAVE_KVM_EVENTFD=y +CONFIG_KVM_MMIO=y +CONFIG_HAVE_KVM_MSI=y +CONFIG_HAVE_KVM_CPU_RELAX_INTERCEPT=y +CONFIG_KVM_VFIO=y +CONFIG_HAVE_KVM_ARCH_TLB_FLUSH_ALL=y +CONFIG_KVM_GENERIC_DIRTYLOG_READ_PROTECT=y +CONFIG_HAVE_KVM_IRQ_BYPASS=y +CONFIG_HAVE_KVM_VCPU_RUN_PID_CHANGE=y +CONFIG_ARM64_CRYPTO=y +CONFIG_CRYPTO_SHA256_ARM64=y +CONFIG_CRYPTO_SHA512_ARM64=y +CONFIG_CRYPTO_SHA1_ARM64_CE=y +CONFIG_CRYPTO_SHA2_ARM64_CE=y +CONFIG_CRYPTO_SHA512_ARM64_CE=y +CONFIG_CRYPTO_SHA3_ARM64=y +# CONFIG_CRYPTO_SM3_ARM64_CE is not set +# CONFIG_CRYPTO_SM4_ARM64_CE is not set +# CONFIG_CRYPTO_GHASH_ARM64_CE is not set +# CONFIG_CRYPTO_CRCT10DIF_ARM64_CE is not set +CONFIG_CRYPTO_AES_ARM64=y +CONFIG_CRYPTO_AES_ARM64_CE=y +CONFIG_CRYPTO_AES_ARM64_CE_CCM=y +CONFIG_CRYPTO_AES_ARM64_CE_BLK=y +CONFIG_CRYPTO_AES_ARM64_NEON_BLK=y +CONFIG_CRYPTO_CHACHA20_NEON=y +CONFIG_CRYPTO_POLY1305_NEON=y +# CONFIG_CRYPTO_NHPOLY1305_NEON is not set +# CONFIG_CRYPTO_AES_ARM64_BS is not set + +# +# General architecture-dependent options +# +CONFIG_CRASH_CORE=y +CONFIG_KEXEC_CORE=y +CONFIG_KPROBES=y +CONFIG_JUMP_LABEL=y +# CONFIG_STATIC_KEYS_SELFTEST is not set +CONFIG_UPROBES=y +CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS=y +CONFIG_KRETPROBES=y +CONFIG_HAVE_KPROBES=y +CONFIG_HAVE_KRETPROBES=y +CONFIG_HAVE_FUNCTION_ERROR_INJECTION=y +CONFIG_HAVE_NMI=y +CONFIG_HAVE_ARCH_TRACEHOOK=y +CONFIG_HAVE_DMA_CONTIGUOUS=y +CONFIG_GENERIC_SMP_IDLE_THREAD=y +CONFIG_GENERIC_IDLE_POLL_SETUP=y +CONFIG_ARCH_HAS_FORTIFY_SOURCE=y +CONFIG_ARCH_HAS_KEEPINITRD=y +CONFIG_ARCH_HAS_SET_MEMORY=y +CONFIG_ARCH_HAS_SET_DIRECT_MAP=y +CONFIG_HAVE_ARCH_THREAD_STRUCT_WHITELIST=y +CONFIG_HAVE_ASM_MODVERSIONS=y +CONFIG_HAVE_REGS_AND_STACK_ACCESS_API=y +CONFIG_HAVE_RSEQ=y +CONFIG_HAVE_FUNCTION_ARG_ACCESS_API=y +CONFIG_HAVE_HW_BREAKPOINT=y +CONFIG_HAVE_PERF_REGS=y +CONFIG_HAVE_PERF_USER_STACK_DUMP=y +CONFIG_HAVE_ARCH_JUMP_LABEL=y +CONFIG_HAVE_ARCH_JUMP_LABEL_RELATIVE=y +CONFIG_MMU_GATHER_TABLE_FREE=y +CONFIG_MMU_GATHER_RCU_TABLE_FREE=y +CONFIG_ARCH_HAVE_NMI_SAFE_CMPXCHG=y +CONFIG_HAVE_ALIGNED_STRUCT_PAGE=y +CONFIG_HAVE_CMPXCHG_LOCAL=y +CONFIG_HAVE_CMPXCHG_DOUBLE=y +CONFIG_ARCH_WANT_COMPAT_IPC_PARSE_VERSION=y +CONFIG_HAVE_ARCH_SECCOMP=y +CONFIG_HAVE_ARCH_SECCOMP_FILTER=y +CONFIG_SECCOMP=y +CONFIG_SECCOMP_FILTER=y +# CONFIG_SECCOMP_CACHE_DEBUG is not set +CONFIG_HAVE_ARCH_STACKLEAK=y +CONFIG_HAVE_STACKPROTECTOR=y +CONFIG_STACKPROTECTOR=y +CONFIG_STACKPROTECTOR_STRONG=y +CONFIG_HAVE_CONTEXT_TRACKING=y +CONFIG_HAVE_VIRT_CPU_ACCOUNTING_GEN=y +CONFIG_HAVE_IRQ_TIME_ACCOUNTING=y +CONFIG_HAVE_MOVE_PUD=y +CONFIG_HAVE_MOVE_PMD=y +CONFIG_HAVE_ARCH_TRANSPARENT_HUGEPAGE=y +CONFIG_HAVE_ARCH_HUGE_VMAP=y +CONFIG_HAVE_MOD_ARCH_SPECIFIC=y +CONFIG_MODULES_USE_ELF_RELA=y +CONFIG_ARCH_HAS_ELF_RANDOMIZE=y +CONFIG_HAVE_ARCH_MMAP_RND_BITS=y +CONFIG_ARCH_MMAP_RND_BITS=18 +CONFIG_HAVE_ARCH_MMAP_RND_COMPAT_BITS=y +CONFIG_ARCH_MMAP_RND_COMPAT_BITS=11 +CONFIG_ARCH_WANT_DEFAULT_TOPDOWN_MMAP_LAYOUT=y +CONFIG_CLONE_BACKWARDS=y +CONFIG_OLD_SIGSUSPEND3=y +CONFIG_COMPAT_OLD_SIGACTION=y +CONFIG_COMPAT_32BIT_TIME=y +CONFIG_HAVE_ARCH_VMAP_STACK=y +CONFIG_VMAP_STACK=y +CONFIG_ARCH_HAS_STRICT_KERNEL_RWX=y +CONFIG_STRICT_KERNEL_RWX=y +CONFIG_ARCH_HAS_STRICT_MODULE_RWX=y +CONFIG_STRICT_MODULE_RWX=y +CONFIG_HAVE_ARCH_COMPILER_H=y +CONFIG_HAVE_ARCH_PREL32_RELOCATIONS=y +CONFIG_ARCH_USE_MEMREMAP_PROT=y +# CONFIG_LOCK_EVENT_COUNTS is not set +CONFIG_ARCH_HAS_RELR=y +CONFIG_ARCH_WANT_LD_ORPHAN_WARN=y +CONFIG_HAVE_ARCH_PFN_VALID=y +CONFIG_ARCH_SUPPORTS_DEBUG_PAGEALLOC=y + +# +# GCOV-based kernel profiling +# +# CONFIG_GCOV_KERNEL is not set +CONFIG_ARCH_HAS_GCOV_PROFILE_ALL=y +# end of GCOV-based kernel profiling + +CONFIG_HAVE_GCC_PLUGINS=y +# end of General architecture-dependent options + +CONFIG_RT_MUTEXES=y +CONFIG_BASE_SMALL=0 +CONFIG_MODULE_SIG_FORMAT=y +CONFIG_MODULES=y +CONFIG_MODULE_FORCE_LOAD=y +CONFIG_MODULE_UNLOAD=y +CONFIG_MODULE_FORCE_UNLOAD=y +CONFIG_MODVERSIONS=y +CONFIG_ASM_MODVERSIONS=y +# CONFIG_MODULE_SRCVERSION_ALL is not set +CONFIG_MODULE_SIG=y +# CONFIG_MODULE_SIG_FORCE is not set +# CONFIG_MODULE_SIG_ALL is not set +# CONFIG_MODULE_SIG_SHA1 is not set +# CONFIG_MODULE_SIG_SHA224 is not set +CONFIG_MODULE_SIG_SHA256=y +# CONFIG_MODULE_SIG_SHA384 is not set +# CONFIG_MODULE_SIG_SHA512 is not set +CONFIG_MODULE_SIG_HASH="sha256" +# CONFIG_MODULE_COMPRESS is not set +# CONFIG_MODULE_ALLOW_MISSING_NAMESPACE_IMPORTS is not set +# CONFIG_UNUSED_SYMBOLS is not set +# CONFIG_TRIM_UNUSED_KSYMS is not set +CONFIG_MODULES_TREE_LOOKUP=y +CONFIG_BLOCK=y +CONFIG_BLK_SCSI_REQUEST=y +CONFIG_BLK_CGROUP_RWSTAT=y +CONFIG_BLK_DEV_BSG=y +CONFIG_BLK_DEV_BSGLIB=y +CONFIG_BLK_DEV_INTEGRITY=y +CONFIG_BLK_DEV_INTEGRITY_T10=y +# CONFIG_BLK_DEV_ZONED is not set +CONFIG_BLK_DEV_THROTTLING=y +# CONFIG_BLK_DEV_THROTTLING_LOW is not set +# CONFIG_BLK_CMDLINE_PARSER is not set +CONFIG_BLK_WBT=y +# CONFIG_BLK_CGROUP_IOLATENCY is not set +# CONFIG_BLK_CGROUP_IOCOST is not set +CONFIG_BLK_WBT_MQ=y +CONFIG_BLK_DEBUG_FS=y +CONFIG_BLK_SED_OPAL=y +# CONFIG_BLK_INLINE_ENCRYPTION is not set + +# +# Partition Types +# +CONFIG_PARTITION_ADVANCED=y +# CONFIG_ACORN_PARTITION is not set +# CONFIG_AIX_PARTITION is not set +# CONFIG_OSF_PARTITION is not set +CONFIG_AMIGA_PARTITION=y +CONFIG_ATARI_PARTITION=y +CONFIG_MAC_PARTITION=y +CONFIG_MSDOS_PARTITION=y +CONFIG_BSD_DISKLABEL=y +CONFIG_MINIX_SUBPARTITION=y +CONFIG_SOLARIS_X86_PARTITION=y +CONFIG_UNIXWARE_DISKLABEL=y +# CONFIG_LDM_PARTITION is not set +# CONFIG_SGI_PARTITION is not set +# CONFIG_ULTRIX_PARTITION is not set +# CONFIG_SUN_PARTITION is not set +# CONFIG_KARMA_PARTITION is not set +CONFIG_EFI_PARTITION=y +# CONFIG_SYSV68_PARTITION is not set +# CONFIG_CMDLINE_PARTITION is not set +# end of Partition Types + +CONFIG_BLOCK_COMPAT=y +CONFIG_BLK_MQ_PCI=y +CONFIG_BLK_MQ_VIRTIO=y +CONFIG_BLK_PM=y + +# +# IO Schedulers +# +CONFIG_MQ_IOSCHED_DEADLINE=y +CONFIG_MQ_IOSCHED_KYBER=y +CONFIG_IOSCHED_BFQ=y +CONFIG_BFQ_GROUP_IOSCHED=y +# CONFIG_BFQ_CGROUP_DEBUG is not set +# end of IO Schedulers + +CONFIG_PREEMPT_NOTIFIERS=y +CONFIG_PADATA=y +CONFIG_ASN1=y +CONFIG_UNINLINE_SPIN_UNLOCK=y +CONFIG_ARCH_SUPPORTS_ATOMIC_RMW=y +CONFIG_MUTEX_SPIN_ON_OWNER=y +CONFIG_RWSEM_SPIN_ON_OWNER=y +CONFIG_LOCK_SPIN_ON_OWNER=y +CONFIG_ARCH_USE_QUEUED_SPINLOCKS=y +CONFIG_QUEUED_SPINLOCKS=y +CONFIG_ARCH_USE_QUEUED_RWLOCKS=y +CONFIG_QUEUED_RWLOCKS=y +CONFIG_ARCH_HAS_NON_OVERLAPPING_ADDRESS_SPACE=y +CONFIG_ARCH_HAS_SYSCALL_WRAPPER=y +CONFIG_FREEZER=y + +# +# Executable file formats +# +CONFIG_BINFMT_ELF=y +CONFIG_COMPAT_BINFMT_ELF=y +CONFIG_ARCH_BINFMT_ELF_STATE=y +CONFIG_ARCH_HAVE_ELF_PROT=y +CONFIG_ARCH_USE_GNU_PROPERTY=y +CONFIG_ELFCORE=y +CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS=y +CONFIG_BINFMT_SCRIPT=y +CONFIG_BINFMT_MISC=y +CONFIG_COREDUMP=y +# end of Executable file formats + +# +# Memory Management options +# +CONFIG_SELECT_MEMORY_MODEL=y +CONFIG_SPARSEMEM_MANUAL=y +CONFIG_SPARSEMEM=y +CONFIG_NEED_MULTIPLE_NODES=y +CONFIG_SPARSEMEM_EXTREME=y +CONFIG_SPARSEMEM_VMEMMAP_ENABLE=y +CONFIG_SPARSEMEM_VMEMMAP=y +CONFIG_HAVE_FAST_GUP=y +CONFIG_ARCH_KEEP_MEMBLOCK=y +CONFIG_MEMORY_ISOLATION=y +# CONFIG_MEMORY_HOTPLUG is not set +CONFIG_SPLIT_PTLOCK_CPUS=4 +CONFIG_MEMORY_BALLOON=y +CONFIG_BALLOON_COMPACTION=y +CONFIG_COMPACTION=y +CONFIG_PAGE_REPORTING=y +CONFIG_MIGRATION=y +CONFIG_CONTIG_ALLOC=y +CONFIG_PHYS_ADDR_T_64BIT=y +CONFIG_BOUNCE=y +CONFIG_MMU_NOTIFIER=y +CONFIG_KSM=y +CONFIG_DEFAULT_MMAP_MIN_ADDR=65536 +CONFIG_ARCH_SUPPORTS_MEMORY_FAILURE=y +CONFIG_MEMORY_FAILURE=y +# CONFIG_HWPOISON_INJECT is not set +CONFIG_TRANSPARENT_HUGEPAGE=y +CONFIG_TRANSPARENT_HUGEPAGE_ALWAYS=y +# CONFIG_TRANSPARENT_HUGEPAGE_MADVISE is not set +# CONFIG_CLEANCACHE is not set +CONFIG_FRONTSWAP=y +CONFIG_CMA=y +# CONFIG_CMA_DEBUG is not set +# CONFIG_CMA_DEBUGFS is not set +CONFIG_CMA_AREAS=7 +CONFIG_ZSWAP=y +# CONFIG_ZSWAP_COMPRESSOR_DEFAULT_DEFLATE is not set +CONFIG_ZSWAP_COMPRESSOR_DEFAULT_LZO=y +# CONFIG_ZSWAP_COMPRESSOR_DEFAULT_842 is not set +# CONFIG_ZSWAP_COMPRESSOR_DEFAULT_LZ4 is not set +# CONFIG_ZSWAP_COMPRESSOR_DEFAULT_LZ4HC is not set +# CONFIG_ZSWAP_COMPRESSOR_DEFAULT_ZSTD is not set +CONFIG_ZSWAP_COMPRESSOR_DEFAULT="lzo" +CONFIG_ZSWAP_ZPOOL_DEFAULT_ZBUD=y +# CONFIG_ZSWAP_ZPOOL_DEFAULT_Z3FOLD is not set +# CONFIG_ZSWAP_ZPOOL_DEFAULT_ZSMALLOC is not set +CONFIG_ZSWAP_ZPOOL_DEFAULT="zbud" +# CONFIG_ZSWAP_DEFAULT_ON is not set +CONFIG_ZPOOL=y +CONFIG_ZBUD=y +# CONFIG_Z3FOLD is not set +# CONFIG_ZSMALLOC is not set +CONFIG_GENERIC_EARLY_IOREMAP=y +# CONFIG_DEFERRED_STRUCT_PAGE_INIT is not set +# CONFIG_IDLE_PAGE_TRACKING is not set +CONFIG_ARCH_HAS_PTE_DEVMAP=y +CONFIG_FRAME_VECTOR=y +CONFIG_ARCH_USES_HIGH_VMA_FLAGS=y +# CONFIG_PERCPU_STATS is not set +# CONFIG_GUP_TEST is not set +# CONFIG_READ_ONLY_THP_FOR_FS is not set +CONFIG_ARCH_HAS_PTE_SPECIAL=y +# end of Memory Management options + +CONFIG_NET=y +CONFIG_NET_INGRESS=y +CONFIG_SKB_EXTENSIONS=y + +# +# Networking options +# +CONFIG_PACKET=y +CONFIG_PACKET_DIAG=y +CONFIG_UNIX=y +CONFIG_UNIX_SCM=y +CONFIG_UNIX_DIAG=y +# CONFIG_TLS is not set +CONFIG_XFRM=y +CONFIG_XFRM_ALGO=y +CONFIG_XFRM_USER=y +# CONFIG_XFRM_INTERFACE is not set +# CONFIG_XFRM_SUB_POLICY is not set +# CONFIG_XFRM_MIGRATE is not set +# CONFIG_XFRM_STATISTICS is not set +CONFIG_XFRM_AH=y +CONFIG_XFRM_ESP=y +CONFIG_XFRM_IPCOMP=y +CONFIG_NET_KEY=y +# CONFIG_NET_KEY_MIGRATE is not set +# CONFIG_XDP_SOCKETS is not set +CONFIG_INET=y +CONFIG_IP_MULTICAST=y +CONFIG_IP_ADVANCED_ROUTER=y +# CONFIG_IP_FIB_TRIE_STATS is not set +CONFIG_IP_MULTIPLE_TABLES=y +CONFIG_IP_ROUTE_MULTIPATH=y +CONFIG_IP_ROUTE_VERBOSE=y +# CONFIG_IP_PNP is not set +# CONFIG_NET_IPIP is not set +# CONFIG_NET_IPGRE_DEMUX is not set +CONFIG_NET_IP_TUNNEL=y +CONFIG_IP_MROUTE_COMMON=y +CONFIG_IP_MROUTE=y +CONFIG_IP_MROUTE_MULTIPLE_TABLES=y +CONFIG_IP_PIMSM_V1=y +CONFIG_IP_PIMSM_V2=y +CONFIG_SYN_COOKIES=y +# CONFIG_NET_IPVTI is not set +CONFIG_NET_UDP_TUNNEL=y +# CONFIG_NET_FOU is not set +# CONFIG_NET_FOU_IP_TUNNELS is not set +# CONFIG_INET_AH is not set +CONFIG_INET_ESP=y +# CONFIG_INET_ESP_OFFLOAD is not set +# CONFIG_INET_ESPINTCP is not set +# CONFIG_INET_IPCOMP is not set +CONFIG_INET_TUNNEL=y +# CONFIG_INET_DIAG is not set +# CONFIG_TCP_CONG_ADVANCED is not set +CONFIG_TCP_CONG_CUBIC=y +CONFIG_DEFAULT_TCP_CONG="cubic" +# CONFIG_TCP_MD5SIG is not set +CONFIG_IPV6=y +CONFIG_IPV6_ROUTER_PREF=y +CONFIG_IPV6_ROUTE_INFO=y +CONFIG_IPV6_OPTIMISTIC_DAD=y +CONFIG_INET6_AH=y +CONFIG_INET6_ESP=y +# CONFIG_INET6_ESP_OFFLOAD is not set +# CONFIG_INET6_ESPINTCP is not set +CONFIG_INET6_IPCOMP=y +# CONFIG_IPV6_MIP6 is not set +# CONFIG_IPV6_ILA is not set +CONFIG_INET6_XFRM_TUNNEL=y +CONFIG_INET6_TUNNEL=y +# CONFIG_IPV6_VTI is not set +CONFIG_IPV6_SIT=y +CONFIG_IPV6_SIT_6RD=y +CONFIG_IPV6_NDISC_NODETYPE=y +# CONFIG_IPV6_TUNNEL is not set +# CONFIG_IPV6_MULTIPLE_TABLES is not set +# CONFIG_IPV6_MROUTE is not set +# CONFIG_IPV6_SEG6_LWTUNNEL is not set +# CONFIG_IPV6_SEG6_HMAC is not set +# CONFIG_IPV6_RPL_LWTUNNEL is not set +# CONFIG_NETLABEL is not set +# CONFIG_MPTCP is not set +CONFIG_NETWORK_SECMARK=y +# CONFIG_NETWORK_PHY_TIMESTAMPING is not set +CONFIG_NETFILTER=y +CONFIG_NETFILTER_ADVANCED=y +CONFIG_BRIDGE_NETFILTER=y + +# +# Core Netfilter Configuration +# +CONFIG_NETFILTER_INGRESS=y +CONFIG_NETFILTER_NETLINK=y +CONFIG_NETFILTER_FAMILY_BRIDGE=y +CONFIG_NETFILTER_NETLINK_ACCT=y +CONFIG_NETFILTER_NETLINK_QUEUE=y +CONFIG_NETFILTER_NETLINK_LOG=y +# CONFIG_NETFILTER_NETLINK_OSF is not set +CONFIG_NF_CONNTRACK=y +# CONFIG_NF_LOG_NETDEV is not set +CONFIG_NETFILTER_CONNCOUNT=y +CONFIG_NF_CONNTRACK_MARK=y +CONFIG_NF_CONNTRACK_SECMARK=y +CONFIG_NF_CONNTRACK_ZONES=y +CONFIG_NF_CONNTRACK_PROCFS=y +CONFIG_NF_CONNTRACK_EVENTS=y +CONFIG_NF_CONNTRACK_TIMEOUT=y +CONFIG_NF_CONNTRACK_TIMESTAMP=y +CONFIG_NF_CONNTRACK_LABELS=y +CONFIG_NF_CT_PROTO_DCCP=y +CONFIG_NF_CT_PROTO_SCTP=y +CONFIG_NF_CT_PROTO_UDPLITE=y +# CONFIG_NF_CONNTRACK_AMANDA is not set +# CONFIG_NF_CONNTRACK_FTP is not set +# CONFIG_NF_CONNTRACK_H323 is not set +# CONFIG_NF_CONNTRACK_IRC is not set +# CONFIG_NF_CONNTRACK_NETBIOS_NS is not set +# CONFIG_NF_CONNTRACK_SNMP is not set +# CONFIG_NF_CONNTRACK_PPTP is not set +# CONFIG_NF_CONNTRACK_SANE is not set +# CONFIG_NF_CONNTRACK_SIP is not set +# CONFIG_NF_CONNTRACK_TFTP is not set +# CONFIG_NF_CT_NETLINK is not set +# CONFIG_NF_CT_NETLINK_TIMEOUT is not set +CONFIG_NF_NAT=y +CONFIG_NF_NAT_REDIRECT=y +CONFIG_NF_NAT_MASQUERADE=y +CONFIG_NF_TABLES=y +CONFIG_NF_TABLES_INET=y +CONFIG_NF_TABLES_NETDEV=y +# CONFIG_NFT_NUMGEN is not set +CONFIG_NFT_CT=y +CONFIG_NFT_COUNTER=y +CONFIG_NFT_CONNLIMIT=y +CONFIG_NFT_LOG=y +CONFIG_NFT_LIMIT=y +CONFIG_NFT_MASQ=y +CONFIG_NFT_REDIR=y +CONFIG_NFT_NAT=y +CONFIG_NFT_TUNNEL=y +# CONFIG_NFT_OBJREF is not set +CONFIG_NFT_QUEUE=y +CONFIG_NFT_QUOTA=y +CONFIG_NFT_REJECT=y +CONFIG_NFT_REJECT_INET=y +CONFIG_NFT_COMPAT=y +# CONFIG_NFT_HASH is not set +# CONFIG_NFT_XFRM is not set +CONFIG_NFT_SOCKET=y +# CONFIG_NFT_OSF is not set +CONFIG_NFT_TPROXY=y +# CONFIG_NFT_SYNPROXY is not set +CONFIG_NF_DUP_NETDEV=y +CONFIG_NFT_DUP_NETDEV=y +CONFIG_NFT_FWD_NETDEV=y +# CONFIG_NFT_REJECT_NETDEV is not set +# CONFIG_NF_FLOW_TABLE is not set +CONFIG_NETFILTER_XTABLES=y + +# +# Xtables combined modules +# +CONFIG_NETFILTER_XT_MARK=y +# CONFIG_NETFILTER_XT_CONNMARK is not set + +# +# Xtables targets +# +# CONFIG_NETFILTER_XT_TARGET_AUDIT is not set +CONFIG_NETFILTER_XT_TARGET_CHECKSUM=y +# CONFIG_NETFILTER_XT_TARGET_CLASSIFY is not set +# CONFIG_NETFILTER_XT_TARGET_CONNMARK is not set +# CONFIG_NETFILTER_XT_TARGET_CONNSECMARK is not set +# CONFIG_NETFILTER_XT_TARGET_DSCP is not set +# CONFIG_NETFILTER_XT_TARGET_HL is not set +# CONFIG_NETFILTER_XT_TARGET_HMARK is not set +# CONFIG_NETFILTER_XT_TARGET_IDLETIMER is not set +# CONFIG_NETFILTER_XT_TARGET_LED is not set +# CONFIG_NETFILTER_XT_TARGET_LOG is not set +# CONFIG_NETFILTER_XT_TARGET_MARK is not set +CONFIG_NETFILTER_XT_NAT=y +# CONFIG_NETFILTER_XT_TARGET_NETMAP is not set +# CONFIG_NETFILTER_XT_TARGET_NFLOG is not set +# CONFIG_NETFILTER_XT_TARGET_NFQUEUE is not set +# CONFIG_NETFILTER_XT_TARGET_RATEEST is not set +CONFIG_NETFILTER_XT_TARGET_REDIRECT=y +CONFIG_NETFILTER_XT_TARGET_MASQUERADE=y +# CONFIG_NETFILTER_XT_TARGET_TEE is not set +# CONFIG_NETFILTER_XT_TARGET_TPROXY is not set +# CONFIG_NETFILTER_XT_TARGET_SECMARK is not set +# CONFIG_NETFILTER_XT_TARGET_TCPMSS is not set +# CONFIG_NETFILTER_XT_TARGET_TCPOPTSTRIP is not set + +# +# Xtables matches +# +CONFIG_NETFILTER_XT_MATCH_ADDRTYPE=y +# CONFIG_NETFILTER_XT_MATCH_BPF is not set +# CONFIG_NETFILTER_XT_MATCH_CGROUP is not set +# CONFIG_NETFILTER_XT_MATCH_CLUSTER is not set +CONFIG_NETFILTER_XT_MATCH_COMMENT=y +# CONFIG_NETFILTER_XT_MATCH_CONNBYTES is not set +# CONFIG_NETFILTER_XT_MATCH_CONNLABEL is not set +# CONFIG_NETFILTER_XT_MATCH_CONNLIMIT is not set +# CONFIG_NETFILTER_XT_MATCH_CONNMARK is not set +CONFIG_NETFILTER_XT_MATCH_CONNTRACK=y +# CONFIG_NETFILTER_XT_MATCH_CPU is not set +# CONFIG_NETFILTER_XT_MATCH_DCCP is not set +# CONFIG_NETFILTER_XT_MATCH_DEVGROUP is not set +# CONFIG_NETFILTER_XT_MATCH_DSCP is not set +# CONFIG_NETFILTER_XT_MATCH_ECN is not set +# CONFIG_NETFILTER_XT_MATCH_ESP is not set +# CONFIG_NETFILTER_XT_MATCH_HASHLIMIT is not set +# CONFIG_NETFILTER_XT_MATCH_HELPER is not set +# CONFIG_NETFILTER_XT_MATCH_HL is not set +# CONFIG_NETFILTER_XT_MATCH_IPCOMP is not set +# CONFIG_NETFILTER_XT_MATCH_IPRANGE is not set +# CONFIG_NETFILTER_XT_MATCH_L2TP is not set +# CONFIG_NETFILTER_XT_MATCH_LENGTH is not set +# CONFIG_NETFILTER_XT_MATCH_LIMIT is not set +# CONFIG_NETFILTER_XT_MATCH_MAC is not set +# CONFIG_NETFILTER_XT_MATCH_MARK is not set +# CONFIG_NETFILTER_XT_MATCH_MULTIPORT is not set +# CONFIG_NETFILTER_XT_MATCH_NFACCT is not set +# CONFIG_NETFILTER_XT_MATCH_OSF is not set +# CONFIG_NETFILTER_XT_MATCH_OWNER is not set +# CONFIG_NETFILTER_XT_MATCH_POLICY is not set +# CONFIG_NETFILTER_XT_MATCH_PHYSDEV is not set +# CONFIG_NETFILTER_XT_MATCH_PKTTYPE is not set +# CONFIG_NETFILTER_XT_MATCH_QUOTA is not set +# CONFIG_NETFILTER_XT_MATCH_RATEEST is not set +# CONFIG_NETFILTER_XT_MATCH_REALM is not set +# CONFIG_NETFILTER_XT_MATCH_RECENT is not set +# CONFIG_NETFILTER_XT_MATCH_SCTP is not set +# CONFIG_NETFILTER_XT_MATCH_SOCKET is not set +# CONFIG_NETFILTER_XT_MATCH_STATE is not set +# CONFIG_NETFILTER_XT_MATCH_STATISTIC is not set +# CONFIG_NETFILTER_XT_MATCH_STRING is not set +# CONFIG_NETFILTER_XT_MATCH_TCPMSS is not set +# CONFIG_NETFILTER_XT_MATCH_TIME is not set +# CONFIG_NETFILTER_XT_MATCH_U32 is not set +# end of Core Netfilter Configuration + +# CONFIG_IP_SET is not set +# CONFIG_IP_VS is not set + +# +# IP: Netfilter Configuration +# +CONFIG_NF_DEFRAG_IPV4=y +CONFIG_NF_SOCKET_IPV4=y +CONFIG_NF_TPROXY_IPV4=y +CONFIG_NF_TABLES_IPV4=y +CONFIG_NFT_REJECT_IPV4=y +CONFIG_NFT_DUP_IPV4=y +# CONFIG_NFT_FIB_IPV4 is not set +# CONFIG_NF_TABLES_ARP is not set +CONFIG_NF_DUP_IPV4=y +# CONFIG_NF_LOG_ARP is not set +# CONFIG_NF_LOG_IPV4 is not set +CONFIG_NF_REJECT_IPV4=y +CONFIG_IP_NF_IPTABLES=y +# CONFIG_IP_NF_MATCH_AH is not set +# CONFIG_IP_NF_MATCH_ECN is not set +# CONFIG_IP_NF_MATCH_RPFILTER is not set +# CONFIG_IP_NF_MATCH_TTL is not set +CONFIG_IP_NF_FILTER=y +# CONFIG_IP_NF_TARGET_REJECT is not set +# CONFIG_IP_NF_TARGET_SYNPROXY is not set +CONFIG_IP_NF_NAT=y +CONFIG_IP_NF_TARGET_MASQUERADE=y +# CONFIG_IP_NF_TARGET_NETMAP is not set +CONFIG_IP_NF_TARGET_REDIRECT=y +CONFIG_IP_NF_MANGLE=y +# CONFIG_IP_NF_TARGET_CLUSTERIP is not set +# CONFIG_IP_NF_TARGET_ECN is not set +# CONFIG_IP_NF_TARGET_TTL is not set +# CONFIG_IP_NF_RAW is not set +# CONFIG_IP_NF_SECURITY is not set +# CONFIG_IP_NF_ARPTABLES is not set +# end of IP: Netfilter Configuration + +# +# IPv6: Netfilter Configuration +# +CONFIG_NF_SOCKET_IPV6=y +CONFIG_NF_TPROXY_IPV6=y +CONFIG_NF_TABLES_IPV6=y +CONFIG_NFT_REJECT_IPV6=y +# CONFIG_NFT_DUP_IPV6 is not set +# CONFIG_NFT_FIB_IPV6 is not set +# CONFIG_NF_DUP_IPV6 is not set +CONFIG_NF_REJECT_IPV6=y +# CONFIG_NF_LOG_IPV6 is not set +CONFIG_IP6_NF_IPTABLES=y +# CONFIG_IP6_NF_MATCH_AH is not set +# CONFIG_IP6_NF_MATCH_EUI64 is not set +# CONFIG_IP6_NF_MATCH_FRAG is not set +# CONFIG_IP6_NF_MATCH_OPTS is not set +# CONFIG_IP6_NF_MATCH_HL is not set +# CONFIG_IP6_NF_MATCH_IPV6HEADER is not set +# CONFIG_IP6_NF_MATCH_MH is not set +# CONFIG_IP6_NF_MATCH_RPFILTER is not set +# CONFIG_IP6_NF_MATCH_RT is not set +# CONFIG_IP6_NF_MATCH_SRH is not set +# CONFIG_IP6_NF_TARGET_HL is not set +# CONFIG_IP6_NF_FILTER is not set +# CONFIG_IP6_NF_TARGET_SYNPROXY is not set +CONFIG_IP6_NF_MANGLE=y +# CONFIG_IP6_NF_RAW is not set +# CONFIG_IP6_NF_SECURITY is not set +CONFIG_IP6_NF_NAT=y +CONFIG_IP6_NF_TARGET_MASQUERADE=y +# CONFIG_IP6_NF_TARGET_NPT is not set +# end of IPv6: Netfilter Configuration + +CONFIG_NF_DEFRAG_IPV6=y +CONFIG_NF_TABLES_BRIDGE=y +# CONFIG_NFT_BRIDGE_META is not set +# CONFIG_NFT_BRIDGE_REJECT is not set +# CONFIG_NF_LOG_BRIDGE is not set +# CONFIG_NF_CONNTRACK_BRIDGE is not set +# CONFIG_BRIDGE_NF_EBTABLES is not set +# CONFIG_BPFILTER is not set +# CONFIG_IP_DCCP is not set +# CONFIG_IP_SCTP is not set +# CONFIG_RDS is not set +# CONFIG_TIPC is not set +# CONFIG_ATM is not set +# CONFIG_L2TP is not set +CONFIG_STP=y +CONFIG_BRIDGE=y +CONFIG_BRIDGE_IGMP_SNOOPING=y +# CONFIG_BRIDGE_MRP is not set +# CONFIG_BRIDGE_CFM is not set +CONFIG_HAVE_NET_DSA=y +# CONFIG_NET_DSA is not set +# CONFIG_VLAN_8021Q is not set +# CONFIG_DECNET is not set +CONFIG_LLC=y +# CONFIG_LLC2 is not set +# CONFIG_ATALK is not set +# CONFIG_X25 is not set +# CONFIG_LAPB is not set +# CONFIG_PHONET is not set +# CONFIG_6LOWPAN is not set +# CONFIG_IEEE802154 is not set +# CONFIG_NET_SCHED is not set +# CONFIG_DCB is not set +CONFIG_DNS_RESOLVER=y +# CONFIG_BATMAN_ADV is not set +# CONFIG_OPENVSWITCH is not set +# CONFIG_VSOCKETS is not set +CONFIG_NETLINK_DIAG=y +# CONFIG_MPLS is not set +# CONFIG_NET_NSH is not set +# CONFIG_HSR is not set +# CONFIG_NET_SWITCHDEV is not set +CONFIG_NET_L3_MASTER_DEV=y +# CONFIG_QRTR is not set +# CONFIG_NET_NCSI is not set +CONFIG_RPS=y +CONFIG_RFS_ACCEL=y +CONFIG_XPS=y +CONFIG_CGROUP_NET_PRIO=y +CONFIG_CGROUP_NET_CLASSID=y +CONFIG_NET_RX_BUSY_POLL=y +CONFIG_BQL=y +CONFIG_BPF_JIT=y +# CONFIG_BPF_STREAM_PARSER is not set +CONFIG_NET_FLOW_LIMIT=y + +# +# Network testing +# +# CONFIG_NET_PKTGEN is not set +# CONFIG_NET_DROP_MONITOR is not set +# end of Network testing +# end of Networking options + +# CONFIG_HAMRADIO is not set +# CONFIG_CAN is not set +CONFIG_BT=y +CONFIG_BT_BREDR=y +CONFIG_BT_RFCOMM=y +CONFIG_BT_RFCOMM_TTY=y +CONFIG_BT_BNEP=y +# CONFIG_BT_BNEP_MC_FILTER is not set +# CONFIG_BT_BNEP_PROTO_FILTER is not set +CONFIG_BT_HIDP=y +CONFIG_BT_HS=y +CONFIG_BT_LE=y +# CONFIG_BT_LEDS is not set +CONFIG_BT_MSFTEXT=y +CONFIG_BT_DEBUGFS=y +# CONFIG_BT_SELFTEST is not set + +# +# Bluetooth device drivers +# +CONFIG_BT_INTEL=y +CONFIG_BT_BCM=y +CONFIG_BT_RTL=y +CONFIG_BT_HCIBTUSB=y +CONFIG_BT_HCIBTUSB_AUTOSUSPEND=y +CONFIG_BT_HCIBTUSB_BCM=y +CONFIG_BT_HCIBTUSB_MTK=y +CONFIG_BT_HCIBTUSB_RTL=y +# CONFIG_BT_HCIBTSDIO is not set +# CONFIG_BT_HCIUART is not set +CONFIG_BT_HCIBCM203X=y +# CONFIG_BT_HCIBPA10X is not set +# CONFIG_BT_HCIBFUSB is not set +# CONFIG_BT_HCIVHCI is not set +CONFIG_BT_MRVL=y +# CONFIG_BT_MRVL_SDIO is not set +CONFIG_BT_ATH3K=y +# CONFIG_BT_MTKSDIO is not set +# CONFIG_BT_MTKUART is not set +# end of Bluetooth device drivers + +# CONFIG_AF_RXRPC is not set +# CONFIG_AF_KCM is not set +CONFIG_FIB_RULES=y +CONFIG_WIRELESS=y +CONFIG_CFG80211=y +# CONFIG_NL80211_TESTMODE is not set +# CONFIG_CFG80211_DEVELOPER_WARNINGS is not set +CONFIG_CFG80211_CERTIFICATION_ONUS=y +# CONFIG_CFG80211_REQUIRE_SIGNED_REGDB is not set +# CONFIG_CFG80211_REG_CELLULAR_HINTS is not set +# CONFIG_CFG80211_REG_RELAX_NO_IR is not set +CONFIG_CFG80211_DEFAULT_PS=y +CONFIG_CFG80211_DEBUGFS=y +CONFIG_CFG80211_CRDA_SUPPORT=y +# CONFIG_CFG80211_WEXT is not set +CONFIG_MAC80211=y +CONFIG_MAC80211_HAS_RC=y +CONFIG_MAC80211_RC_MINSTREL=y +CONFIG_MAC80211_RC_DEFAULT_MINSTREL=y +CONFIG_MAC80211_RC_DEFAULT="minstrel_ht" +CONFIG_MAC80211_MESH=y +CONFIG_MAC80211_LEDS=y +CONFIG_MAC80211_DEBUGFS=y +# CONFIG_MAC80211_MESSAGE_TRACING is not set +# CONFIG_MAC80211_DEBUG_MENU is not set +CONFIG_MAC80211_STA_HASH_MAX_SIZE=0 +CONFIG_RFKILL=y +CONFIG_RFKILL_LEDS=y +CONFIG_RFKILL_INPUT=y +CONFIG_RFKILL_GPIO=y +# CONFIG_NET_9P is not set +# CONFIG_CAIF is not set +# CONFIG_CEPH_LIB is not set +# CONFIG_NFC is not set +# CONFIG_PSAMPLE is not set +# CONFIG_NET_IFE is not set +CONFIG_LWTUNNEL=y +CONFIG_LWTUNNEL_BPF=y +CONFIG_DST_CACHE=y +CONFIG_GRO_CELLS=y +CONFIG_FAILOVER=y +CONFIG_ETHTOOL_NETLINK=y +CONFIG_HAVE_EBPF_JIT=y + +# +# Device Drivers +# +CONFIG_ARM_AMBA=y +CONFIG_HAVE_PCI=y +CONFIG_PCI=y +CONFIG_PCI_DOMAINS=y +CONFIG_PCI_DOMAINS_GENERIC=y +CONFIG_PCI_SYSCALL=y +CONFIG_PCIEPORTBUS=y +CONFIG_PCIEAER=y +# CONFIG_PCIEAER_INJECT is not set +# CONFIG_PCIE_ECRC is not set +CONFIG_PCIEASPM=y +# CONFIG_PCIEASPM_DEFAULT is not set +# CONFIG_PCIEASPM_POWERSAVE is not set +# CONFIG_PCIEASPM_POWER_SUPERSAVE is not set +CONFIG_PCIEASPM_PERFORMANCE=y +CONFIG_PCIE_PME=y +CONFIG_PCIE_DPC=y +CONFIG_PCIE_PTM=y +CONFIG_PCIE_BW=y +CONFIG_PCI_MSI=y +CONFIG_PCI_MSI_IRQ_DOMAIN=y +CONFIG_PCI_QUIRKS=y +# CONFIG_PCI_DEBUG is not set +# CONFIG_PCI_STUB is not set +CONFIG_PCI_ATS=y +CONFIG_PCI_ECAM=y +# CONFIG_PCI_IOV is not set +CONFIG_PCI_PRI=y +CONFIG_PCI_PASID=y +CONFIG_PCI_LABEL=y +# CONFIG_PCIE_BUS_TUNE_OFF is not set +CONFIG_PCIE_BUS_DEFAULT=y +# CONFIG_PCIE_BUS_SAFE is not set +# CONFIG_PCIE_BUS_PERFORMANCE is not set +# CONFIG_PCIE_BUS_PEER2PEER is not set +# CONFIG_HOTPLUG_PCI is not set + +# +# PCI controller drivers +# +# CONFIG_PCI_FTPCI100 is not set +CONFIG_PCI_HOST_COMMON=y +CONFIG_PCI_HOST_GENERIC=y +# CONFIG_PCIE_XILINX is not set +# CONFIG_PCI_XGENE is not set +# CONFIG_PCIE_ALTERA is not set +# CONFIG_PCI_HOST_THUNDER_PEM is not set +# CONFIG_PCI_HOST_THUNDER_ECAM is not set + +# +# DesignWare PCI Core Support +# +CONFIG_PCIE_DW=y +CONFIG_PCIE_DW_HOST=y +# CONFIG_PCIE_DW_PLAT_HOST is not set +CONFIG_PCI_IMX6=y +# CONFIG_PCI_HISI is not set +# CONFIG_PCIE_KIRIN is not set +# CONFIG_PCI_MESON is not set +# CONFIG_PCIE_AL is not set +# end of DesignWare PCI Core Support + +# +# Mobiveil PCIe Core Support +# +# CONFIG_PCIE_LAYERSCAPE_GEN4 is not set +# end of Mobiveil PCIe Core Support + +# +# Cadence PCIe controllers support +# +# CONFIG_PCIE_CADENCE_PLAT_HOST is not set +# CONFIG_PCI_J721E_HOST is not set +# end of Cadence PCIe controllers support +# end of PCI controller drivers + +# +# PCI Endpoint +# +# CONFIG_PCI_ENDPOINT is not set +# end of PCI Endpoint + +# +# PCI switch controller drivers +# +# CONFIG_PCI_SW_SWITCHTEC is not set +# end of PCI switch controller drivers + +# CONFIG_PCCARD is not set +# CONFIG_RAPIDIO is not set + +# +# Generic Driver Options +# +# CONFIG_UEVENT_HELPER is not set +CONFIG_DEVTMPFS=y +CONFIG_DEVTMPFS_MOUNT=y +CONFIG_STANDALONE=y +CONFIG_PREVENT_FIRMWARE_BUILD=y + +# +# Firmware loader +# +CONFIG_FW_LOADER=y +CONFIG_FW_LOADER_PAGED_BUF=y +CONFIG_EXTRA_FIRMWARE="" +CONFIG_FW_LOADER_USER_HELPER=y +# CONFIG_FW_LOADER_USER_HELPER_FALLBACK is not set +# CONFIG_FW_LOADER_COMPRESS is not set +CONFIG_FW_CACHE=y +# end of Firmware loader + +CONFIG_WANT_DEV_COREDUMP=y +CONFIG_ALLOW_DEV_COREDUMP=y +CONFIG_DEV_COREDUMP=y +# CONFIG_DEBUG_DRIVER is not set +# CONFIG_DEBUG_DEVRES is not set +# CONFIG_DEBUG_TEST_DRIVER_REMOVE is not set +# CONFIG_TEST_ASYNC_DRIVER_PROBE is not set +CONFIG_GENERIC_CPU_AUTOPROBE=y +CONFIG_GENERIC_CPU_VULNERABILITIES=y +CONFIG_SOC_BUS=y +CONFIG_REGMAP=y +CONFIG_REGMAP_I2C=y +CONFIG_REGMAP_SPI=y +CONFIG_REGMAP_MMIO=y +CONFIG_DMA_SHARED_BUFFER=y +# CONFIG_DMA_FENCE_TRACE is not set +CONFIG_GENERIC_ARCH_TOPOLOGY=y +# end of Generic Driver Options + +# +# Bus devices +# +# CONFIG_BRCMSTB_GISB_ARB is not set +# CONFIG_MOXTET is not set +# CONFIG_IMX_WEIM is not set +# CONFIG_SIMPLE_PM_BUS is not set +# CONFIG_VEXPRESS_CONFIG is not set +# CONFIG_FSL_MC_BUS is not set +# CONFIG_MHI_BUS is not set +# end of Bus devices + +CONFIG_CONNECTOR=y +CONFIG_PROC_EVENTS=y +# CONFIG_GNSS is not set +# CONFIG_MTD is not set +CONFIG_DTC=y +CONFIG_OF=y +# CONFIG_OF_UNITTEST is not set +CONFIG_OF_FLATTREE=y +CONFIG_OF_EARLY_FLATTREE=y +CONFIG_OF_KOBJ=y +CONFIG_OF_ADDRESS=y +CONFIG_OF_IRQ=y +CONFIG_OF_NET=y +CONFIG_OF_RESERVED_MEM=y +# CONFIG_OF_OVERLAY is not set +CONFIG_OF_NUMA=y +# CONFIG_PARPORT is not set +CONFIG_BLK_DEV=y +# CONFIG_BLK_DEV_NULL_BLK is not set +CONFIG_BLK_DEV_PCIESSD_MTIP32XX=y +# CONFIG_BLK_DEV_UMEM is not set +CONFIG_BLK_DEV_LOOP=y +CONFIG_BLK_DEV_LOOP_MIN_COUNT=8 +# CONFIG_BLK_DEV_CRYPTOLOOP is not set +# CONFIG_BLK_DEV_DRBD is not set +# CONFIG_BLK_DEV_NBD is not set +# CONFIG_BLK_DEV_SKD is not set +# CONFIG_BLK_DEV_SX8 is not set +# CONFIG_BLK_DEV_RAM is not set +# CONFIG_CDROM_PKTCDVD is not set +# CONFIG_ATA_OVER_ETH is not set +# CONFIG_XEN_BLKDEV_FRONTEND is not set +CONFIG_VIRTIO_BLK=y +# CONFIG_BLK_DEV_RBD is not set +# CONFIG_BLK_DEV_RSXX is not set + +# +# NVME Support +# +CONFIG_NVME_CORE=y +CONFIG_BLK_DEV_NVME=y +CONFIG_NVME_MULTIPATH=y +CONFIG_NVME_HWMON=y +# CONFIG_NVME_FC is not set +# CONFIG_NVME_TCP is not set +# end of NVME Support + +# +# Misc devices +# +# CONFIG_AD525X_DPOT is not set +# CONFIG_DUMMY_IRQ is not set +# CONFIG_PHANTOM is not set +# CONFIG_TIFM_CORE is not set +# CONFIG_ICS932S401 is not set +# CONFIG_ENCLOSURE_SERVICES is not set +# CONFIG_HP_ILO is not set +# CONFIG_APDS9802ALS is not set +# CONFIG_ISL29003 is not set +# CONFIG_ISL29020 is not set +# CONFIG_SENSORS_TSL2550 is not set +# CONFIG_SENSORS_BH1770 is not set +# CONFIG_SENSORS_APDS990X is not set +# CONFIG_HMC6352 is not set +# CONFIG_DS1682 is not set +# CONFIG_LATTICE_ECP3_CONFIG is not set +# CONFIG_SRAM is not set +# CONFIG_PCI_ENDPOINT_TEST is not set +# CONFIG_XILINX_SDFEC is not set +# CONFIG_PVPANIC is not set +# CONFIG_HISI_HIKEY_USB is not set +# CONFIG_C2PORT is not set + +# +# EEPROM support +# +CONFIG_EEPROM_AT24=y +CONFIG_EEPROM_AT25=y +# CONFIG_EEPROM_LEGACY is not set +# CONFIG_EEPROM_MAX6875 is not set +CONFIG_EEPROM_93CX6=y +# CONFIG_EEPROM_93XX46 is not set +# CONFIG_EEPROM_IDT_89HPESX is not set +# CONFIG_EEPROM_EE1004 is not set +# end of EEPROM support + +# CONFIG_CB710_CORE is not set + +# +# Texas Instruments shared transport line discipline +# +# CONFIG_TI_ST is not set +# end of Texas Instruments shared transport line discipline + +# CONFIG_SENSORS_LIS3_SPI is not set +# CONFIG_SENSORS_LIS3_I2C is not set +# CONFIG_ALTERA_STAPL is not set +# CONFIG_GENWQE is not set +# CONFIG_ECHO is not set +# CONFIG_MISC_ALCOR_PCI is not set +# CONFIG_MISC_RTSX_PCI is not set +# CONFIG_MISC_RTSX_USB is not set +# CONFIG_HABANA_AI is not set +# CONFIG_UACCE is not set +# end of Misc devices + +# +# SCSI device support +# +CONFIG_SCSI_MOD=y +# CONFIG_RAID_ATTRS is not set +CONFIG_SCSI=y +CONFIG_SCSI_DMA=y +# CONFIG_SCSI_PROC_FS is not set + +# +# SCSI support type (disk, tape, CD-ROM) +# +CONFIG_BLK_DEV_SD=y +# CONFIG_CHR_DEV_ST is not set +# CONFIG_BLK_DEV_SR is not set +CONFIG_CHR_DEV_SG=y +# CONFIG_CHR_DEV_SCH is not set +CONFIG_SCSI_CONSTANTS=y +CONFIG_SCSI_LOGGING=y +# CONFIG_SCSI_SCAN_ASYNC is not set + +# +# SCSI Transports +# +# CONFIG_SCSI_SPI_ATTRS is not set +# CONFIG_SCSI_FC_ATTRS is not set +# CONFIG_SCSI_ISCSI_ATTRS is not set +# CONFIG_SCSI_SAS_ATTRS is not set +# CONFIG_SCSI_SAS_LIBSAS is not set +# CONFIG_SCSI_SRP_ATTRS is not set +# end of SCSI Transports + +CONFIG_SCSI_LOWLEVEL=y +# CONFIG_ISCSI_TCP is not set +# CONFIG_ISCSI_BOOT_SYSFS is not set +# CONFIG_SCSI_CXGB3_ISCSI is not set +# CONFIG_SCSI_CXGB4_ISCSI is not set +# CONFIG_SCSI_BNX2_ISCSI is not set +# CONFIG_BE2ISCSI is not set +# CONFIG_BLK_DEV_3W_XXXX_RAID is not set +# CONFIG_SCSI_HPSA is not set +# CONFIG_SCSI_3W_9XXX is not set +# CONFIG_SCSI_3W_SAS is not set +# CONFIG_SCSI_ACARD is not set +# CONFIG_SCSI_AACRAID is not set +# CONFIG_SCSI_AIC7XXX is not set +# CONFIG_SCSI_AIC79XX is not set +# CONFIG_SCSI_AIC94XX is not set +# CONFIG_SCSI_MVSAS is not set +# CONFIG_SCSI_MVUMI is not set +# CONFIG_SCSI_ADVANSYS is not set +# CONFIG_SCSI_ARCMSR is not set +# CONFIG_SCSI_ESAS2R is not set +# CONFIG_MEGARAID_NEWGEN is not set +# CONFIG_MEGARAID_LEGACY is not set +# CONFIG_MEGARAID_SAS is not set +# CONFIG_SCSI_MPT3SAS is not set +# CONFIG_SCSI_MPT2SAS is not set +# CONFIG_SCSI_SMARTPQI is not set +# CONFIG_SCSI_UFSHCD is not set +# CONFIG_SCSI_HPTIOP is not set +# CONFIG_SCSI_MYRB is not set +# CONFIG_SCSI_MYRS is not set +# CONFIG_XEN_SCSI_FRONTEND is not set +# CONFIG_SCSI_SNIC is not set +# CONFIG_SCSI_DMX3191D is not set +# CONFIG_SCSI_FDOMAIN_PCI is not set +# CONFIG_SCSI_GDTH is not set +# CONFIG_SCSI_IPS is not set +# CONFIG_SCSI_INITIO is not set +# CONFIG_SCSI_INIA100 is not set +# CONFIG_SCSI_STEX is not set +# CONFIG_SCSI_SYM53C8XX_2 is not set +# CONFIG_SCSI_QLOGIC_1280 is not set +# CONFIG_SCSI_QLA_ISCSI is not set +# CONFIG_SCSI_DC395x is not set +# CONFIG_SCSI_AM53C974 is not set +# CONFIG_SCSI_WD719X is not set +# CONFIG_SCSI_DEBUG is not set +# CONFIG_SCSI_PMCRAID is not set +# CONFIG_SCSI_PM8001 is not set +CONFIG_SCSI_VIRTIO=y +CONFIG_SCSI_DH=y +# CONFIG_SCSI_DH_RDAC is not set +# CONFIG_SCSI_DH_HP_SW is not set +# CONFIG_SCSI_DH_EMC is not set +# CONFIG_SCSI_DH_ALUA is not set +# end of SCSI device support + +CONFIG_HAVE_PATA_PLATFORM=y +# CONFIG_ATA is not set +CONFIG_MD=y +CONFIG_BLK_DEV_MD=y +CONFIG_MD_AUTODETECT=y +# CONFIG_MD_LINEAR is not set +# CONFIG_MD_RAID0 is not set +# CONFIG_MD_RAID1 is not set +# CONFIG_MD_RAID10 is not set +# CONFIG_MD_RAID456 is not set +# CONFIG_MD_MULTIPATH is not set +# CONFIG_MD_FAULTY is not set +# CONFIG_BCACHE is not set +CONFIG_BLK_DEV_DM_BUILTIN=y +CONFIG_BLK_DEV_DM=y +# CONFIG_DM_DEBUG is not set +CONFIG_DM_BUFIO=y +# CONFIG_DM_DEBUG_BLOCK_MANAGER_LOCKING is not set +CONFIG_DM_BIO_PRISON=y +CONFIG_DM_PERSISTENT_DATA=y +# CONFIG_DM_UNSTRIPED is not set +CONFIG_DM_CRYPT=y +# CONFIG_DM_SNAPSHOT is not set +CONFIG_DM_THIN_PROVISIONING=y +# CONFIG_DM_CACHE is not set +# CONFIG_DM_WRITECACHE is not set +# CONFIG_DM_EBS is not set +# CONFIG_DM_ERA is not set +# CONFIG_DM_CLONE is not set +# CONFIG_DM_MIRROR is not set +# CONFIG_DM_RAID is not set +# CONFIG_DM_ZERO is not set +# CONFIG_DM_MULTIPATH is not set +# CONFIG_DM_DELAY is not set +# CONFIG_DM_DUST is not set +# CONFIG_DM_INIT is not set +CONFIG_DM_UEVENT=y +# CONFIG_DM_FLAKEY is not set +# CONFIG_DM_VERITY is not set +# CONFIG_DM_SWITCH is not set +# CONFIG_DM_LOG_WRITES is not set +# CONFIG_DM_INTEGRITY is not set +# CONFIG_TARGET_CORE is not set +# CONFIG_FUSION is not set + +# +# IEEE 1394 (FireWire) support +# +# CONFIG_FIREWIRE is not set +# CONFIG_FIREWIRE_NOSY is not set +# end of IEEE 1394 (FireWire) support + +CONFIG_NETDEVICES=y +CONFIG_MII=y +CONFIG_NET_CORE=y +# CONFIG_BONDING is not set +# CONFIG_DUMMY is not set +CONFIG_WIREGUARD=y +# CONFIG_WIREGUARD_DEBUG is not set +# CONFIG_EQUALIZER is not set +# CONFIG_NET_FC is not set +# CONFIG_NET_TEAM is not set +CONFIG_MACVLAN=y +CONFIG_MACVTAP=y +CONFIG_IPVLAN_L3S=y +CONFIG_IPVLAN=y +CONFIG_IPVTAP=y +CONFIG_VXLAN=y +# CONFIG_GENEVE is not set +# CONFIG_BAREUDP is not set +# CONFIG_GTP is not set +# CONFIG_MACSEC is not set +# CONFIG_NETCONSOLE is not set +CONFIG_TUN=y +CONFIG_TAP=y +# CONFIG_TUN_VNET_CROSS_LE is not set +CONFIG_VETH=y +CONFIG_VIRTIO_NET=y +# CONFIG_NLMON is not set +# CONFIG_ARCNET is not set + +# +# Distributed Switch Architecture drivers +# +# end of Distributed Switch Architecture drivers + +CONFIG_ETHERNET=y +# CONFIG_NET_VENDOR_3COM is not set +# CONFIG_NET_VENDOR_ADAPTEC is not set +# CONFIG_NET_VENDOR_AGERE is not set +# CONFIG_NET_VENDOR_ALACRITECH is not set +# CONFIG_NET_VENDOR_ALTEON is not set +# CONFIG_ALTERA_TSE is not set +# CONFIG_NET_VENDOR_AMAZON is not set +# CONFIG_NET_VENDOR_AMD is not set +# CONFIG_NET_VENDOR_AQUANTIA is not set +# CONFIG_NET_VENDOR_ARC is not set +# CONFIG_NET_VENDOR_ATHEROS is not set +# CONFIG_NET_VENDOR_AURORA is not set +# CONFIG_NET_VENDOR_BROADCOM is not set +# CONFIG_NET_VENDOR_BROCADE is not set +# CONFIG_NET_VENDOR_CADENCE is not set +# CONFIG_NET_VENDOR_CAVIUM is not set +# CONFIG_NET_VENDOR_CHELSIO is not set +# CONFIG_NET_VENDOR_CISCO is not set +# CONFIG_NET_VENDOR_CORTINA is not set +# CONFIG_DNET is not set +# CONFIG_NET_VENDOR_DEC is not set +# CONFIG_NET_VENDOR_DLINK is not set +# CONFIG_NET_VENDOR_EMULEX is not set +# CONFIG_NET_VENDOR_EZCHIP is not set +CONFIG_NET_VENDOR_FREESCALE=y +CONFIG_FEC=y +# CONFIG_FSL_PQ_MDIO is not set +# CONFIG_FSL_XGMAC_MDIO is not set +# CONFIG_GIANFAR is not set +# CONFIG_FSL_ENETC is not set +# CONFIG_FSL_ENETC_VF is not set +# CONFIG_FSL_ENETC_MDIO is not set +# CONFIG_NET_VENDOR_GOOGLE is not set +# CONFIG_NET_VENDOR_HISILICON is not set +# CONFIG_NET_VENDOR_HUAWEI is not set +# CONFIG_NET_VENDOR_INTEL is not set +# CONFIG_JME is not set +# CONFIG_NET_VENDOR_MARVELL is not set +# CONFIG_NET_VENDOR_MELLANOX is not set +# CONFIG_NET_VENDOR_MICREL is not set +# CONFIG_NET_VENDOR_MICROCHIP is not set +# CONFIG_NET_VENDOR_MICROSEMI is not set +# CONFIG_NET_VENDOR_MYRI is not set +# CONFIG_FEALNX is not set +# CONFIG_NET_VENDOR_NATSEMI is not set +# CONFIG_NET_VENDOR_NETERION is not set +# CONFIG_NET_VENDOR_NETRONOME is not set +# CONFIG_NET_VENDOR_NI is not set +# CONFIG_NET_VENDOR_NVIDIA is not set +# CONFIG_NET_VENDOR_OKI is not set +# CONFIG_ETHOC is not set +# CONFIG_NET_VENDOR_PACKET_ENGINES is not set +# CONFIG_NET_VENDOR_PENSANDO is not set +# CONFIG_NET_VENDOR_QLOGIC is not set +# CONFIG_NET_VENDOR_QUALCOMM is not set +# CONFIG_NET_VENDOR_RDC is not set +# CONFIG_NET_VENDOR_REALTEK is not set +# CONFIG_NET_VENDOR_RENESAS is not set +# CONFIG_NET_VENDOR_ROCKER is not set +# CONFIG_NET_VENDOR_SAMSUNG is not set +# CONFIG_NET_VENDOR_SEEQ is not set +# CONFIG_NET_VENDOR_SOLARFLARE is not set +# CONFIG_NET_VENDOR_SILAN is not set +# CONFIG_NET_VENDOR_SIS is not set +# CONFIG_NET_VENDOR_SMSC is not set +# CONFIG_NET_VENDOR_SOCIONEXT is not set +# CONFIG_NET_VENDOR_STMICRO is not set +# CONFIG_NET_VENDOR_SUN is not set +# CONFIG_NET_VENDOR_SYNOPSYS is not set +# CONFIG_NET_VENDOR_TEHUTI is not set +# CONFIG_NET_VENDOR_TI is not set +# CONFIG_NET_VENDOR_VIA is not set +# CONFIG_NET_VENDOR_WIZNET is not set +# CONFIG_NET_VENDOR_XILINX is not set +# CONFIG_FDDI is not set +# CONFIG_HIPPI is not set +CONFIG_PHYLIB=y +CONFIG_SWPHY=y +# CONFIG_LED_TRIGGER_PHY is not set +CONFIG_FIXED_PHY=y + +# +# MII PHY device drivers +# +# CONFIG_AMD_PHY is not set +# CONFIG_ADIN_PHY is not set +# CONFIG_AQUANTIA_PHY is not set +# CONFIG_AX88796B_PHY is not set +# CONFIG_BROADCOM_PHY is not set +# CONFIG_BCM54140_PHY is not set +# CONFIG_BCM7XXX_PHY is not set +# CONFIG_BCM84881_PHY is not set +# CONFIG_BCM87XX_PHY is not set +# CONFIG_CICADA_PHY is not set +# CONFIG_CORTINA_PHY is not set +# CONFIG_DAVICOM_PHY is not set +# CONFIG_ICPLUS_PHY is not set +# CONFIG_LXT_PHY is not set +# CONFIG_INTEL_XWAY_PHY is not set +# CONFIG_LSI_ET1011C_PHY is not set +# CONFIG_MARVELL_PHY is not set +# CONFIG_MARVELL_10G_PHY is not set +# CONFIG_MICREL_PHY is not set +# CONFIG_MICROCHIP_PHY is not set +# CONFIG_MICROCHIP_T1_PHY is not set +# CONFIG_MICROSEMI_PHY is not set +# CONFIG_NATIONAL_PHY is not set +# CONFIG_NXP_TJA11XX_PHY is not set +CONFIG_AT803X_PHY=y +# CONFIG_QSEMI_PHY is not set +# CONFIG_REALTEK_PHY is not set +# CONFIG_RENESAS_PHY is not set +# CONFIG_ROCKCHIP_PHY is not set +# CONFIG_SMSC_PHY is not set +# CONFIG_STE10XP is not set +# CONFIG_TERANETICS_PHY is not set +# CONFIG_DP83822_PHY is not set +# CONFIG_DP83TC811_PHY is not set +# CONFIG_DP83848_PHY is not set +# CONFIG_DP83867_PHY is not set +# CONFIG_DP83869_PHY is not set +# CONFIG_VITESSE_PHY is not set +# CONFIG_XILINX_GMII2RGMII is not set +# CONFIG_MICREL_KS8995MA is not set +CONFIG_MDIO_DEVICE=y +CONFIG_MDIO_BUS=y +CONFIG_OF_MDIO=y +CONFIG_MDIO_DEVRES=y +# CONFIG_MDIO_BITBANG is not set +# CONFIG_MDIO_BCM_UNIMAC is not set +# CONFIG_MDIO_HISI_FEMAC is not set +# CONFIG_MDIO_MVUSB is not set +# CONFIG_MDIO_MSCC_MIIM is not set +# CONFIG_MDIO_OCTEON is not set +# CONFIG_MDIO_IPQ4019 is not set +# CONFIG_MDIO_IPQ8064 is not set +# CONFIG_MDIO_THUNDER is not set + +# +# MDIO Multiplexers +# +CONFIG_MDIO_BUS_MUX=y +# CONFIG_MDIO_BUS_MUX_GPIO is not set +CONFIG_MDIO_BUS_MUX_MULTIPLEXER=y +# CONFIG_MDIO_BUS_MUX_MMIOREG is not set + +# +# PCS device drivers +# +# CONFIG_PCS_XPCS is not set +# end of PCS device drivers + +# CONFIG_PPP is not set +# CONFIG_SLIP is not set +CONFIG_USB_NET_DRIVERS=y +# CONFIG_USB_CATC is not set +# CONFIG_USB_KAWETH is not set +# CONFIG_USB_PEGASUS is not set +# CONFIG_USB_RTL8150 is not set +# CONFIG_USB_RTL8152 is not set +# CONFIG_USB_LAN78XX is not set +CONFIG_USB_USBNET=y +# CONFIG_USB_NET_AX8817X is not set +# CONFIG_USB_NET_AX88179_178A is not set +CONFIG_USB_NET_CDCETHER=y +CONFIG_USB_NET_CDC_EEM=y +# CONFIG_USB_NET_CDC_NCM is not set +# CONFIG_USB_NET_HUAWEI_CDC_NCM is not set +# CONFIG_USB_NET_CDC_MBIM is not set +# CONFIG_USB_NET_DM9601 is not set +# CONFIG_USB_NET_SR9700 is not set +# CONFIG_USB_NET_SR9800 is not set +# CONFIG_USB_NET_SMSC75XX is not set +# CONFIG_USB_NET_SMSC95XX is not set +# CONFIG_USB_NET_GL620A is not set +# CONFIG_USB_NET_NET1080 is not set +# CONFIG_USB_NET_PLUSB is not set +# CONFIG_USB_NET_MCS7830 is not set +# CONFIG_USB_NET_RNDIS_HOST is not set +# CONFIG_USB_NET_CDC_SUBSET is not set +# CONFIG_USB_NET_ZAURUS is not set +# CONFIG_USB_NET_CX82310_ETH is not set +# CONFIG_USB_NET_KALMIA is not set +# CONFIG_USB_NET_QMI_WWAN is not set +# CONFIG_USB_HSO is not set +# CONFIG_USB_NET_INT51X1 is not set +CONFIG_USB_IPHETH=y +# CONFIG_USB_SIERRA_NET is not set +# CONFIG_USB_VL600 is not set +# CONFIG_USB_NET_CH9200 is not set +# CONFIG_USB_NET_AQC111 is not set +# CONFIG_USB_RTL8153_ECM is not set +CONFIG_WLAN=y +# CONFIG_WLAN_VENDOR_ADMTEK is not set +CONFIG_ATH_COMMON=y +CONFIG_WLAN_VENDOR_ATH=y +# CONFIG_ATH_DEBUG is not set +# CONFIG_ATH_REG_DYNAMIC_USER_REG_HINTS is not set +CONFIG_ATH5K=y +CONFIG_ATH5K_DEBUG=y +# CONFIG_ATH5K_TRACER is not set +CONFIG_ATH5K_PCI=y +# CONFIG_ATH5K_TEST_CHANNELS is not set +CONFIG_ATH9K_HW=y +CONFIG_ATH9K_COMMON=y +CONFIG_ATH9K_BTCOEX_SUPPORT=y +CONFIG_ATH9K=y +CONFIG_ATH9K_PCI=y +# CONFIG_ATH9K_AHB is not set +# CONFIG_ATH9K_DEBUGFS is not set +# CONFIG_ATH9K_DFS_CERTIFIED is not set +# CONFIG_ATH9K_DYNACK is not set +# CONFIG_ATH9K_WOW is not set +CONFIG_ATH9K_RFKILL=y +CONFIG_ATH9K_CHANNEL_CONTEXT=y +CONFIG_ATH9K_PCOEM=y +# CONFIG_ATH9K_PCI_NO_EEPROM is not set +CONFIG_ATH9K_HTC=y +# CONFIG_ATH9K_HTC_DEBUGFS is not set +CONFIG_ATH9K_HWRNG=y +# CONFIG_CARL9170 is not set +# CONFIG_ATH6KL is not set +CONFIG_AR5523=y +# CONFIG_WIL6210 is not set +CONFIG_ATH10K=y +CONFIG_ATH10K_CE=y +CONFIG_ATH10K_PCI=y +# CONFIG_ATH10K_AHB is not set +# CONFIG_ATH10K_SDIO is not set +# CONFIG_ATH10K_USB is not set +# CONFIG_ATH10K_DEBUG is not set +# CONFIG_ATH10K_DEBUGFS is not set +# CONFIG_ATH10K_TRACING is not set +# CONFIG_ATH10K_DFS_CERTIFIED is not set +# CONFIG_WCN36XX is not set +# CONFIG_WLAN_VENDOR_ATMEL is not set +CONFIG_WLAN_VENDOR_BROADCOM=y +# CONFIG_B43 is not set +# CONFIG_B43LEGACY is not set +# CONFIG_BRCMSMAC is not set +# CONFIG_BRCMFMAC is not set +# CONFIG_WLAN_VENDOR_CISCO is not set +CONFIG_WLAN_VENDOR_INTEL=y +# CONFIG_IPW2100 is not set +# CONFIG_IPW2200 is not set +# CONFIG_IWL4965 is not set +# CONFIG_IWL3945 is not set +CONFIG_IWLWIFI=m +CONFIG_IWLWIFI_LEDS=y +# CONFIG_IWLDVM is not set +CONFIG_IWLMVM=m +CONFIG_IWLWIFI_OPMODE_MODULAR=y +# CONFIG_IWLWIFI_BCAST_FILTERING is not set + +# +# Debugging Options +# +# CONFIG_IWLWIFI_DEBUG is not set +# CONFIG_IWLWIFI_DEBUGFS is not set +CONFIG_IWLWIFI_DEVICE_TRACING=y +# end of Debugging Options + +# CONFIG_WLAN_VENDOR_INTERSIL is not set +# CONFIG_WLAN_VENDOR_MARVELL is not set +CONFIG_WLAN_VENDOR_MEDIATEK=y +# CONFIG_MT7601U is not set +# CONFIG_MT76x0U is not set +# CONFIG_MT76x0E is not set +# CONFIG_MT76x2E is not set +# CONFIG_MT76x2U is not set +# CONFIG_MT7603E is not set +# CONFIG_MT7615E is not set +# CONFIG_MT7663U is not set +# CONFIG_MT7663S is not set +# CONFIG_MT7915E is not set +CONFIG_WLAN_VENDOR_MICROCHIP=y +# CONFIG_WILC1000_SDIO is not set +# CONFIG_WILC1000_SPI is not set +# CONFIG_WLAN_VENDOR_RALINK is not set +CONFIG_WLAN_VENDOR_REALTEK=y +# CONFIG_RTL8180 is not set +# CONFIG_RTL8187 is not set +# CONFIG_RTL_CARDS is not set +# CONFIG_RTL8XXXU is not set +# CONFIG_RTW88 is not set +# CONFIG_WLAN_VENDOR_RSI is not set +# CONFIG_WLAN_VENDOR_ST is not set +# CONFIG_WLAN_VENDOR_TI is not set +# CONFIG_WLAN_VENDOR_ZYDAS is not set +# CONFIG_WLAN_VENDOR_QUANTENNA is not set +# CONFIG_MAC80211_HWSIM is not set +# CONFIG_USB_NET_RNDIS_WLAN is not set +# CONFIG_VIRT_WIFI is not set +# CONFIG_WAN is not set +# CONFIG_XEN_NETDEV_FRONTEND is not set +# CONFIG_VMXNET3 is not set +# CONFIG_NETDEVSIM is not set +CONFIG_NET_FAILOVER=y +# CONFIG_ISDN is not set +# CONFIG_NVM is not set + +# +# Input device support +# +CONFIG_INPUT=y +CONFIG_INPUT_LEDS=y +CONFIG_INPUT_FF_MEMLESS=y +# CONFIG_INPUT_SPARSEKMAP is not set +# CONFIG_INPUT_MATRIXKMAP is not set + +# +# Userland interfaces +# +CONFIG_INPUT_MOUSEDEV=y +CONFIG_INPUT_MOUSEDEV_PSAUX=y +CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024 +CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768 +CONFIG_INPUT_JOYDEV=y +CONFIG_INPUT_EVDEV=y +# CONFIG_INPUT_EVBUG is not set + +# +# Input Device Drivers +# +CONFIG_INPUT_KEYBOARD=y +# CONFIG_KEYBOARD_ADP5588 is not set +# CONFIG_KEYBOARD_ADP5589 is not set +# CONFIG_KEYBOARD_ATKBD is not set +# CONFIG_KEYBOARD_QT1050 is not set +# CONFIG_KEYBOARD_QT1070 is not set +# CONFIG_KEYBOARD_QT2160 is not set +# CONFIG_KEYBOARD_DLINK_DIR685 is not set +# CONFIG_KEYBOARD_LKKBD is not set +# CONFIG_KEYBOARD_GPIO is not set +# CONFIG_KEYBOARD_GPIO_POLLED is not set +# CONFIG_KEYBOARD_TCA6416 is not set +# CONFIG_KEYBOARD_TCA8418 is not set +# CONFIG_KEYBOARD_MATRIX is not set +# CONFIG_KEYBOARD_LM8323 is not set +# CONFIG_KEYBOARD_LM8333 is not set +# CONFIG_KEYBOARD_MAX7359 is not set +# CONFIG_KEYBOARD_MCS is not set +# CONFIG_KEYBOARD_MPR121 is not set +CONFIG_KEYBOARD_SNVS_PWRKEY=y +# CONFIG_KEYBOARD_IMX is not set +# CONFIG_KEYBOARD_NEWTON is not set +# CONFIG_KEYBOARD_OPENCORES is not set +# CONFIG_KEYBOARD_SAMSUNG is not set +# CONFIG_KEYBOARD_STOWAWAY is not set +# CONFIG_KEYBOARD_SUNKBD is not set +# CONFIG_KEYBOARD_OMAP4 is not set +# CONFIG_KEYBOARD_TM2_TOUCHKEY is not set +# CONFIG_KEYBOARD_XTKBD is not set +# CONFIG_KEYBOARD_CAP11XX is not set +# CONFIG_KEYBOARD_BCM is not set +CONFIG_INPUT_MOUSE=y +# CONFIG_MOUSE_PS2 is not set +# CONFIG_MOUSE_SERIAL is not set +# CONFIG_MOUSE_APPLETOUCH is not set +# CONFIG_MOUSE_BCM5974 is not set +# CONFIG_MOUSE_CYAPA is not set +# CONFIG_MOUSE_ELAN_I2C is not set +# CONFIG_MOUSE_VSXXXAA is not set +# CONFIG_MOUSE_GPIO is not set +# CONFIG_MOUSE_SYNAPTICS_I2C is not set +# CONFIG_MOUSE_SYNAPTICS_USB is not set +CONFIG_INPUT_JOYSTICK=y +# CONFIG_JOYSTICK_ANALOG is not set +# CONFIG_JOYSTICK_A3D is not set +# CONFIG_JOYSTICK_ADI is not set +# CONFIG_JOYSTICK_COBRA is not set +# CONFIG_JOYSTICK_GF2K is not set +# CONFIG_JOYSTICK_GRIP is not set +# CONFIG_JOYSTICK_GRIP_MP is not set +# CONFIG_JOYSTICK_GUILLEMOT is not set +# CONFIG_JOYSTICK_INTERACT is not set +# CONFIG_JOYSTICK_SIDEWINDER is not set +# CONFIG_JOYSTICK_TMDC is not set +# CONFIG_JOYSTICK_IFORCE is not set +# CONFIG_JOYSTICK_WARRIOR is not set +# CONFIG_JOYSTICK_MAGELLAN is not set +# CONFIG_JOYSTICK_SPACEORB is not set +# CONFIG_JOYSTICK_SPACEBALL is not set +# CONFIG_JOYSTICK_STINGER is not set +# CONFIG_JOYSTICK_TWIDJOY is not set +# CONFIG_JOYSTICK_ZHENHUA is not set +# CONFIG_JOYSTICK_AS5011 is not set +# CONFIG_JOYSTICK_JOYDUMP is not set +CONFIG_JOYSTICK_XPAD=y +CONFIG_JOYSTICK_XPAD_FF=y +CONFIG_JOYSTICK_XPAD_LEDS=y +# CONFIG_JOYSTICK_PSXPAD_SPI is not set +# CONFIG_JOYSTICK_PXRC is not set +# CONFIG_JOYSTICK_FSIA6B is not set +# CONFIG_INPUT_TABLET is not set +# CONFIG_INPUT_TOUCHSCREEN is not set +# CONFIG_INPUT_MISC is not set +# CONFIG_RMI4_CORE is not set + +# +# Hardware I/O ports +# +CONFIG_SERIO=y +# CONFIG_SERIO_SERPORT is not set +# CONFIG_SERIO_AMBAKMI is not set +# CONFIG_SERIO_PCIPS2 is not set +CONFIG_SERIO_LIBPS2=y +# CONFIG_SERIO_RAW is not set +# CONFIG_SERIO_ALTERA_PS2 is not set +# CONFIG_SERIO_PS2MULT is not set +# CONFIG_SERIO_ARC_PS2 is not set +# CONFIG_SERIO_APBPS2 is not set +# CONFIG_SERIO_GPIO_PS2 is not set +# CONFIG_USERIO is not set +# CONFIG_GAMEPORT is not set +# end of Hardware I/O ports +# end of Input device support + +# +# Character devices +# +CONFIG_TTY=y +CONFIG_VT=y +CONFIG_CONSOLE_TRANSLATIONS=y +CONFIG_VT_CONSOLE=y +CONFIG_VT_CONSOLE_SLEEP=y +CONFIG_HW_CONSOLE=y +CONFIG_VT_HW_CONSOLE_BINDING=y +CONFIG_UNIX98_PTYS=y +# CONFIG_LEGACY_PTYS is not set +CONFIG_LDISC_AUTOLOAD=y + +# +# Serial drivers +# +CONFIG_SERIAL_EARLYCON=y +# CONFIG_SERIAL_8250 is not set + +# +# Non-8250 serial port support +# +CONFIG_SERIAL_AMBA_PL010=y +CONFIG_SERIAL_AMBA_PL010_CONSOLE=y +CONFIG_SERIAL_AMBA_PL011=y +CONFIG_SERIAL_AMBA_PL011_CONSOLE=y +# CONFIG_SERIAL_EARLYCON_ARM_SEMIHOST is not set +# CONFIG_SERIAL_KGDB_NMI is not set +# CONFIG_SERIAL_MAX3100 is not set +# CONFIG_SERIAL_MAX310X is not set +CONFIG_SERIAL_IMX=y +CONFIG_SERIAL_IMX_CONSOLE=y +CONFIG_SERIAL_IMX_EARLYCON=y +# CONFIG_SERIAL_UARTLITE is not set +CONFIG_SERIAL_CORE=y +CONFIG_SERIAL_CORE_CONSOLE=y +CONFIG_CONSOLE_POLL=y +# CONFIG_SERIAL_JSM is not set +# CONFIG_SERIAL_SIFIVE is not set +# CONFIG_SERIAL_SCCNXP is not set +# CONFIG_SERIAL_SC16IS7XX is not set +# CONFIG_SERIAL_BCM63XX is not set +# CONFIG_SERIAL_ALTERA_JTAGUART is not set +# CONFIG_SERIAL_ALTERA_UART is not set +# CONFIG_SERIAL_IFX6X60 is not set +# CONFIG_SERIAL_XILINX_PS_UART is not set +# CONFIG_SERIAL_ARC is not set +# CONFIG_SERIAL_RP2 is not set +# CONFIG_SERIAL_FSL_LPUART is not set +# CONFIG_SERIAL_FSL_LINFLEXUART is not set +# CONFIG_SERIAL_CONEXANT_DIGICOLOR is not set +# CONFIG_SERIAL_SPRD is not set +# end of Serial drivers + +CONFIG_SERIAL_MCTRL_GPIO=y +# CONFIG_SERIAL_NONSTANDARD is not set +# CONFIG_N_GSM is not set +# CONFIG_NOZOMI is not set +# CONFIG_NULL_TTY is not set +# CONFIG_TRACE_SINK is not set +CONFIG_HVC_DRIVER=y +# CONFIG_HVC_XEN is not set +# CONFIG_HVC_DCC is not set +CONFIG_SERIAL_DEV_BUS=y +CONFIG_SERIAL_DEV_CTRL_TTYPORT=y +# CONFIG_TTY_PRINTK is not set +CONFIG_VIRTIO_CONSOLE=y +# CONFIG_IPMI_HANDLER is not set +# CONFIG_IPMB_DEVICE_INTERFACE is not set +CONFIG_HW_RANDOM=y +# CONFIG_HW_RANDOM_TIMERIOMEM is not set +# CONFIG_HW_RANDOM_BA431 is not set +CONFIG_HW_RANDOM_VIRTIO=y +# CONFIG_HW_RANDOM_CAVIUM is not set +# CONFIG_HW_RANDOM_CCTRNG is not set +# CONFIG_HW_RANDOM_XIPHERA is not set +# CONFIG_APPLICOM is not set +CONFIG_DEVMEM=y +# CONFIG_RAW_DRIVER is not set +CONFIG_DEVPORT=y +# CONFIG_TCG_TPM is not set +# CONFIG_XILLYBUS is not set +# end of Character devices + +CONFIG_RANDOM_TRUST_CPU=y +# CONFIG_RANDOM_TRUST_BOOTLOADER is not set + +# +# I2C support +# +CONFIG_I2C=y +CONFIG_I2C_BOARDINFO=y +CONFIG_I2C_COMPAT=y +CONFIG_I2C_CHARDEV=y +CONFIG_I2C_MUX=y + +# +# Multiplexer I2C Chip support +# +# CONFIG_I2C_ARB_GPIO_CHALLENGE is not set +# CONFIG_I2C_MUX_GPIO is not set +# CONFIG_I2C_MUX_GPMUX is not set +# CONFIG_I2C_MUX_LTC4306 is not set +# CONFIG_I2C_MUX_PCA9541 is not set +CONFIG_I2C_MUX_PCA954x=y +CONFIG_I2C_MUX_PINCTRL=y +CONFIG_I2C_MUX_REG=y +# CONFIG_I2C_DEMUX_PINCTRL is not set +# CONFIG_I2C_MUX_MLXCPLD is not set +# end of Multiplexer I2C Chip support + +CONFIG_I2C_HELPER_AUTO=y +CONFIG_I2C_ALGOBIT=y + +# +# I2C Hardware Bus support +# + +# +# PC SMBus host controller drivers +# +# CONFIG_I2C_ALI1535 is not set +# CONFIG_I2C_ALI1563 is not set +# CONFIG_I2C_ALI15X3 is not set +# CONFIG_I2C_AMD756 is not set +# CONFIG_I2C_AMD8111 is not set +# CONFIG_I2C_I801 is not set +# CONFIG_I2C_ISCH is not set +# CONFIG_I2C_PIIX4 is not set +# CONFIG_I2C_NFORCE2 is not set +# CONFIG_I2C_NVIDIA_GPU is not set +# CONFIG_I2C_SIS5595 is not set +# CONFIG_I2C_SIS630 is not set +# CONFIG_I2C_SIS96X is not set +# CONFIG_I2C_VIA is not set +# CONFIG_I2C_VIAPRO is not set + +# +# I2C system bus drivers (mostly embedded / system-on-chip) +# +# CONFIG_I2C_CADENCE is not set +# CONFIG_I2C_CBUS_GPIO is not set +# CONFIG_I2C_DESIGNWARE_PLATFORM is not set +# CONFIG_I2C_DESIGNWARE_PCI is not set +# CONFIG_I2C_EMEV2 is not set +# CONFIG_I2C_GPIO is not set +CONFIG_I2C_IMX=y +CONFIG_I2C_IMX_LPI2C=y +# CONFIG_I2C_NOMADIK is not set +# CONFIG_I2C_OCORES is not set +# CONFIG_I2C_PCA_PLATFORM is not set +# CONFIG_I2C_RK3X is not set +# CONFIG_I2C_SIMTEC is not set +# CONFIG_I2C_THUNDERX is not set +# CONFIG_I2C_XILINX is not set + +# +# External I2C/SMBus adapter drivers +# +# CONFIG_I2C_DIOLAN_U2C is not set +# CONFIG_I2C_ROBOTFUZZ_OSIF is not set +# CONFIG_I2C_TAOS_EVM is not set +# CONFIG_I2C_TINY_USB is not set + +# +# Other I2C/SMBus bus drivers +# +# end of I2C Hardware Bus support + +# CONFIG_I2C_STUB is not set +CONFIG_I2C_SLAVE=y +# CONFIG_I2C_SLAVE_EEPROM is not set +# CONFIG_I2C_SLAVE_TESTUNIT is not set +# CONFIG_I2C_DEBUG_CORE is not set +# CONFIG_I2C_DEBUG_ALGO is not set +# CONFIG_I2C_DEBUG_BUS is not set +# end of I2C support + +# CONFIG_I3C is not set +CONFIG_SPI=y +# CONFIG_SPI_DEBUG is not set +CONFIG_SPI_MASTER=y +CONFIG_SPI_MEM=y + +# +# SPI Master Controller Drivers +# +# CONFIG_SPI_ALTERA is not set +# CONFIG_SPI_AXI_SPI_ENGINE is not set +CONFIG_SPI_BITBANG=y +# CONFIG_SPI_CADENCE is not set +# CONFIG_SPI_CADENCE_QUADSPI is not set +# CONFIG_SPI_DESIGNWARE is not set +# CONFIG_SPI_FSL_LPSPI is not set +# CONFIG_SPI_FSL_QUADSPI is not set +# CONFIG_SPI_NXP_FLEXSPI is not set +# CONFIG_SPI_GPIO is not set +CONFIG_SPI_IMX=y +# CONFIG_SPI_FSL_SPI is not set +# CONFIG_SPI_OC_TINY is not set +# CONFIG_SPI_PL022 is not set +# CONFIG_SPI_PXA2XX is not set +# CONFIG_SPI_ROCKCHIP is not set +# CONFIG_SPI_SC18IS602 is not set +# CONFIG_SPI_SIFIVE is not set +# CONFIG_SPI_MXIC is not set +# CONFIG_SPI_THUNDERX is not set +# CONFIG_SPI_XCOMM is not set +# CONFIG_SPI_XILINX is not set +# CONFIG_SPI_ZYNQMP_GQSPI is not set +# CONFIG_SPI_AMD is not set + +# +# SPI Multiplexer support +# +# CONFIG_SPI_MUX is not set + +# +# SPI Protocol Masters +# +CONFIG_SPI_SPIDEV=y +# CONFIG_SPI_LOOPBACK_TEST is not set +# CONFIG_SPI_TLE62X0 is not set +# CONFIG_SPI_SLAVE is not set +# CONFIG_SPMI is not set +# CONFIG_HSI is not set +# CONFIG_PPS is not set + +# +# PTP clock support +# +# CONFIG_PTP_1588_CLOCK is not set + +# +# Enable PHYLIB and NETWORK_PHY_TIMESTAMPING to see the additional clocks. +# +# end of PTP clock support + +CONFIG_PINCTRL=y +CONFIG_GENERIC_PINCTRL_GROUPS=y +CONFIG_PINMUX=y +CONFIG_GENERIC_PINMUX_FUNCTIONS=y +CONFIG_PINCONF=y +CONFIG_GENERIC_PINCONF=y +# CONFIG_DEBUG_PINCTRL is not set +# CONFIG_PINCTRL_MCP23S08 is not set +# CONFIG_PINCTRL_SINGLE is not set +# CONFIG_PINCTRL_SX150X is not set +# CONFIG_PINCTRL_STMFX is not set +# CONFIG_PINCTRL_OCELOT is not set +# CONFIG_PINCTRL_MICROCHIP_SGPIO is not set +CONFIG_PINCTRL_IMX=y +# CONFIG_PINCTRL_IMX8MM is not set +# CONFIG_PINCTRL_IMX8MN is not set +# CONFIG_PINCTRL_IMX8MP is not set +CONFIG_PINCTRL_IMX8MQ=y + +# +# Renesas pinctrl drivers +# +# end of Renesas pinctrl drivers + +CONFIG_GPIOLIB=y +CONFIG_GPIOLIB_FASTPATH_LIMIT=512 +CONFIG_OF_GPIO=y +CONFIG_GPIOLIB_IRQCHIP=y +# CONFIG_DEBUG_GPIO is not set +CONFIG_GPIO_SYSFS=y +CONFIG_GPIO_CDEV=y +CONFIG_GPIO_CDEV_V1=y +CONFIG_GPIO_GENERIC=y + +# +# Memory mapped GPIO drivers +# +# CONFIG_GPIO_74XX_MMIO is not set +# CONFIG_GPIO_ALTERA is not set +# CONFIG_GPIO_CADENCE is not set +# CONFIG_GPIO_DWAPB is not set +# CONFIG_GPIO_FTGPIO010 is not set +# CONFIG_GPIO_GENERIC_PLATFORM is not set +# CONFIG_GPIO_GRGPIO is not set +# CONFIG_GPIO_HLWD is not set +# CONFIG_GPIO_LOGICVC is not set +# CONFIG_GPIO_MB86S7X is not set +CONFIG_GPIO_MXC=y +# CONFIG_GPIO_PL061 is not set +# CONFIG_GPIO_SAMA5D2_PIOBU is not set +# CONFIG_GPIO_SIFIVE is not set +# CONFIG_GPIO_SYSCON is not set +# CONFIG_GPIO_XGENE is not set +# CONFIG_GPIO_XILINX is not set +# CONFIG_GPIO_AMD_FCH is not set +# end of Memory mapped GPIO drivers + +# +# I2C GPIO expanders +# +# CONFIG_GPIO_ADP5588 is not set +# CONFIG_GPIO_ADNP is not set +# CONFIG_GPIO_GW_PLD is not set +# CONFIG_GPIO_MAX7300 is not set +# CONFIG_GPIO_MAX732X is not set +CONFIG_GPIO_PCA953X=y +CONFIG_GPIO_PCA953X_IRQ=y +# CONFIG_GPIO_PCA9570 is not set +# CONFIG_GPIO_PCF857X is not set +# CONFIG_GPIO_TPIC2810 is not set +# end of I2C GPIO expanders + +# +# MFD GPIO expanders +# +# end of MFD GPIO expanders + +# +# PCI GPIO expanders +# +# CONFIG_GPIO_BT8XX is not set +# CONFIG_GPIO_PCI_IDIO_16 is not set +# CONFIG_GPIO_PCIE_IDIO_24 is not set +# CONFIG_GPIO_RDC321X is not set +# end of PCI GPIO expanders + +# +# SPI GPIO expanders +# +# CONFIG_GPIO_74X164 is not set +# CONFIG_GPIO_MAX3191X is not set +# CONFIG_GPIO_MAX7301 is not set +# CONFIG_GPIO_MC33880 is not set +# CONFIG_GPIO_PISOSR is not set +# CONFIG_GPIO_XRA1403 is not set +# end of SPI GPIO expanders + +# +# USB GPIO expanders +# +# end of USB GPIO expanders + +# +# Virtual GPIO drivers +# +# CONFIG_GPIO_AGGREGATOR is not set +# CONFIG_GPIO_MOCKUP is not set +# end of Virtual GPIO drivers + +# CONFIG_W1 is not set +CONFIG_POWER_RESET=y +# CONFIG_POWER_RESET_BRCMSTB is not set +# CONFIG_POWER_RESET_GPIO is not set +# CONFIG_POWER_RESET_GPIO_RESTART is not set +# CONFIG_POWER_RESET_LTC2952 is not set +# CONFIG_POWER_RESET_REGULATOR is not set +# CONFIG_POWER_RESET_RESTART is not set +# CONFIG_POWER_RESET_XGENE is not set +CONFIG_POWER_RESET_SYSCON=y +CONFIG_POWER_RESET_SYSCON_POWEROFF=y +# CONFIG_SYSCON_REBOOT_MODE is not set +# CONFIG_NVMEM_REBOOT_MODE is not set +CONFIG_POWER_SUPPLY=y +# CONFIG_POWER_SUPPLY_DEBUG is not set +CONFIG_POWER_SUPPLY_HWMON=y +# CONFIG_PDA_POWER is not set +# CONFIG_TEST_POWER is not set +# CONFIG_CHARGER_ADP5061 is not set +# CONFIG_BATTERY_CW2015 is not set +# CONFIG_BATTERY_DS2780 is not set +# CONFIG_BATTERY_DS2781 is not set +# CONFIG_BATTERY_DS2782 is not set +# CONFIG_BATTERY_SBS is not set +# CONFIG_CHARGER_SBS is not set +# CONFIG_MANAGER_SBS is not set +# CONFIG_BATTERY_BQ27XXX is not set +# CONFIG_BATTERY_MAX17040 is not set +# CONFIG_BATTERY_MAX17042 is not set +# CONFIG_CHARGER_MAX8903 is not set +# CONFIG_CHARGER_LP8727 is not set +# CONFIG_CHARGER_GPIO is not set +# CONFIG_CHARGER_MANAGER is not set +# CONFIG_CHARGER_LT3651 is not set +# CONFIG_CHARGER_DETECTOR_MAX14656 is not set +# CONFIG_CHARGER_BQ2415X is not set +# CONFIG_CHARGER_BQ24257 is not set +# CONFIG_CHARGER_BQ24735 is not set +# CONFIG_CHARGER_BQ2515X is not set +# CONFIG_CHARGER_BQ25890 is not set +# CONFIG_CHARGER_BQ25980 is not set +# CONFIG_CHARGER_SMB347 is not set +# CONFIG_BATTERY_GAUGE_LTC2941 is not set +# CONFIG_CHARGER_RT9455 is not set +# CONFIG_CHARGER_UCS1002 is not set +# CONFIG_CHARGER_BD99954 is not set +CONFIG_HWMON=y +# CONFIG_HWMON_DEBUG_CHIP is not set + +# +# Native drivers +# +# CONFIG_SENSORS_AD7314 is not set +# CONFIG_SENSORS_AD7414 is not set +# CONFIG_SENSORS_AD7418 is not set +# CONFIG_SENSORS_ADM1021 is not set +# CONFIG_SENSORS_ADM1025 is not set +# CONFIG_SENSORS_ADM1026 is not set +# CONFIG_SENSORS_ADM1029 is not set +# CONFIG_SENSORS_ADM1031 is not set +# CONFIG_SENSORS_ADM1177 is not set +# CONFIG_SENSORS_ADM9240 is not set +# CONFIG_SENSORS_ADT7310 is not set +# CONFIG_SENSORS_ADT7410 is not set +# CONFIG_SENSORS_ADT7411 is not set +# CONFIG_SENSORS_ADT7462 is not set +# CONFIG_SENSORS_ADT7470 is not set +# CONFIG_SENSORS_ADT7475 is not set +# CONFIG_SENSORS_AS370 is not set +# CONFIG_SENSORS_ASC7621 is not set +# CONFIG_SENSORS_AXI_FAN_CONTROL is not set +# CONFIG_SENSORS_ASPEED is not set +# CONFIG_SENSORS_ATXP1 is not set +# CONFIG_SENSORS_CORSAIR_CPRO is not set +# CONFIG_SENSORS_CORSAIR_PSU is not set +# CONFIG_SENSORS_DS620 is not set +# CONFIG_SENSORS_DS1621 is not set +# CONFIG_SENSORS_I5K_AMB is not set +# CONFIG_SENSORS_F71805F is not set +# CONFIG_SENSORS_F71882FG is not set +# CONFIG_SENSORS_F75375S is not set +# CONFIG_SENSORS_FTSTEUTATES is not set +# CONFIG_SENSORS_GL518SM is not set +# CONFIG_SENSORS_GL520SM is not set +# CONFIG_SENSORS_G760A is not set +# CONFIG_SENSORS_G762 is not set +# CONFIG_SENSORS_GPIO_FAN is not set +# CONFIG_SENSORS_HIH6130 is not set +# CONFIG_SENSORS_IT87 is not set +# CONFIG_SENSORS_JC42 is not set +# CONFIG_SENSORS_POWR1220 is not set +# CONFIG_SENSORS_LINEAGE is not set +# CONFIG_SENSORS_LTC2945 is not set +# CONFIG_SENSORS_LTC2947_I2C is not set +# CONFIG_SENSORS_LTC2947_SPI is not set +# CONFIG_SENSORS_LTC2990 is not set +# CONFIG_SENSORS_LTC2992 is not set +# CONFIG_SENSORS_LTC4151 is not set +# CONFIG_SENSORS_LTC4215 is not set +# CONFIG_SENSORS_LTC4222 is not set +# CONFIG_SENSORS_LTC4245 is not set +# CONFIG_SENSORS_LTC4260 is not set +# CONFIG_SENSORS_LTC4261 is not set +# CONFIG_SENSORS_MAX1111 is not set +# CONFIG_SENSORS_MAX127 is not set +# CONFIG_SENSORS_MAX16065 is not set +# CONFIG_SENSORS_MAX1619 is not set +# CONFIG_SENSORS_MAX1668 is not set +# CONFIG_SENSORS_MAX197 is not set +# CONFIG_SENSORS_MAX31722 is not set +# CONFIG_SENSORS_MAX31730 is not set +# CONFIG_SENSORS_MAX6621 is not set +# CONFIG_SENSORS_MAX6639 is not set +# CONFIG_SENSORS_MAX6642 is not set +# CONFIG_SENSORS_MAX6650 is not set +# CONFIG_SENSORS_MAX6697 is not set +# CONFIG_SENSORS_MAX31790 is not set +# CONFIG_SENSORS_MCP3021 is not set +# CONFIG_SENSORS_TC654 is not set +# CONFIG_SENSORS_MR75203 is not set +# CONFIG_SENSORS_ADCXX is not set +# CONFIG_SENSORS_LM63 is not set +# CONFIG_SENSORS_LM70 is not set +# CONFIG_SENSORS_LM73 is not set +# CONFIG_SENSORS_LM75 is not set +# CONFIG_SENSORS_LM77 is not set +# CONFIG_SENSORS_LM78 is not set +# CONFIG_SENSORS_LM80 is not set +# CONFIG_SENSORS_LM83 is not set +# CONFIG_SENSORS_LM85 is not set +# CONFIG_SENSORS_LM87 is not set +# CONFIG_SENSORS_LM90 is not set +# CONFIG_SENSORS_LM92 is not set +# CONFIG_SENSORS_LM93 is not set +# CONFIG_SENSORS_LM95234 is not set +# CONFIG_SENSORS_LM95241 is not set +# CONFIG_SENSORS_LM95245 is not set +# CONFIG_SENSORS_PC87360 is not set +# CONFIG_SENSORS_PC87427 is not set +# CONFIG_SENSORS_NTC_THERMISTOR is not set +# CONFIG_SENSORS_NCT6683 is not set +# CONFIG_SENSORS_NCT6775 is not set +# CONFIG_SENSORS_NCT7802 is not set +# CONFIG_SENSORS_NCT7904 is not set +# CONFIG_SENSORS_NPCM7XX is not set +# CONFIG_SENSORS_OCC_P8_I2C is not set +# CONFIG_SENSORS_PCF8591 is not set +# CONFIG_PMBUS is not set +CONFIG_SENSORS_PWM_FAN=y +# CONFIG_SENSORS_SBTSI is not set +# CONFIG_SENSORS_SHT15 is not set +# CONFIG_SENSORS_SHT21 is not set +# CONFIG_SENSORS_SHT3x is not set +# CONFIG_SENSORS_SHTC1 is not set +# CONFIG_SENSORS_SIS5595 is not set +# CONFIG_SENSORS_DME1737 is not set +# CONFIG_SENSORS_EMC1403 is not set +# CONFIG_SENSORS_EMC2103 is not set +# CONFIG_SENSORS_EMC6W201 is not set +# CONFIG_SENSORS_SMSC47M1 is not set +# CONFIG_SENSORS_SMSC47M192 is not set +# CONFIG_SENSORS_SMSC47B397 is not set +# CONFIG_SENSORS_SCH5627 is not set +# CONFIG_SENSORS_SCH5636 is not set +# CONFIG_SENSORS_STTS751 is not set +# CONFIG_SENSORS_SMM665 is not set +# CONFIG_SENSORS_ADC128D818 is not set +# CONFIG_SENSORS_ADS7828 is not set +# CONFIG_SENSORS_ADS7871 is not set +# CONFIG_SENSORS_AMC6821 is not set +# CONFIG_SENSORS_INA209 is not set +# CONFIG_SENSORS_INA2XX is not set +# CONFIG_SENSORS_INA3221 is not set +# CONFIG_SENSORS_TC74 is not set +# CONFIG_SENSORS_THMC50 is not set +# CONFIG_SENSORS_TMP102 is not set +# CONFIG_SENSORS_TMP103 is not set +# CONFIG_SENSORS_TMP108 is not set +# CONFIG_SENSORS_TMP401 is not set +# CONFIG_SENSORS_TMP421 is not set +# CONFIG_SENSORS_TMP513 is not set +# CONFIG_SENSORS_VIA686A is not set +# CONFIG_SENSORS_VT1211 is not set +# CONFIG_SENSORS_VT8231 is not set +# CONFIG_SENSORS_W83773G is not set +# CONFIG_SENSORS_W83781D is not set +# CONFIG_SENSORS_W83791D is not set +# CONFIG_SENSORS_W83792D is not set +# CONFIG_SENSORS_W83793 is not set +# CONFIG_SENSORS_W83795 is not set +# CONFIG_SENSORS_W83L785TS is not set +# CONFIG_SENSORS_W83L786NG is not set +# CONFIG_SENSORS_W83627HF is not set +# CONFIG_SENSORS_W83627EHF is not set +CONFIG_THERMAL=y +# CONFIG_THERMAL_NETLINK is not set +CONFIG_THERMAL_STATISTICS=y +CONFIG_THERMAL_EMERGENCY_POWEROFF_DELAY_MS=0 +CONFIG_THERMAL_HWMON=y +CONFIG_THERMAL_OF=y +CONFIG_THERMAL_WRITABLE_TRIPS=y +CONFIG_THERMAL_DEFAULT_GOV_STEP_WISE=y +# CONFIG_THERMAL_DEFAULT_GOV_FAIR_SHARE is not set +# CONFIG_THERMAL_DEFAULT_GOV_USER_SPACE is not set +CONFIG_THERMAL_GOV_FAIR_SHARE=y +CONFIG_THERMAL_GOV_STEP_WISE=y +CONFIG_THERMAL_GOV_BANG_BANG=y +CONFIG_THERMAL_GOV_USER_SPACE=y +CONFIG_CPU_THERMAL=y +CONFIG_CPU_FREQ_THERMAL=y +CONFIG_CPU_IDLE_THERMAL=y +CONFIG_DEVFREQ_THERMAL=y +# CONFIG_THERMAL_EMULATION is not set +CONFIG_THERMAL_MMIO=y +CONFIG_IMX_THERMAL=y +# CONFIG_IMX8MM_THERMAL is not set +CONFIG_QORIQ_THERMAL=y +CONFIG_WATCHDOG=y +CONFIG_WATCHDOG_CORE=y +# CONFIG_WATCHDOG_NOWAYOUT is not set +CONFIG_WATCHDOG_HANDLE_BOOT_ENABLED=y +CONFIG_WATCHDOG_OPEN_TIMEOUT=0 +CONFIG_WATCHDOG_SYSFS=y + +# +# Watchdog Pretimeout Governors +# +# CONFIG_WATCHDOG_PRETIMEOUT_GOV is not set + +# +# Watchdog Device Drivers +# +# CONFIG_SOFT_WATCHDOG is not set +# CONFIG_GPIO_WATCHDOG is not set +# CONFIG_XILINX_WATCHDOG is not set +# CONFIG_ZIIRAVE_WATCHDOG is not set +# CONFIG_ARM_SP805_WATCHDOG is not set +# CONFIG_ARM_SBSA_WATCHDOG is not set +# CONFIG_CADENCE_WATCHDOG is not set +# CONFIG_DW_WATCHDOG is not set +# CONFIG_MAX63XX_WATCHDOG is not set +CONFIG_IMX2_WDT=y +# CONFIG_IMX7ULP_WDT is not set +# CONFIG_ARM_SMC_WATCHDOG is not set +# CONFIG_ALIM7101_WDT is not set +# CONFIG_I6300ESB_WDT is not set +# CONFIG_MEN_A21_WDT is not set +# CONFIG_XEN_WDT is not set + +# +# PCI-based Watchdog Cards +# +# CONFIG_PCIPCWATCHDOG is not set +# CONFIG_WDTPCI is not set + +# +# USB-based Watchdog Cards +# +# CONFIG_USBPCWATCHDOG is not set +CONFIG_SSB_POSSIBLE=y +CONFIG_SSB=y +CONFIG_SSB_SPROM=y +CONFIG_SSB_PCIHOST_POSSIBLE=y +CONFIG_SSB_PCIHOST=y +CONFIG_SSB_SDIOHOST_POSSIBLE=y +# CONFIG_SSB_SDIOHOST is not set +CONFIG_SSB_DRIVER_PCICORE_POSSIBLE=y +CONFIG_SSB_DRIVER_PCICORE=y +# CONFIG_SSB_DRIVER_GPIO is not set +CONFIG_BCMA_POSSIBLE=y +CONFIG_BCMA=y +CONFIG_BCMA_HOST_PCI_POSSIBLE=y +# CONFIG_BCMA_HOST_PCI is not set +# CONFIG_BCMA_HOST_SOC is not set +# CONFIG_BCMA_DRIVER_PCI is not set +# CONFIG_BCMA_DRIVER_GMAC_CMN is not set +# CONFIG_BCMA_DRIVER_GPIO is not set +# CONFIG_BCMA_DEBUG is not set + +# +# Multifunction device drivers +# +# CONFIG_MFD_ACT8945A is not set +# CONFIG_MFD_AS3711 is not set +# CONFIG_MFD_AS3722 is not set +# CONFIG_PMIC_ADP5520 is not set +# CONFIG_MFD_AAT2870_CORE is not set +# CONFIG_MFD_ATMEL_FLEXCOM is not set +# CONFIG_MFD_ATMEL_HLCDC is not set +# CONFIG_MFD_BCM590XX is not set +# CONFIG_MFD_BD9571MWV is not set +# CONFIG_MFD_AXP20X_I2C is not set +# CONFIG_MFD_MADERA is not set +# CONFIG_PMIC_DA903X is not set +# CONFIG_MFD_DA9052_SPI is not set +# CONFIG_MFD_DA9052_I2C is not set +# CONFIG_MFD_DA9055 is not set +# CONFIG_MFD_DA9062 is not set +# CONFIG_MFD_DA9063 is not set +# CONFIG_MFD_DA9150 is not set +# CONFIG_MFD_DLN2 is not set +# CONFIG_MFD_GATEWORKS_GSC is not set +# CONFIG_MFD_MC13XXX_SPI is not set +# CONFIG_MFD_MC13XXX_I2C is not set +# CONFIG_MFD_MP2629 is not set +# CONFIG_MFD_HI6421_PMIC is not set +# CONFIG_HTC_PASIC3 is not set +# CONFIG_HTC_I2CPLD is not set +# CONFIG_LPC_ICH is not set +# CONFIG_LPC_SCH is not set +# CONFIG_MFD_INTEL_PMT is not set +# CONFIG_MFD_IQS62X is not set +# CONFIG_MFD_JANZ_CMODIO is not set +# CONFIG_MFD_KEMPLD is not set +# CONFIG_MFD_88PM800 is not set +# CONFIG_MFD_88PM805 is not set +# CONFIG_MFD_88PM860X is not set +# CONFIG_MFD_MAX14577 is not set +# CONFIG_MFD_MAX77620 is not set +# CONFIG_MFD_MAX77650 is not set +# CONFIG_MFD_MAX77686 is not set +# CONFIG_MFD_MAX77693 is not set +# CONFIG_MFD_MAX77843 is not set +# CONFIG_MFD_MAX8907 is not set +# CONFIG_MFD_MAX8925 is not set +# CONFIG_MFD_MAX8997 is not set +# CONFIG_MFD_MAX8998 is not set +# CONFIG_MFD_MT6360 is not set +# CONFIG_MFD_MT6397 is not set +# CONFIG_MFD_MENF21BMC is not set +# CONFIG_EZX_PCAP is not set +# CONFIG_MFD_CPCAP is not set +# CONFIG_MFD_VIPERBOARD is not set +# CONFIG_MFD_RETU is not set +# CONFIG_MFD_PCF50633 is not set +# CONFIG_UCB1400_CORE is not set +# CONFIG_MFD_RDC321X is not set +# CONFIG_MFD_RT5033 is not set +# CONFIG_MFD_RC5T583 is not set +# CONFIG_MFD_RK808 is not set +# CONFIG_MFD_RN5T618 is not set +# CONFIG_MFD_SEC_CORE is not set +# CONFIG_MFD_SI476X_CORE is not set +# CONFIG_MFD_SM501 is not set +# CONFIG_MFD_SKY81452 is not set +# CONFIG_ABX500_CORE is not set +# CONFIG_MFD_STMPE is not set +CONFIG_MFD_SYSCON=y +# CONFIG_MFD_TI_AM335X_TSCADC is not set +# CONFIG_MFD_LP3943 is not set +# CONFIG_MFD_LP8788 is not set +# CONFIG_MFD_TI_LMU is not set +# CONFIG_MFD_PALMAS is not set +# CONFIG_TPS6105X is not set +# CONFIG_TPS65010 is not set +# CONFIG_TPS6507X is not set +# CONFIG_MFD_TPS65086 is not set +# CONFIG_MFD_TPS65090 is not set +# CONFIG_MFD_TPS65217 is not set +# CONFIG_MFD_TI_LP873X is not set +# CONFIG_MFD_TI_LP87565 is not set +# CONFIG_MFD_TPS65218 is not set +# CONFIG_MFD_TPS6586X is not set +# CONFIG_MFD_TPS65910 is not set +# CONFIG_MFD_TPS65912_I2C is not set +# CONFIG_MFD_TPS65912_SPI is not set +# CONFIG_MFD_TPS80031 is not set +# CONFIG_TWL4030_CORE is not set +# CONFIG_TWL6040_CORE is not set +# CONFIG_MFD_WL1273_CORE is not set +# CONFIG_MFD_LM3533 is not set +# CONFIG_MFD_TC3589X is not set +# CONFIG_MFD_TQMX86 is not set +# CONFIG_MFD_VX855 is not set +# CONFIG_MFD_LOCHNAGAR is not set +# CONFIG_MFD_ARIZONA_I2C is not set +# CONFIG_MFD_ARIZONA_SPI is not set +# CONFIG_MFD_WM8400 is not set +# CONFIG_MFD_WM831X_I2C is not set +# CONFIG_MFD_WM831X_SPI is not set +# CONFIG_MFD_WM8350_I2C is not set +# CONFIG_MFD_WM8994 is not set +# CONFIG_MFD_ROHM_BD718XX is not set +# CONFIG_MFD_ROHM_BD70528 is not set +# CONFIG_MFD_ROHM_BD71828 is not set +# CONFIG_MFD_STPMIC1 is not set +# CONFIG_MFD_STMFX is not set +# CONFIG_RAVE_SP_CORE is not set +# CONFIG_MFD_INTEL_M10_BMC is not set +# end of Multifunction device drivers + +CONFIG_REGULATOR=y +CONFIG_REGULATOR_DEBUG=y +CONFIG_REGULATOR_FIXED_VOLTAGE=y +CONFIG_REGULATOR_VIRTUAL_CONSUMER=y +CONFIG_REGULATOR_USERSPACE_CONSUMER=y +# CONFIG_REGULATOR_88PG86X is not set +# CONFIG_REGULATOR_ACT8865 is not set +# CONFIG_REGULATOR_AD5398 is not set +CONFIG_REGULATOR_ANATOP=y +# CONFIG_REGULATOR_DA9121 is not set +# CONFIG_REGULATOR_DA9210 is not set +# CONFIG_REGULATOR_DA9211 is not set +CONFIG_REGULATOR_FAN53555=y +# CONFIG_REGULATOR_FAN53880 is not set +CONFIG_REGULATOR_GPIO=y +# CONFIG_REGULATOR_ISL9305 is not set +# CONFIG_REGULATOR_ISL6271A is not set +# CONFIG_REGULATOR_LP3971 is not set +# CONFIG_REGULATOR_LP3972 is not set +# CONFIG_REGULATOR_LP872X is not set +# CONFIG_REGULATOR_LP8755 is not set +# CONFIG_REGULATOR_LTC3589 is not set +# CONFIG_REGULATOR_LTC3676 is not set +# CONFIG_REGULATOR_MAX1586 is not set +# CONFIG_REGULATOR_MAX8649 is not set +# CONFIG_REGULATOR_MAX8660 is not set +# CONFIG_REGULATOR_MAX8952 is not set +# CONFIG_REGULATOR_MAX8973 is not set +# CONFIG_REGULATOR_MAX77826 is not set +# CONFIG_REGULATOR_MCP16502 is not set +# CONFIG_REGULATOR_MP5416 is not set +# CONFIG_REGULATOR_MP8859 is not set +# CONFIG_REGULATOR_MP886X is not set +# CONFIG_REGULATOR_MPQ7920 is not set +# CONFIG_REGULATOR_MT6311 is not set +# CONFIG_REGULATOR_PCA9450 is not set +# CONFIG_REGULATOR_PF8X00 is not set +CONFIG_REGULATOR_PFUZE100=y +# CONFIG_REGULATOR_PV88060 is not set +# CONFIG_REGULATOR_PV88080 is not set +# CONFIG_REGULATOR_PV88090 is not set +CONFIG_REGULATOR_PWM=y +# CONFIG_REGULATOR_RASPBERRYPI_TOUCHSCREEN_ATTINY is not set +# CONFIG_REGULATOR_RT4801 is not set +# CONFIG_REGULATOR_RTMV20 is not set +# CONFIG_REGULATOR_SLG51000 is not set +# CONFIG_REGULATOR_SY8106A is not set +# CONFIG_REGULATOR_SY8824X is not set +# CONFIG_REGULATOR_SY8827N is not set +# CONFIG_REGULATOR_TPS51632 is not set +# CONFIG_REGULATOR_TPS62360 is not set +# CONFIG_REGULATOR_TPS65023 is not set +# CONFIG_REGULATOR_TPS6507X is not set +# CONFIG_REGULATOR_TPS65132 is not set +# CONFIG_REGULATOR_TPS6524X is not set +CONFIG_REGULATOR_VCTRL=y +# CONFIG_RC_CORE is not set +CONFIG_CEC_CORE=y +CONFIG_CEC_NOTIFIER=y +CONFIG_MEDIA_CEC_SUPPORT=y +# CONFIG_CEC_CH7322 is not set +# CONFIG_CEC_GPIO is not set +# CONFIG_USB_PULSE8_CEC is not set +# CONFIG_USB_RAINSHADOW_CEC is not set +CONFIG_MEDIA_SUPPORT=y +# CONFIG_MEDIA_SUPPORT_FILTER is not set +CONFIG_MEDIA_SUBDRV_AUTOSELECT=y + +# +# Media device types +# +CONFIG_MEDIA_CAMERA_SUPPORT=y +CONFIG_MEDIA_ANALOG_TV_SUPPORT=y +CONFIG_MEDIA_DIGITAL_TV_SUPPORT=y +CONFIG_MEDIA_RADIO_SUPPORT=y +CONFIG_MEDIA_SDR_SUPPORT=y +CONFIG_MEDIA_PLATFORM_SUPPORT=y +CONFIG_MEDIA_TEST_SUPPORT=y +# end of Media device types + +# +# Media core support +# +CONFIG_VIDEO_DEV=y +CONFIG_MEDIA_CONTROLLER=y +CONFIG_DVB_CORE=y +# end of Media core support + +# +# Video4Linux options +# +CONFIG_VIDEO_V4L2=y +CONFIG_VIDEO_V4L2_I2C=y +CONFIG_VIDEO_V4L2_SUBDEV_API=y +# CONFIG_VIDEO_ADV_DEBUG is not set +# CONFIG_VIDEO_FIXED_MINOR_RANGES is not set +CONFIG_V4L2_H264=y +CONFIG_V4L2_MEM2MEM_DEV=y +# end of Video4Linux options + +# +# Media controller options +# +# CONFIG_MEDIA_CONTROLLER_DVB is not set +CONFIG_MEDIA_CONTROLLER_REQUEST_API=y + +# +# Please notice that the enabled Media controller Request API is EXPERIMENTAL +# +# end of Media controller options + +# +# Digital TV options +# +# CONFIG_DVB_MMAP is not set +CONFIG_DVB_NET=y +CONFIG_DVB_MAX_ADAPTERS=16 +CONFIG_DVB_DYNAMIC_MINORS=y +# CONFIG_DVB_DEMUX_SECTION_LOSS_LOG is not set +# CONFIG_DVB_ULE_DEBUG is not set +# end of Digital TV options + +# +# Media drivers +# +CONFIG_MEDIA_USB_SUPPORT=y + +# +# Webcam devices +# +CONFIG_USB_VIDEO_CLASS=y +CONFIG_USB_VIDEO_CLASS_INPUT_EVDEV=y +CONFIG_USB_GSPCA=y +# CONFIG_USB_M5602 is not set +# CONFIG_USB_STV06XX is not set +# CONFIG_USB_GL860 is not set +# CONFIG_USB_GSPCA_BENQ is not set +# CONFIG_USB_GSPCA_CONEX is not set +# CONFIG_USB_GSPCA_CPIA1 is not set +# CONFIG_USB_GSPCA_DTCS033 is not set +# CONFIG_USB_GSPCA_ETOMS is not set +# CONFIG_USB_GSPCA_FINEPIX is not set +# CONFIG_USB_GSPCA_JEILINJ is not set +# CONFIG_USB_GSPCA_JL2005BCD is not set +# CONFIG_USB_GSPCA_KINECT is not set +# CONFIG_USB_GSPCA_KONICA is not set +# CONFIG_USB_GSPCA_MARS is not set +# CONFIG_USB_GSPCA_MR97310A is not set +# CONFIG_USB_GSPCA_NW80X is not set +# CONFIG_USB_GSPCA_OV519 is not set +# CONFIG_USB_GSPCA_OV534 is not set +# CONFIG_USB_GSPCA_OV534_9 is not set +# CONFIG_USB_GSPCA_PAC207 is not set +# CONFIG_USB_GSPCA_PAC7302 is not set +# CONFIG_USB_GSPCA_PAC7311 is not set +# CONFIG_USB_GSPCA_SE401 is not set +# CONFIG_USB_GSPCA_SN9C2028 is not set +# CONFIG_USB_GSPCA_SN9C20X is not set +# CONFIG_USB_GSPCA_SONIXB is not set +# CONFIG_USB_GSPCA_SONIXJ is not set +# CONFIG_USB_GSPCA_SPCA500 is not set +# CONFIG_USB_GSPCA_SPCA501 is not set +# CONFIG_USB_GSPCA_SPCA505 is not set +# CONFIG_USB_GSPCA_SPCA506 is not set +# CONFIG_USB_GSPCA_SPCA508 is not set +# CONFIG_USB_GSPCA_SPCA561 is not set +# CONFIG_USB_GSPCA_SPCA1528 is not set +# CONFIG_USB_GSPCA_SQ905 is not set +# CONFIG_USB_GSPCA_SQ905C is not set +# CONFIG_USB_GSPCA_SQ930X is not set +# CONFIG_USB_GSPCA_STK014 is not set +CONFIG_USB_GSPCA_STK1135=y +# CONFIG_USB_GSPCA_STV0680 is not set +# CONFIG_USB_GSPCA_SUNPLUS is not set +# CONFIG_USB_GSPCA_T613 is not set +# CONFIG_USB_GSPCA_TOPRO is not set +# CONFIG_USB_GSPCA_TOUPTEK is not set +# CONFIG_USB_GSPCA_TV8532 is not set +# CONFIG_USB_GSPCA_VC032X is not set +# CONFIG_USB_GSPCA_VICAM is not set +# CONFIG_USB_GSPCA_XIRLINK_CIT is not set +# CONFIG_USB_GSPCA_ZC3XX is not set +# CONFIG_USB_PWC is not set +# CONFIG_VIDEO_CPIA2 is not set +# CONFIG_USB_ZR364XX is not set +# CONFIG_USB_STKWEBCAM is not set +# CONFIG_USB_S2255 is not set +# CONFIG_VIDEO_USBTV is not set + +# +# Analog TV USB devices +# +# CONFIG_VIDEO_PVRUSB2 is not set +# CONFIG_VIDEO_HDPVR is not set +# CONFIG_VIDEO_STK1160_COMMON is not set +# CONFIG_VIDEO_GO7007 is not set + +# +# Analog/digital TV USB devices +# +# CONFIG_VIDEO_AU0828 is not set +# CONFIG_VIDEO_CX231XX is not set + +# +# Digital TV USB devices +# +# CONFIG_DVB_USB_V2 is not set +# CONFIG_DVB_TTUSB_BUDGET is not set +# CONFIG_DVB_TTUSB_DEC is not set +# CONFIG_SMS_USB_DRV is not set +# CONFIG_DVB_B2C2_FLEXCOP_USB is not set +# CONFIG_DVB_AS102 is not set + +# +# Webcam, TV (analog/digital) USB devices +# +# CONFIG_VIDEO_EM28XX is not set + +# +# Software defined radio USB devices +# +# CONFIG_USB_AIRSPY is not set +# CONFIG_USB_HACKRF is not set +# CONFIG_USB_MSI2500 is not set +# CONFIG_MEDIA_PCI_SUPPORT is not set +CONFIG_RADIO_ADAPTERS=y +# CONFIG_RADIO_SI470X is not set +# CONFIG_RADIO_SI4713 is not set +# CONFIG_USB_MR800 is not set +# CONFIG_USB_DSBR is not set +# CONFIG_RADIO_MAXIRADIO is not set +# CONFIG_RADIO_SHARK is not set +# CONFIG_RADIO_SHARK2 is not set +# CONFIG_USB_KEENE is not set +# CONFIG_USB_RAREMONO is not set +# CONFIG_USB_MA901 is not set +# CONFIG_RADIO_TEA5764 is not set +# CONFIG_RADIO_SAA7706H is not set +# CONFIG_RADIO_TEF6862 is not set +# CONFIG_RADIO_WL1273 is not set +CONFIG_VIDEOBUF2_CORE=y +CONFIG_VIDEOBUF2_V4L2=y +CONFIG_VIDEOBUF2_MEMOPS=y +CONFIG_VIDEOBUF2_DMA_CONTIG=y +CONFIG_VIDEOBUF2_VMALLOC=y +# CONFIG_V4L_PLATFORM_DRIVERS is not set +CONFIG_V4L_MEM2MEM_DRIVERS=y +# CONFIG_VIDEO_CODA is not set +# CONFIG_VIDEO_IMX_PXP is not set +# CONFIG_VIDEO_MEM2MEM_DEINTERLACE is not set +# CONFIG_DVB_PLATFORM_DRIVERS is not set +# CONFIG_SDR_PLATFORM_DRIVERS is not set + +# +# MMC/SDIO DVB adapters +# +# CONFIG_SMS_SDIO_DRV is not set +# CONFIG_V4L_TEST_DRIVERS is not set +# CONFIG_DVB_TEST_DRIVERS is not set +# end of Media drivers + +# +# Media ancillary drivers +# +CONFIG_MEDIA_ATTACH=y + +# +# Audio decoders, processors and mixers +# +# CONFIG_VIDEO_TVAUDIO is not set +# CONFIG_VIDEO_TDA7432 is not set +# CONFIG_VIDEO_TDA9840 is not set +# CONFIG_VIDEO_TDA1997X is not set +# CONFIG_VIDEO_TEA6415C is not set +# CONFIG_VIDEO_TEA6420 is not set +# CONFIG_VIDEO_MSP3400 is not set +# CONFIG_VIDEO_CS3308 is not set +# CONFIG_VIDEO_CS5345 is not set +# CONFIG_VIDEO_CS53L32A is not set +# CONFIG_VIDEO_TLV320AIC23B is not set +# CONFIG_VIDEO_UDA1342 is not set +# CONFIG_VIDEO_WM8775 is not set +# CONFIG_VIDEO_WM8739 is not set +# CONFIG_VIDEO_VP27SMPX is not set +# CONFIG_VIDEO_SONY_BTF_MPX is not set +# end of Audio decoders, processors and mixers + +# +# RDS decoders +# +# CONFIG_VIDEO_SAA6588 is not set +# end of RDS decoders + +# +# Video decoders +# +# CONFIG_VIDEO_ADV7180 is not set +# CONFIG_VIDEO_ADV7183 is not set +# CONFIG_VIDEO_ADV748X is not set +# CONFIG_VIDEO_ADV7604 is not set +# CONFIG_VIDEO_ADV7842 is not set +# CONFIG_VIDEO_BT819 is not set +# CONFIG_VIDEO_BT856 is not set +# CONFIG_VIDEO_BT866 is not set +# CONFIG_VIDEO_KS0127 is not set +# CONFIG_VIDEO_ML86V7667 is not set +# CONFIG_VIDEO_SAA7110 is not set +# CONFIG_VIDEO_SAA711X is not set +# CONFIG_VIDEO_TC358743 is not set +# CONFIG_VIDEO_TVP514X is not set +# CONFIG_VIDEO_TVP5150 is not set +# CONFIG_VIDEO_TVP7002 is not set +# CONFIG_VIDEO_TW2804 is not set +# CONFIG_VIDEO_TW9903 is not set +# CONFIG_VIDEO_TW9906 is not set +# CONFIG_VIDEO_TW9910 is not set +# CONFIG_VIDEO_VPX3220 is not set +# CONFIG_VIDEO_MAX9286 is not set + +# +# Video and audio decoders +# +# CONFIG_VIDEO_SAA717X is not set +# CONFIG_VIDEO_CX25840 is not set +# end of Video decoders + +# +# Video encoders +# +# CONFIG_VIDEO_SAA7127 is not set +# CONFIG_VIDEO_SAA7185 is not set +# CONFIG_VIDEO_ADV7170 is not set +# CONFIG_VIDEO_ADV7175 is not set +# CONFIG_VIDEO_ADV7343 is not set +# CONFIG_VIDEO_ADV7393 is not set +# CONFIG_VIDEO_ADV7511 is not set +# CONFIG_VIDEO_AD9389B is not set +# CONFIG_VIDEO_AK881X is not set +# CONFIG_VIDEO_THS8200 is not set +# end of Video encoders + +# +# Video improvement chips +# +# CONFIG_VIDEO_UPD64031A is not set +# CONFIG_VIDEO_UPD64083 is not set +# end of Video improvement chips + +# +# Audio/Video compression chips +# +# CONFIG_VIDEO_SAA6752HS is not set +# end of Audio/Video compression chips + +# +# SDR tuner chips +# +# CONFIG_SDR_MAX2175 is not set +# end of SDR tuner chips + +# +# Miscellaneous helper chips +# +# CONFIG_VIDEO_THS7303 is not set +# CONFIG_VIDEO_M52790 is not set +# CONFIG_VIDEO_I2C is not set +# CONFIG_VIDEO_ST_MIPID02 is not set +# end of Miscellaneous helper chips + +# +# Camera sensor devices +# +# CONFIG_VIDEO_HI556 is not set +# CONFIG_VIDEO_IMX214 is not set +# CONFIG_VIDEO_IMX219 is not set +# CONFIG_VIDEO_IMX258 is not set +# CONFIG_VIDEO_IMX274 is not set +# CONFIG_VIDEO_IMX290 is not set +# CONFIG_VIDEO_IMX319 is not set +# CONFIG_VIDEO_IMX355 is not set +# CONFIG_VIDEO_OV02A10 is not set +# CONFIG_VIDEO_OV2640 is not set +# CONFIG_VIDEO_OV2659 is not set +# CONFIG_VIDEO_OV2680 is not set +# CONFIG_VIDEO_OV2685 is not set +# CONFIG_VIDEO_OV5640 is not set +# CONFIG_VIDEO_OV5645 is not set +# CONFIG_VIDEO_OV5647 is not set +# CONFIG_VIDEO_OV6650 is not set +# CONFIG_VIDEO_OV5670 is not set +# CONFIG_VIDEO_OV5675 is not set +# CONFIG_VIDEO_OV5695 is not set +# CONFIG_VIDEO_OV7251 is not set +# CONFIG_VIDEO_OV772X is not set +# CONFIG_VIDEO_OV7640 is not set +# CONFIG_VIDEO_OV7670 is not set +# CONFIG_VIDEO_OV7740 is not set +# CONFIG_VIDEO_OV8856 is not set +# CONFIG_VIDEO_OV9640 is not set +# CONFIG_VIDEO_OV9650 is not set +# CONFIG_VIDEO_OV13858 is not set +# CONFIG_VIDEO_VS6624 is not set +# CONFIG_VIDEO_MT9M001 is not set +# CONFIG_VIDEO_MT9M032 is not set +# CONFIG_VIDEO_MT9M111 is not set +# CONFIG_VIDEO_MT9P031 is not set +# CONFIG_VIDEO_MT9T001 is not set +# CONFIG_VIDEO_MT9T112 is not set +# CONFIG_VIDEO_MT9V011 is not set +# CONFIG_VIDEO_MT9V032 is not set +# CONFIG_VIDEO_MT9V111 is not set +# CONFIG_VIDEO_SR030PC30 is not set +# CONFIG_VIDEO_NOON010PC30 is not set +# CONFIG_VIDEO_M5MOLS is not set +# CONFIG_VIDEO_RDACM20 is not set +# CONFIG_VIDEO_RJ54N1 is not set +# CONFIG_VIDEO_S5K6AA is not set +# CONFIG_VIDEO_S5K6A3 is not set +# CONFIG_VIDEO_S5K4ECGX is not set +# CONFIG_VIDEO_S5K5BAF is not set +# CONFIG_VIDEO_CCS is not set +# CONFIG_VIDEO_ET8EK8 is not set +# CONFIG_VIDEO_S5C73M3 is not set +# end of Camera sensor devices + +# +# Lens drivers +# +# CONFIG_VIDEO_AD5820 is not set +# CONFIG_VIDEO_AK7375 is not set +# CONFIG_VIDEO_DW9714 is not set +# CONFIG_VIDEO_DW9768 is not set +# CONFIG_VIDEO_DW9807_VCM is not set +# end of Lens drivers + +# +# Flash devices +# +# CONFIG_VIDEO_ADP1653 is not set +# CONFIG_VIDEO_LM3560 is not set +# CONFIG_VIDEO_LM3646 is not set +# end of Flash devices + +# +# SPI helper chips +# +# CONFIG_VIDEO_GS1662 is not set +# end of SPI helper chips + +# +# Media SPI Adapters +# +# CONFIG_CXD2880_SPI_DRV is not set +# end of Media SPI Adapters + +CONFIG_MEDIA_TUNER=y + +# +# Customize TV tuners +# +CONFIG_MEDIA_TUNER_SIMPLE=y +# CONFIG_MEDIA_TUNER_TDA18250 is not set +CONFIG_MEDIA_TUNER_TDA8290=y +CONFIG_MEDIA_TUNER_TDA827X=y +CONFIG_MEDIA_TUNER_TDA18271=y +CONFIG_MEDIA_TUNER_TDA9887=y +CONFIG_MEDIA_TUNER_TEA5761=y +CONFIG_MEDIA_TUNER_TEA5767=y +# CONFIG_MEDIA_TUNER_MSI001 is not set +CONFIG_MEDIA_TUNER_MT20XX=y +# CONFIG_MEDIA_TUNER_MT2060 is not set +# CONFIG_MEDIA_TUNER_MT2063 is not set +# CONFIG_MEDIA_TUNER_MT2266 is not set +# CONFIG_MEDIA_TUNER_MT2131 is not set +# CONFIG_MEDIA_TUNER_QT1010 is not set +CONFIG_MEDIA_TUNER_XC2028=y +CONFIG_MEDIA_TUNER_XC5000=y +CONFIG_MEDIA_TUNER_XC4000=y +# CONFIG_MEDIA_TUNER_MXL5005S is not set +# CONFIG_MEDIA_TUNER_MXL5007T is not set +CONFIG_MEDIA_TUNER_MC44S803=y +# CONFIG_MEDIA_TUNER_MAX2165 is not set +# CONFIG_MEDIA_TUNER_TDA18218 is not set +# CONFIG_MEDIA_TUNER_FC0011 is not set +# CONFIG_MEDIA_TUNER_FC0012 is not set +# CONFIG_MEDIA_TUNER_FC0013 is not set +# CONFIG_MEDIA_TUNER_TDA18212 is not set +# CONFIG_MEDIA_TUNER_E4000 is not set +# CONFIG_MEDIA_TUNER_FC2580 is not set +# CONFIG_MEDIA_TUNER_M88RS6000T is not set +# CONFIG_MEDIA_TUNER_TUA9001 is not set +# CONFIG_MEDIA_TUNER_SI2157 is not set +# CONFIG_MEDIA_TUNER_IT913X is not set +# CONFIG_MEDIA_TUNER_R820T is not set +# CONFIG_MEDIA_TUNER_MXL301RF is not set +# CONFIG_MEDIA_TUNER_QM1D1C0042 is not set +# CONFIG_MEDIA_TUNER_QM1D1B0004 is not set +# end of Customize TV tuners + +# +# Customise DVB Frontends +# + +# +# Multistandard (satellite) frontends +# +# CONFIG_DVB_STB0899 is not set +# CONFIG_DVB_STB6100 is not set +# CONFIG_DVB_STV090x is not set +# CONFIG_DVB_STV0910 is not set +# CONFIG_DVB_STV6110x is not set +# CONFIG_DVB_STV6111 is not set +# CONFIG_DVB_MXL5XX is not set +# CONFIG_DVB_M88DS3103 is not set + +# +# Multistandard (cable + terrestrial) frontends +# +# CONFIG_DVB_DRXK is not set +# CONFIG_DVB_TDA18271C2DD is not set +# CONFIG_DVB_SI2165 is not set +# CONFIG_DVB_MN88472 is not set +# CONFIG_DVB_MN88473 is not set + +# +# DVB-S (satellite) frontends +# +# CONFIG_DVB_CX24110 is not set +# CONFIG_DVB_CX24123 is not set +# CONFIG_DVB_MT312 is not set +# CONFIG_DVB_ZL10036 is not set +# CONFIG_DVB_ZL10039 is not set +# CONFIG_DVB_S5H1420 is not set +# CONFIG_DVB_STV0288 is not set +# CONFIG_DVB_STB6000 is not set +# CONFIG_DVB_STV0299 is not set +# CONFIG_DVB_STV6110 is not set +# CONFIG_DVB_STV0900 is not set +# CONFIG_DVB_TDA8083 is not set +# CONFIG_DVB_TDA10086 is not set +# CONFIG_DVB_TDA8261 is not set +# CONFIG_DVB_VES1X93 is not set +# CONFIG_DVB_TUNER_ITD1000 is not set +# CONFIG_DVB_TUNER_CX24113 is not set +# CONFIG_DVB_TDA826X is not set +# CONFIG_DVB_TUA6100 is not set +# CONFIG_DVB_CX24116 is not set +# CONFIG_DVB_CX24117 is not set +# CONFIG_DVB_CX24120 is not set +# CONFIG_DVB_SI21XX is not set +# CONFIG_DVB_TS2020 is not set +# CONFIG_DVB_DS3000 is not set +# CONFIG_DVB_MB86A16 is not set +# CONFIG_DVB_TDA10071 is not set + +# +# DVB-T (terrestrial) frontends +# +# CONFIG_DVB_SP8870 is not set +# CONFIG_DVB_SP887X is not set +# CONFIG_DVB_CX22700 is not set +# CONFIG_DVB_CX22702 is not set +# CONFIG_DVB_S5H1432 is not set +# CONFIG_DVB_DRXD is not set +# CONFIG_DVB_L64781 is not set +# CONFIG_DVB_TDA1004X is not set +# CONFIG_DVB_NXT6000 is not set +# CONFIG_DVB_MT352 is not set +# CONFIG_DVB_ZL10353 is not set +# CONFIG_DVB_DIB3000MB is not set +# CONFIG_DVB_DIB3000MC is not set +# CONFIG_DVB_DIB7000M is not set +# CONFIG_DVB_DIB7000P is not set +# CONFIG_DVB_DIB9000 is not set +# CONFIG_DVB_TDA10048 is not set +# CONFIG_DVB_AF9013 is not set +# CONFIG_DVB_EC100 is not set +# CONFIG_DVB_STV0367 is not set +# CONFIG_DVB_CXD2820R is not set +# CONFIG_DVB_CXD2841ER is not set +# CONFIG_DVB_RTL2830 is not set +# CONFIG_DVB_RTL2832 is not set +# CONFIG_DVB_RTL2832_SDR is not set +# CONFIG_DVB_SI2168 is not set +# CONFIG_DVB_ZD1301_DEMOD is not set +# CONFIG_DVB_CXD2880 is not set + +# +# DVB-C (cable) frontends +# +# CONFIG_DVB_VES1820 is not set +# CONFIG_DVB_TDA10021 is not set +# CONFIG_DVB_TDA10023 is not set +# CONFIG_DVB_STV0297 is not set + +# +# ATSC (North American/Korean Terrestrial/Cable DTV) frontends +# +# CONFIG_DVB_NXT200X is not set +# CONFIG_DVB_OR51211 is not set +# CONFIG_DVB_OR51132 is not set +# CONFIG_DVB_BCM3510 is not set +# CONFIG_DVB_LGDT330X is not set +# CONFIG_DVB_LGDT3305 is not set +# CONFIG_DVB_LGDT3306A is not set +# CONFIG_DVB_LG2160 is not set +# CONFIG_DVB_S5H1409 is not set +# CONFIG_DVB_AU8522_DTV is not set +# CONFIG_DVB_AU8522_V4L is not set +# CONFIG_DVB_S5H1411 is not set + +# +# ISDB-T (terrestrial) frontends +# +# CONFIG_DVB_S921 is not set +# CONFIG_DVB_DIB8000 is not set +# CONFIG_DVB_MB86A20S is not set + +# +# ISDB-S (satellite) & ISDB-T (terrestrial) frontends +# +# CONFIG_DVB_TC90522 is not set +# CONFIG_DVB_MN88443X is not set + +# +# Digital terrestrial only tuners/PLL +# +# CONFIG_DVB_PLL is not set +# CONFIG_DVB_TUNER_DIB0070 is not set +# CONFIG_DVB_TUNER_DIB0090 is not set + +# +# SEC control devices for DVB-S +# +# CONFIG_DVB_DRX39XYJ is not set +# CONFIG_DVB_LNBH25 is not set +# CONFIG_DVB_LNBH29 is not set +# CONFIG_DVB_LNBP21 is not set +# CONFIG_DVB_LNBP22 is not set +# CONFIG_DVB_ISL6405 is not set +# CONFIG_DVB_ISL6421 is not set +# CONFIG_DVB_ISL6423 is not set +# CONFIG_DVB_A8293 is not set +# CONFIG_DVB_LGS8GL5 is not set +# CONFIG_DVB_LGS8GXX is not set +# CONFIG_DVB_ATBM8830 is not set +# CONFIG_DVB_TDA665x is not set +# CONFIG_DVB_IX2505V is not set +# CONFIG_DVB_M88RS2000 is not set +# CONFIG_DVB_AF9033 is not set +# CONFIG_DVB_HORUS3A is not set +# CONFIG_DVB_ASCOT2E is not set +# CONFIG_DVB_HELENE is not set + +# +# Common Interface (EN50221) controller drivers +# +# CONFIG_DVB_CXD2099 is not set +# CONFIG_DVB_SP2 is not set +# end of Customise DVB Frontends + +# +# Tools to develop new frontends +# +# CONFIG_DVB_DUMMY_FE is not set +# end of Media ancillary drivers + +# +# Graphics support +# +# CONFIG_VGA_ARB is not set +CONFIG_DRM=y +CONFIG_DRM_MIPI_DSI=y +CONFIG_DRM_DP_AUX_CHARDEV=y +# CONFIG_DRM_DEBUG_MM is not set +# CONFIG_DRM_DEBUG_SELFTEST is not set +CONFIG_DRM_KMS_HELPER=y +CONFIG_DRM_KMS_FB_HELPER=y +# CONFIG_DRM_DEBUG_DP_MST_TOPOLOGY_REFS is not set +CONFIG_DRM_FBDEV_EMULATION=y +CONFIG_DRM_FBDEV_OVERALLOC=100 +# CONFIG_DRM_FBDEV_LEAK_PHYS_SMEM is not set +CONFIG_DRM_LOAD_EDID_FIRMWARE=y +# CONFIG_DRM_DP_CEC is not set +CONFIG_DRM_GEM_CMA_HELPER=y +CONFIG_DRM_KMS_CMA_HELPER=y +CONFIG_DRM_GEM_SHMEM_HELPER=y +CONFIG_DRM_SCHED=y + +# +# I2C encoder or helper chips +# +# CONFIG_DRM_I2C_CH7006 is not set +# CONFIG_DRM_I2C_SIL164 is not set +# CONFIG_DRM_I2C_NXP_TDA998X is not set +# CONFIG_DRM_I2C_NXP_TDA9950 is not set +# end of I2C encoder or helper chips + +# +# ARM devices +# +# CONFIG_DRM_HDLCD is not set +# CONFIG_DRM_MALI_DISPLAY is not set +# CONFIG_DRM_KOMEDA is not set +# end of ARM devices + +# CONFIG_DRM_RADEON is not set +# CONFIG_DRM_AMDGPU is not set +# CONFIG_DRM_NOUVEAU is not set +# CONFIG_DRM_VGEM is not set +# CONFIG_DRM_VKMS is not set +# CONFIG_DRM_UDL is not set +# CONFIG_DRM_AST is not set +# CONFIG_DRM_MGAG200 is not set +# CONFIG_DRM_RCAR_DW_HDMI is not set +# CONFIG_DRM_RCAR_LVDS is not set +# CONFIG_DRM_QXL is not set +# CONFIG_DRM_BOCHS is not set +CONFIG_DRM_VIRTIO_GPU=y +CONFIG_DRM_PANEL=y + +# +# Display Panels +# +# CONFIG_DRM_PANEL_ABT_Y030XX067A is not set +# CONFIG_DRM_PANEL_ARM_VERSATILE is not set +# CONFIG_DRM_PANEL_ASUS_Z00T_TM5P5_NT35596 is not set +# CONFIG_DRM_PANEL_BOE_HIMAX8279D is not set +# CONFIG_DRM_PANEL_BOE_TV101WUM_NL6 is not set +CONFIG_DRM_PANEL_LVDS=y +CONFIG_DRM_PANEL_SIMPLE=y +# CONFIG_DRM_PANEL_ELIDA_KD35T133 is not set +# CONFIG_DRM_PANEL_FEIXIN_K101_IM2BA02 is not set +# CONFIG_DRM_PANEL_FEIYANG_FY07024DI26A30D is not set +# CONFIG_DRM_PANEL_ILITEK_IL9322 is not set +# CONFIG_DRM_PANEL_ILITEK_ILI9881C is not set +# CONFIG_DRM_PANEL_INNOLUX_P079ZCA is not set +# CONFIG_DRM_PANEL_JDI_LT070ME05000 is not set +# CONFIG_DRM_PANEL_KINGDISPLAY_KD097D04 is not set +# CONFIG_DRM_PANEL_LEADTEK_LTK050H3146W is not set +# CONFIG_DRM_PANEL_LEADTEK_LTK500HD1829 is not set +# CONFIG_DRM_PANEL_SAMSUNG_LD9040 is not set +# CONFIG_DRM_PANEL_LG_LB035Q02 is not set +# CONFIG_DRM_PANEL_LG_LG4573 is not set +# CONFIG_DRM_PANEL_NEC_NL8048HL11 is not set +# CONFIG_DRM_PANEL_NOVATEK_NT35510 is not set +# CONFIG_DRM_PANEL_NOVATEK_NT36672A is not set +# CONFIG_DRM_PANEL_NOVATEK_NT39016 is not set +# CONFIG_DRM_PANEL_MANTIX_MLAF057WE51 is not set +# CONFIG_DRM_PANEL_OLIMEX_LCD_OLINUXINO is not set +# CONFIG_DRM_PANEL_ORISETECH_OTM8009A is not set +# CONFIG_DRM_PANEL_OSD_OSD101T2587_53TS is not set +# CONFIG_DRM_PANEL_PANASONIC_VVX10F034N00 is not set +# CONFIG_DRM_PANEL_RASPBERRYPI_TOUCHSCREEN is not set +# CONFIG_DRM_PANEL_RAYDIUM_RM67191 is not set +# CONFIG_DRM_PANEL_RAYDIUM_RM68200 is not set +# CONFIG_DRM_PANEL_RONBO_RB070D30 is not set +# CONFIG_DRM_PANEL_SAMSUNG_S6D16D0 is not set +# CONFIG_DRM_PANEL_SAMSUNG_S6E3HA2 is not set +# CONFIG_DRM_PANEL_SAMSUNG_S6E63J0X03 is not set +# CONFIG_DRM_PANEL_SAMSUNG_S6E63M0 is not set +# CONFIG_DRM_PANEL_SAMSUNG_S6E88A0_AMS452EF01 is not set +# CONFIG_DRM_PANEL_SAMSUNG_S6E8AA0 is not set +# CONFIG_DRM_PANEL_SAMSUNG_SOFEF00 is not set +# CONFIG_DRM_PANEL_SEIKO_43WVF1G is not set +# CONFIG_DRM_PANEL_SHARP_LQ101R1SX01 is not set +# CONFIG_DRM_PANEL_SHARP_LS037V7DW01 is not set +# CONFIG_DRM_PANEL_SHARP_LS043T1LE01 is not set +# CONFIG_DRM_PANEL_SITRONIX_ST7701 is not set +# CONFIG_DRM_PANEL_SITRONIX_ST7703 is not set +# CONFIG_DRM_PANEL_SITRONIX_ST7789V is not set +# CONFIG_DRM_PANEL_SONY_ACX424AKP is not set +# CONFIG_DRM_PANEL_SONY_ACX565AKM is not set +# CONFIG_DRM_PANEL_TDO_TL070WSH30 is not set +# CONFIG_DRM_PANEL_TPO_TD028TTEC1 is not set +# CONFIG_DRM_PANEL_TPO_TD043MTEA1 is not set +# CONFIG_DRM_PANEL_TPO_TPG110 is not set +# CONFIG_DRM_PANEL_TRULY_NT35597_WQXGA is not set +# CONFIG_DRM_PANEL_VISIONOX_RM69299 is not set +# CONFIG_DRM_PANEL_XINPENG_XPP055C272 is not set +# end of Display Panels + +CONFIG_DRM_BRIDGE=y +CONFIG_DRM_PANEL_BRIDGE=y + +# +# Display Interface Bridges +# +# CONFIG_DRM_CDNS_DSI is not set +# CONFIG_DRM_CHRONTEL_CH7033 is not set +CONFIG_DRM_DISPLAY_CONNECTOR=y +# CONFIG_DRM_LONTIUM_LT9611 is not set +# CONFIG_DRM_LONTIUM_LT9611UXC is not set +CONFIG_DRM_LVDS_CODEC=y +# CONFIG_DRM_MEGACHIPS_STDPXXXX_GE_B850V3_FW is not set +CONFIG_DRM_NWL_MIPI_DSI=y +# CONFIG_DRM_NXP_PTN3460 is not set +# CONFIG_DRM_PARADE_PS8622 is not set +# CONFIG_DRM_PARADE_PS8640 is not set +# CONFIG_DRM_SIL_SII8620 is not set +# CONFIG_DRM_SII902X is not set +# CONFIG_DRM_SII9234 is not set +CONFIG_DRM_SIMPLE_BRIDGE=y +# CONFIG_DRM_THINE_THC63LVD1024 is not set +# CONFIG_DRM_TOSHIBA_TC358762 is not set +# CONFIG_DRM_TOSHIBA_TC358764 is not set +# CONFIG_DRM_TOSHIBA_TC358767 is not set +# CONFIG_DRM_TOSHIBA_TC358768 is not set +# CONFIG_DRM_TOSHIBA_TC358775 is not set +# CONFIG_DRM_TI_TFP410 is not set +CONFIG_DRM_TI_SN65DSI86=y +# CONFIG_DRM_TI_TPD12S015 is not set +# CONFIG_DRM_ANALOGIX_ANX6345 is not set +# CONFIG_DRM_ANALOGIX_ANX78XX is not set +# CONFIG_DRM_ANALOGIX_ANX7625 is not set +# CONFIG_DRM_I2C_ADV7511 is not set +CONFIG_DRM_CDNS_MHDP8546=y +CONFIG_DRM_CDNS_MHDP=y +CONFIG_DRM_CDNS_HDMI=y +CONFIG_DRM_CDNS_DP=y +CONFIG_DRM_CDNS_AUDIO=y +CONFIG_DRM_CDNS_HDMI_CEC=y +# end of Display Interface Bridges + +CONFIG_DRM_IMX_CDNS_MHDP=y +CONFIG_DRM_IMX_DCSS=y +CONFIG_DRM_ETNAVIV=y +CONFIG_DRM_ETNAVIV_THERMAL=y +# CONFIG_DRM_ARCPGU is not set +# CONFIG_DRM_HISI_HIBMC is not set +# CONFIG_DRM_HISI_KIRIN is not set +CONFIG_DRM_MXS=y +CONFIG_DRM_MXSFB=y +# CONFIG_DRM_CIRRUS_QEMU is not set +# CONFIG_DRM_GM12U320 is not set +# CONFIG_TINYDRM_HX8357D is not set +# CONFIG_TINYDRM_ILI9225 is not set +# CONFIG_TINYDRM_ILI9341 is not set +# CONFIG_TINYDRM_ILI9486 is not set +# CONFIG_TINYDRM_MI0283QT is not set +# CONFIG_TINYDRM_REPAPER is not set +# CONFIG_TINYDRM_ST7586 is not set +# CONFIG_TINYDRM_ST7735R is not set +# CONFIG_DRM_PL111 is not set +# CONFIG_DRM_XEN is not set +# CONFIG_DRM_LIMA is not set +# CONFIG_DRM_PANFROST is not set +# CONFIG_DRM_TIDSS is not set +# CONFIG_DRM_LEGACY is not set +CONFIG_DRM_PANEL_ORIENTATION_QUIRKS=y + +# +# Frame buffer Devices +# +CONFIG_FB_CMDLINE=y +CONFIG_FB_NOTIFY=y +CONFIG_FB=y +CONFIG_FIRMWARE_EDID=y +CONFIG_FB_CFB_FILLRECT=y +CONFIG_FB_CFB_COPYAREA=y +CONFIG_FB_CFB_IMAGEBLIT=y +CONFIG_FB_SYS_FILLRECT=y +CONFIG_FB_SYS_COPYAREA=y +CONFIG_FB_SYS_IMAGEBLIT=y +# CONFIG_FB_FOREIGN_ENDIAN is not set +CONFIG_FB_SYS_FOPS=y +CONFIG_FB_DEFERRED_IO=y +CONFIG_FB_MODE_HELPERS=y +CONFIG_FB_TILEBLITTING=y + +# +# Frame buffer hardware drivers +# +# CONFIG_FB_CIRRUS is not set +# CONFIG_FB_PM2 is not set +# CONFIG_FB_ARMCLCD is not set +# CONFIG_FB_IMX is not set +# CONFIG_FB_CYBER2000 is not set +# CONFIG_FB_ASILIANT is not set +# CONFIG_FB_IMSTT is not set +# CONFIG_FB_UVESA is not set +CONFIG_FB_EFI=y +# CONFIG_FB_OPENCORES is not set +# CONFIG_FB_S1D13XXX is not set +# CONFIG_FB_NVIDIA is not set +# CONFIG_FB_RIVA is not set +# CONFIG_FB_I740 is not set +# CONFIG_FB_MATROX is not set +# CONFIG_FB_RADEON is not set +# CONFIG_FB_ATY128 is not set +# CONFIG_FB_ATY is not set +# CONFIG_FB_S3 is not set +# CONFIG_FB_SAVAGE is not set +# CONFIG_FB_SIS is not set +# CONFIG_FB_NEOMAGIC is not set +# CONFIG_FB_KYRO is not set +# CONFIG_FB_3DFX is not set +# CONFIG_FB_VOODOO1 is not set +# CONFIG_FB_VT8623 is not set +# CONFIG_FB_TRIDENT is not set +# CONFIG_FB_ARK is not set +# CONFIG_FB_PM3 is not set +# CONFIG_FB_CARMINE is not set +# CONFIG_FB_SMSCUFX is not set +CONFIG_FB_UDL=y +# CONFIG_FB_IBM_GXT4500 is not set +# CONFIG_FB_VIRTUAL is not set +# CONFIG_XEN_FBDEV_FRONTEND is not set +# CONFIG_FB_METRONOME is not set +# CONFIG_FB_MB862XX is not set +# CONFIG_FB_MX3 is not set +CONFIG_FB_SIMPLE=y +# CONFIG_FB_SSD1307 is not set +# CONFIG_FB_SM712 is not set +# end of Frame buffer Devices + +# +# Backlight & LCD device support +# +# CONFIG_LCD_CLASS_DEVICE is not set +CONFIG_BACKLIGHT_CLASS_DEVICE=y +# CONFIG_BACKLIGHT_KTD253 is not set +CONFIG_BACKLIGHT_PWM=y +# CONFIG_BACKLIGHT_QCOM_WLED is not set +# CONFIG_BACKLIGHT_ADP8860 is not set +# CONFIG_BACKLIGHT_ADP8870 is not set +# CONFIG_BACKLIGHT_LM3630A is not set +# CONFIG_BACKLIGHT_LM3639 is not set +# CONFIG_BACKLIGHT_LP855X is not set +CONFIG_BACKLIGHT_GPIO=y +# CONFIG_BACKLIGHT_LV5207LP is not set +# CONFIG_BACKLIGHT_BD6107 is not set +# CONFIG_BACKLIGHT_ARCXCNN is not set +CONFIG_BACKLIGHT_LED=y +# end of Backlight & LCD device support + +CONFIG_VIDEOMODE_HELPERS=y +CONFIG_HDMI=y + +# +# Console display driver support +# +CONFIG_DUMMY_CONSOLE=y +CONFIG_DUMMY_CONSOLE_COLUMNS=80 +CONFIG_DUMMY_CONSOLE_ROWS=25 +CONFIG_FRAMEBUFFER_CONSOLE=y +CONFIG_FRAMEBUFFER_CONSOLE_DETECT_PRIMARY=y +# CONFIG_FRAMEBUFFER_CONSOLE_ROTATION is not set +# CONFIG_FRAMEBUFFER_CONSOLE_DEFERRED_TAKEOVER is not set +# end of Console display driver support + +CONFIG_LOGO=y +CONFIG_LOGO_LINUX_MONO=y +# CONFIG_LOGO_LINUX_VGA16 is not set +# CONFIG_LOGO_LINUX_CLUT224 is not set +# end of Graphics support + +CONFIG_SOUND=y +CONFIG_SOUND_OSS_CORE=y +CONFIG_SOUND_OSS_CORE_PRECLAIM=y +CONFIG_SND=y +CONFIG_SND_TIMER=y +CONFIG_SND_PCM=y +CONFIG_SND_PCM_ELD=y +CONFIG_SND_PCM_IEC958=y +CONFIG_SND_DMAENGINE_PCM=y +CONFIG_SND_HWDEP=y +CONFIG_SND_SEQ_DEVICE=y +CONFIG_SND_RAWMIDI=y +CONFIG_SND_JACK=y +CONFIG_SND_JACK_INPUT_DEV=y +CONFIG_SND_OSSEMUL=y +CONFIG_SND_MIXER_OSS=y +CONFIG_SND_PCM_OSS=y +# CONFIG_SND_PCM_OSS_PLUGINS is not set +CONFIG_SND_PCM_TIMER=y +CONFIG_SND_HRTIMER=y +CONFIG_SND_DYNAMIC_MINORS=y +CONFIG_SND_MAX_CARDS=32 +CONFIG_SND_SUPPORT_OLD_API=y +CONFIG_SND_PROC_FS=y +CONFIG_SND_VERBOSE_PROCFS=y +# CONFIG_SND_VERBOSE_PRINTK is not set +# CONFIG_SND_DEBUG is not set +CONFIG_SND_VMASTER=y +CONFIG_SND_SEQUENCER=y +# CONFIG_SND_SEQ_DUMMY is not set +# CONFIG_SND_SEQUENCER_OSS is not set +CONFIG_SND_SEQ_HRTIMER_DEFAULT=y +CONFIG_SND_SEQ_MIDI_EVENT=y +CONFIG_SND_SEQ_MIDI=y +CONFIG_SND_AC97_CODEC=y +CONFIG_SND_DRIVERS=y +# CONFIG_SND_DUMMY is not set +# CONFIG_SND_ALOOP is not set +# CONFIG_SND_VIRMIDI is not set +# CONFIG_SND_MTPAV is not set +# CONFIG_SND_SERIAL_U16550 is not set +# CONFIG_SND_MPU401 is not set +# CONFIG_SND_AC97_POWER_SAVE is not set +# CONFIG_SND_PCI is not set + +# +# HD-Audio +# +# end of HD-Audio + +CONFIG_SND_HDA_PREALLOC_SIZE=2048 +# CONFIG_SND_SPI is not set +CONFIG_SND_USB=y +CONFIG_SND_USB_AUDIO=y +CONFIG_SND_USB_AUDIO_USE_MEDIA_CONTROLLER=y +# CONFIG_SND_USB_UA101 is not set +# CONFIG_SND_USB_CAIAQ is not set +# CONFIG_SND_USB_6FIRE is not set +# CONFIG_SND_USB_HIFACE is not set +# CONFIG_SND_BCD2000 is not set +# CONFIG_SND_USB_POD is not set +# CONFIG_SND_USB_PODHD is not set +# CONFIG_SND_USB_TONEPORT is not set +# CONFIG_SND_USB_VARIAX is not set +CONFIG_SND_SOC=y +CONFIG_SND_SOC_AC97_BUS=y +CONFIG_SND_SOC_GENERIC_DMAENGINE_PCM=y +# CONFIG_SND_SOC_ADI is not set +# CONFIG_SND_SOC_AMD_ACP is not set +# CONFIG_SND_ATMEL_SOC is not set +# CONFIG_SND_BCM63XX_I2S_WHISTLER is not set +# CONFIG_SND_DESIGNWARE_I2S is not set + +# +# SoC Audio for Freescale CPUs +# + +# +# Common SoC Audio options for Freescale CPUs: +# +CONFIG_SND_SOC_FSL_ASRC=y +CONFIG_SND_SOC_FSL_SAI=y +# CONFIG_SND_SOC_FSL_MQS is not set +CONFIG_SND_SOC_FSL_AUDMIX=y +CONFIG_SND_SOC_FSL_SSI=y +CONFIG_SND_SOC_FSL_SPDIF=y +CONFIG_SND_SOC_FSL_ESAI=y +CONFIG_SND_SOC_FSL_MICFIL=y +# CONFIG_SND_SOC_FSL_EASRC is not set +# CONFIG_SND_SOC_FSL_XCVR is not set +CONFIG_SND_SOC_FSL_AUD2HTX=y +CONFIG_SND_SOC_IMX_PCM_DMA=y +CONFIG_SND_SOC_IMX_AUDMUX=y +CONFIG_SND_IMX_SOC=y + +# +# SoC Audio support for Freescale i.MX boards: +# +# CONFIG_SND_SOC_IMX_ES8328 is not set +# CONFIG_SND_SOC_IMX_SGTL5000 is not set +CONFIG_SND_SOC_IMX_SPDIF=y +CONFIG_SND_SOC_FSL_ASOC_CARD=y +CONFIG_SND_SOC_IMX_AUDMIX=y +CONFIG_SND_SOC_IMX_HDMI=y +# end of SoC Audio for Freescale CPUs + +# CONFIG_SND_I2S_HI6210_I2S is not set +# CONFIG_SND_SOC_IMG is not set +# CONFIG_SND_SOC_MTK_BTCVSD is not set +# CONFIG_SND_SOC_SOF_TOPLEVEL is not set + +# +# STMicroelectronics STM32 SOC audio support +# +# end of STMicroelectronics STM32 SOC audio support + +# CONFIG_SND_SOC_XILINX_I2S is not set +# CONFIG_SND_SOC_XILINX_AUDIO_FORMATTER is not set +# CONFIG_SND_SOC_XILINX_SPDIF is not set +# CONFIG_SND_SOC_XTFPGA_I2S is not set +# CONFIG_ZX_TDM is not set +CONFIG_SND_SOC_I2C_AND_SPI=y + +# +# CODEC drivers +# +CONFIG_SND_SOC_AC97_CODEC=y +# CONFIG_SND_SOC_ADAU1372_I2C is not set +# CONFIG_SND_SOC_ADAU1372_SPI is not set +# CONFIG_SND_SOC_ADAU1701 is not set +# CONFIG_SND_SOC_ADAU1761_I2C is not set +# CONFIG_SND_SOC_ADAU1761_SPI is not set +# CONFIG_SND_SOC_ADAU7002 is not set +# CONFIG_SND_SOC_ADAU7118_HW is not set +# CONFIG_SND_SOC_ADAU7118_I2C is not set +# CONFIG_SND_SOC_AK4104 is not set +# CONFIG_SND_SOC_AK4118 is not set +# CONFIG_SND_SOC_AK4458 is not set +# CONFIG_SND_SOC_AK4554 is not set +# CONFIG_SND_SOC_AK4613 is not set +# CONFIG_SND_SOC_AK4642 is not set +# CONFIG_SND_SOC_AK5386 is not set +# CONFIG_SND_SOC_AK5558 is not set +# CONFIG_SND_SOC_ALC5623 is not set +# CONFIG_SND_SOC_BD28623 is not set +# CONFIG_SND_SOC_BT_SCO is not set +# CONFIG_SND_SOC_CS35L32 is not set +# CONFIG_SND_SOC_CS35L33 is not set +# CONFIG_SND_SOC_CS35L34 is not set +# CONFIG_SND_SOC_CS35L35 is not set +# CONFIG_SND_SOC_CS35L36 is not set +# CONFIG_SND_SOC_CS42L42 is not set +# CONFIG_SND_SOC_CS42L51_I2C is not set +# CONFIG_SND_SOC_CS42L52 is not set +# CONFIG_SND_SOC_CS42L56 is not set +# CONFIG_SND_SOC_CS42L73 is not set +# CONFIG_SND_SOC_CS4234 is not set +# CONFIG_SND_SOC_CS4265 is not set +# CONFIG_SND_SOC_CS4270 is not set +# CONFIG_SND_SOC_CS4271_I2C is not set +# CONFIG_SND_SOC_CS4271_SPI is not set +# CONFIG_SND_SOC_CS42XX8_I2C is not set +# CONFIG_SND_SOC_CS43130 is not set +# CONFIG_SND_SOC_CS4341 is not set +# CONFIG_SND_SOC_CS4349 is not set +# CONFIG_SND_SOC_CS53L30 is not set +# CONFIG_SND_SOC_CX2072X is not set +# CONFIG_SND_SOC_DA7213 is not set +# CONFIG_SND_SOC_DMIC is not set +CONFIG_SND_SOC_HDMI_CODEC=y +# CONFIG_SND_SOC_ES7134 is not set +# CONFIG_SND_SOC_ES7241 is not set +# CONFIG_SND_SOC_ES8316 is not set +# CONFIG_SND_SOC_ES8328_I2C is not set +# CONFIG_SND_SOC_ES8328_SPI is not set +# CONFIG_SND_SOC_GTM601 is not set +# CONFIG_SND_SOC_INNO_RK3036 is not set +# CONFIG_SND_SOC_MAX98088 is not set +# CONFIG_SND_SOC_MAX98357A is not set +# CONFIG_SND_SOC_MAX98504 is not set +# CONFIG_SND_SOC_MAX9867 is not set +# CONFIG_SND_SOC_MAX98927 is not set +# CONFIG_SND_SOC_MAX98373_I2C is not set +# CONFIG_SND_SOC_MAX98390 is not set +# CONFIG_SND_SOC_MAX9860 is not set +# CONFIG_SND_SOC_MSM8916_WCD_DIGITAL is not set +# CONFIG_SND_SOC_PCM1681 is not set +# CONFIG_SND_SOC_PCM1789_I2C is not set +# CONFIG_SND_SOC_PCM179X_I2C is not set +# CONFIG_SND_SOC_PCM179X_SPI is not set +# CONFIG_SND_SOC_PCM186X_I2C is not set +# CONFIG_SND_SOC_PCM186X_SPI is not set +# CONFIG_SND_SOC_PCM3060_I2C is not set +# CONFIG_SND_SOC_PCM3060_SPI is not set +# CONFIG_SND_SOC_PCM3168A_I2C is not set +# CONFIG_SND_SOC_PCM3168A_SPI is not set +# CONFIG_SND_SOC_PCM5102A is not set +# CONFIG_SND_SOC_PCM512x_I2C is not set +# CONFIG_SND_SOC_PCM512x_SPI is not set +# CONFIG_SND_SOC_RK3328 is not set +# CONFIG_SND_SOC_RT5616 is not set +# CONFIG_SND_SOC_RT5631 is not set +# CONFIG_SND_SOC_SGTL5000 is not set +# CONFIG_SND_SOC_SIMPLE_AMPLIFIER is not set +# CONFIG_SND_SOC_SIMPLE_MUX is not set +# CONFIG_SND_SOC_SIRF_AUDIO_CODEC is not set +# CONFIG_SND_SOC_SPDIF is not set +# CONFIG_SND_SOC_SSM2305 is not set +# CONFIG_SND_SOC_SSM2602_SPI is not set +# CONFIG_SND_SOC_SSM2602_I2C is not set +# CONFIG_SND_SOC_SSM4567 is not set +# CONFIG_SND_SOC_STA32X is not set +# CONFIG_SND_SOC_STA350 is not set +# CONFIG_SND_SOC_STI_SAS is not set +# CONFIG_SND_SOC_TAS2552 is not set +# CONFIG_SND_SOC_TAS2562 is not set +# CONFIG_SND_SOC_TAS2764 is not set +# CONFIG_SND_SOC_TAS2770 is not set +# CONFIG_SND_SOC_TAS5086 is not set +# CONFIG_SND_SOC_TAS571X is not set +# CONFIG_SND_SOC_TAS5720 is not set +# CONFIG_SND_SOC_TAS6424 is not set +# CONFIG_SND_SOC_TDA7419 is not set +# CONFIG_SND_SOC_TFA9879 is not set +# CONFIG_SND_SOC_TLV320AIC23_I2C is not set +# CONFIG_SND_SOC_TLV320AIC23_SPI is not set +# CONFIG_SND_SOC_TLV320AIC31XX is not set +# CONFIG_SND_SOC_TLV320AIC32X4_I2C is not set +# CONFIG_SND_SOC_TLV320AIC32X4_SPI is not set +# CONFIG_SND_SOC_TLV320AIC3X is not set +# CONFIG_SND_SOC_TLV320ADCX140 is not set +# CONFIG_SND_SOC_TS3A227E is not set +# CONFIG_SND_SOC_TSCS42XX is not set +# CONFIG_SND_SOC_TSCS454 is not set +# CONFIG_SND_SOC_UDA1334 is not set +# CONFIG_SND_SOC_WM8510 is not set +# CONFIG_SND_SOC_WM8523 is not set +# CONFIG_SND_SOC_WM8524 is not set +# CONFIG_SND_SOC_WM8580 is not set +# CONFIG_SND_SOC_WM8711 is not set +# CONFIG_SND_SOC_WM8728 is not set +# CONFIG_SND_SOC_WM8731 is not set +# CONFIG_SND_SOC_WM8737 is not set +# CONFIG_SND_SOC_WM8741 is not set +# CONFIG_SND_SOC_WM8750 is not set +# CONFIG_SND_SOC_WM8753 is not set +# CONFIG_SND_SOC_WM8770 is not set +# CONFIG_SND_SOC_WM8776 is not set +# CONFIG_SND_SOC_WM8782 is not set +# CONFIG_SND_SOC_WM8804_I2C is not set +# CONFIG_SND_SOC_WM8804_SPI is not set +# CONFIG_SND_SOC_WM8903 is not set +# CONFIG_SND_SOC_WM8904 is not set +CONFIG_SND_SOC_WM8960=y +# CONFIG_SND_SOC_WM8962 is not set +# CONFIG_SND_SOC_WM8974 is not set +# CONFIG_SND_SOC_WM8978 is not set +# CONFIG_SND_SOC_WM8985 is not set +# CONFIG_SND_SOC_ZL38060 is not set +# CONFIG_SND_SOC_ZX_AUD96P22 is not set +# CONFIG_SND_SOC_MAX9759 is not set +# CONFIG_SND_SOC_MT6351 is not set +# CONFIG_SND_SOC_MT6358 is not set +# CONFIG_SND_SOC_MT6660 is not set +# CONFIG_SND_SOC_NAU8315 is not set +# CONFIG_SND_SOC_NAU8540 is not set +# CONFIG_SND_SOC_NAU8810 is not set +# CONFIG_SND_SOC_NAU8822 is not set +# CONFIG_SND_SOC_NAU8824 is not set +# CONFIG_SND_SOC_TPA6130A2 is not set +# CONFIG_SND_SOC_LPASS_WSA_MACRO is not set +# CONFIG_SND_SOC_LPASS_VA_MACRO is not set +# end of CODEC drivers + +CONFIG_SND_SIMPLE_CARD_UTILS=y +CONFIG_SND_SIMPLE_CARD=y +CONFIG_SND_AUDIO_GRAPH_CARD=y +# CONFIG_SND_XEN_FRONTEND is not set +CONFIG_AC97_BUS=y + +# +# HID support +# +CONFIG_HID=y +CONFIG_HID_BATTERY_STRENGTH=y +CONFIG_HIDRAW=y +CONFIG_UHID=y +CONFIG_HID_GENERIC=y + +# +# Special HID drivers +# +# CONFIG_HID_A4TECH is not set +# CONFIG_HID_ACCUTOUCH is not set +# CONFIG_HID_ACRUX is not set +# CONFIG_HID_APPLE is not set +# CONFIG_HID_APPLEIR is not set +# CONFIG_HID_ASUS is not set +# CONFIG_HID_AUREAL is not set +# CONFIG_HID_BELKIN is not set +# CONFIG_HID_BETOP_FF is not set +# CONFIG_HID_BIGBEN_FF is not set +# CONFIG_HID_CHERRY is not set +# CONFIG_HID_CHICONY is not set +# CONFIG_HID_CORSAIR is not set +# CONFIG_HID_COUGAR is not set +# CONFIG_HID_MACALLY is not set +# CONFIG_HID_PRODIKEYS is not set +# CONFIG_HID_CMEDIA is not set +# CONFIG_HID_CP2112 is not set +# CONFIG_HID_CREATIVE_SB0540 is not set +# CONFIG_HID_CYPRESS is not set +# CONFIG_HID_DRAGONRISE is not set +# CONFIG_HID_EMS_FF is not set +# CONFIG_HID_ELAN is not set +# CONFIG_HID_ELECOM is not set +# CONFIG_HID_ELO is not set +# CONFIG_HID_EZKEY is not set +# CONFIG_HID_GEMBIRD is not set +# CONFIG_HID_GFRM is not set +# CONFIG_HID_GLORIOUS is not set +# CONFIG_HID_HOLTEK is not set +# CONFIG_HID_VIVALDI is not set +# CONFIG_HID_GT683R is not set +# CONFIG_HID_KEYTOUCH is not set +# CONFIG_HID_KYE is not set +# CONFIG_HID_UCLOGIC is not set +# CONFIG_HID_WALTOP is not set +# CONFIG_HID_VIEWSONIC is not set +# CONFIG_HID_GYRATION is not set +# CONFIG_HID_ICADE is not set +# CONFIG_HID_ITE is not set +# CONFIG_HID_JABRA is not set +# CONFIG_HID_TWINHAN is not set +# CONFIG_HID_KENSINGTON is not set +# CONFIG_HID_LCPOWER is not set +# CONFIG_HID_LED is not set +# CONFIG_HID_LENOVO is not set +CONFIG_HID_LOGITECH=y +CONFIG_HID_LOGITECH_DJ=y +CONFIG_HID_LOGITECH_HIDPP=y +# CONFIG_LOGITECH_FF is not set +# CONFIG_LOGIRUMBLEPAD2_FF is not set +# CONFIG_LOGIG940_FF is not set +# CONFIG_LOGIWHEELS_FF is not set +CONFIG_HID_MAGICMOUSE=y +# CONFIG_HID_MALTRON is not set +# CONFIG_HID_MAYFLASH is not set +# CONFIG_HID_REDRAGON is not set +CONFIG_HID_MICROSOFT=y +# CONFIG_HID_MONTEREY is not set +# CONFIG_HID_MULTITOUCH is not set +# CONFIG_HID_NTI is not set +# CONFIG_HID_NTRIG is not set +# CONFIG_HID_ORTEK is not set +# CONFIG_HID_PANTHERLORD is not set +# CONFIG_HID_PENMOUNT is not set +# CONFIG_HID_PETALYNX is not set +# CONFIG_HID_PICOLCD is not set +# CONFIG_HID_PLANTRONICS is not set +# CONFIG_HID_PRIMAX is not set +# CONFIG_HID_RETRODE is not set +# CONFIG_HID_ROCCAT is not set +# CONFIG_HID_SAITEK is not set +# CONFIG_HID_SAMSUNG is not set +CONFIG_HID_SONY=y +CONFIG_SONY_FF=y +# CONFIG_HID_SPEEDLINK is not set +# CONFIG_HID_STEAM is not set +# CONFIG_HID_STEELSERIES is not set +# CONFIG_HID_SUNPLUS is not set +# CONFIG_HID_RMI is not set +# CONFIG_HID_GREENASIA is not set +# CONFIG_HID_SMARTJOYPLUS is not set +# CONFIG_HID_TIVO is not set +# CONFIG_HID_TOPSEED is not set +# CONFIG_HID_THINGM is not set +# CONFIG_HID_THRUSTMASTER is not set +# CONFIG_HID_UDRAW_PS3 is not set +# CONFIG_HID_U2FZERO is not set +CONFIG_HID_WACOM=y +CONFIG_HID_WIIMOTE=y +# CONFIG_HID_XINMO is not set +# CONFIG_HID_ZEROPLUS is not set +# CONFIG_HID_ZYDACRON is not set +# CONFIG_HID_SENSOR_HUB is not set +# CONFIG_HID_ALPS is not set +# CONFIG_HID_MCP2221 is not set +# end of Special HID drivers + +# +# USB HID support +# +CONFIG_USB_HID=y +CONFIG_HID_PID=y +CONFIG_USB_HIDDEV=y +# end of USB HID support + +# +# I2C HID support +# +# CONFIG_I2C_HID is not set +# end of I2C HID support +# end of HID support + +CONFIG_USB_OHCI_LITTLE_ENDIAN=y +CONFIG_USB_SUPPORT=y +CONFIG_USB_COMMON=y +CONFIG_USB_LED_TRIG=y +CONFIG_USB_ULPI_BUS=y +# CONFIG_USB_CONN_GPIO is not set +CONFIG_USB_ARCH_HAS_HCD=y +CONFIG_USB=y +CONFIG_USB_PCI=y +CONFIG_USB_ANNOUNCE_NEW_DEVICES=y + +# +# Miscellaneous USB options +# +CONFIG_USB_DEFAULT_PERSIST=y +# CONFIG_USB_FEW_INIT_RETRIES is not set +CONFIG_USB_DYNAMIC_MINORS=y +CONFIG_USB_OTG=y +# CONFIG_USB_OTG_PRODUCTLIST is not set +# CONFIG_USB_OTG_DISABLE_EXTERNAL_HUB is not set +# CONFIG_USB_OTG_FSM is not set +# CONFIG_USB_LEDS_TRIGGER_USBPORT is not set +CONFIG_USB_AUTOSUSPEND_DELAY=2 +CONFIG_USB_MON=y + +# +# USB Host Controller Drivers +# +# CONFIG_USB_C67X00_HCD is not set +CONFIG_USB_XHCI_HCD=y +# CONFIG_USB_XHCI_DBGCAP is not set +CONFIG_USB_XHCI_PCI=y +# CONFIG_USB_XHCI_PCI_RENESAS is not set +CONFIG_USB_XHCI_PLATFORM=y +CONFIG_USB_EHCI_HCD=y +CONFIG_USB_EHCI_ROOT_HUB_TT=y +CONFIG_USB_EHCI_TT_NEWSCHED=y +CONFIG_USB_EHCI_PCI=y +CONFIG_USB_EHCI_FSL=y +# CONFIG_USB_EHCI_HCD_PLATFORM is not set +# CONFIG_USB_OXU210HP_HCD is not set +# CONFIG_USB_ISP116X_HCD is not set +# CONFIG_USB_FOTG210_HCD is not set +# CONFIG_USB_MAX3421_HCD is not set +CONFIG_USB_OHCI_HCD=y +# CONFIG_USB_OHCI_HCD_PCI is not set +# CONFIG_USB_OHCI_HCD_SSB is not set +# CONFIG_USB_OHCI_HCD_PLATFORM is not set +# CONFIG_USB_UHCI_HCD is not set +# CONFIG_USB_SL811_HCD is not set +# CONFIG_USB_R8A66597_HCD is not set +# CONFIG_USB_HCD_BCMA is not set +# CONFIG_USB_HCD_SSB is not set +# CONFIG_USB_HCD_TEST_MODE is not set + +# +# USB Device Class drivers +# +CONFIG_USB_ACM=y +CONFIG_USB_PRINTER=y +CONFIG_USB_WDM=y +CONFIG_USB_TMC=y + +# +# NOTE: USB_STORAGE depends on SCSI but BLK_DEV_SD may +# + +# +# also be needed; see USB_STORAGE Help for more info +# +CONFIG_USB_STORAGE=y +# CONFIG_USB_STORAGE_DEBUG is not set +# CONFIG_USB_STORAGE_REALTEK is not set +# CONFIG_USB_STORAGE_DATAFAB is not set +# CONFIG_USB_STORAGE_FREECOM is not set +# CONFIG_USB_STORAGE_ISD200 is not set +# CONFIG_USB_STORAGE_USBAT is not set +# CONFIG_USB_STORAGE_SDDR09 is not set +# CONFIG_USB_STORAGE_SDDR55 is not set +# CONFIG_USB_STORAGE_JUMPSHOT is not set +# CONFIG_USB_STORAGE_ALAUDA is not set +# CONFIG_USB_STORAGE_ONETOUCH is not set +# CONFIG_USB_STORAGE_KARMA is not set +# CONFIG_USB_STORAGE_CYPRESS_ATACB is not set +# CONFIG_USB_STORAGE_ENE_UB6250 is not set +CONFIG_USB_UAS=y + +# +# USB Imaging devices +# +# CONFIG_USB_MDC800 is not set +# CONFIG_USB_MICROTEK is not set +# CONFIG_USBIP_CORE is not set +# CONFIG_USB_CDNS3 is not set +# CONFIG_USB_MUSB_HDRC is not set +CONFIG_USB_DWC3=y +# CONFIG_USB_DWC3_ULPI is not set +CONFIG_USB_DWC3_HOST=y + +# +# Platform Glue Driver Support +# +# CONFIG_USB_DWC3_HAPS is not set +# CONFIG_USB_DWC3_OF_SIMPLE is not set +# CONFIG_USB_DWC2 is not set +# CONFIG_USB_CHIPIDEA is not set +# CONFIG_USB_ISP1760 is not set + +# +# USB port drivers +# +CONFIG_USB_SERIAL=y +# CONFIG_USB_SERIAL_CONSOLE is not set +CONFIG_USB_SERIAL_GENERIC=y +# CONFIG_USB_SERIAL_SIMPLE is not set +# CONFIG_USB_SERIAL_AIRCABLE is not set +# CONFIG_USB_SERIAL_ARK3116 is not set +# CONFIG_USB_SERIAL_BELKIN is not set +# CONFIG_USB_SERIAL_CH341 is not set +# CONFIG_USB_SERIAL_WHITEHEAT is not set +# CONFIG_USB_SERIAL_DIGI_ACCELEPORT is not set +CONFIG_USB_SERIAL_CP210X=y +# CONFIG_USB_SERIAL_CYPRESS_M8 is not set +# CONFIG_USB_SERIAL_EMPEG is not set +CONFIG_USB_SERIAL_FTDI_SIO=y +# CONFIG_USB_SERIAL_VISOR is not set +# CONFIG_USB_SERIAL_IPAQ is not set +# CONFIG_USB_SERIAL_IR is not set +# CONFIG_USB_SERIAL_EDGEPORT is not set +# CONFIG_USB_SERIAL_EDGEPORT_TI is not set +# CONFIG_USB_SERIAL_F81232 is not set +# CONFIG_USB_SERIAL_F8153X is not set +# CONFIG_USB_SERIAL_GARMIN is not set +# CONFIG_USB_SERIAL_IPW is not set +# CONFIG_USB_SERIAL_IUU is not set +# CONFIG_USB_SERIAL_KEYSPAN_PDA is not set +# CONFIG_USB_SERIAL_KEYSPAN is not set +# CONFIG_USB_SERIAL_KLSI is not set +# CONFIG_USB_SERIAL_KOBIL_SCT is not set +# CONFIG_USB_SERIAL_MCT_U232 is not set +# CONFIG_USB_SERIAL_METRO is not set +# CONFIG_USB_SERIAL_MOS7720 is not set +# CONFIG_USB_SERIAL_MOS7840 is not set +# CONFIG_USB_SERIAL_MXUPORT is not set +# CONFIG_USB_SERIAL_NAVMAN is not set +CONFIG_USB_SERIAL_PL2303=y +# CONFIG_USB_SERIAL_OTI6858 is not set +# CONFIG_USB_SERIAL_QCAUX is not set +# CONFIG_USB_SERIAL_QUALCOMM is not set +# CONFIG_USB_SERIAL_SPCP8X5 is not set +# CONFIG_USB_SERIAL_SAFE is not set +# CONFIG_USB_SERIAL_SIERRAWIRELESS is not set +# CONFIG_USB_SERIAL_SYMBOL is not set +# CONFIG_USB_SERIAL_TI is not set +# CONFIG_USB_SERIAL_CYBERJACK is not set +# CONFIG_USB_SERIAL_OPTION is not set +# CONFIG_USB_SERIAL_OMNINET is not set +# CONFIG_USB_SERIAL_OPTICON is not set +# CONFIG_USB_SERIAL_XSENS_MT is not set +# CONFIG_USB_SERIAL_WISHBONE is not set +# CONFIG_USB_SERIAL_SSU100 is not set +# CONFIG_USB_SERIAL_QT2 is not set +# CONFIG_USB_SERIAL_UPD78F0730 is not set +# CONFIG_USB_SERIAL_DEBUG is not set + +# +# USB Miscellaneous drivers +# +# CONFIG_USB_EMI62 is not set +# CONFIG_USB_EMI26 is not set +# CONFIG_USB_ADUTUX is not set +# CONFIG_USB_SEVSEG is not set +# CONFIG_USB_LEGOTOWER is not set +# CONFIG_USB_LCD is not set +# CONFIG_USB_CYPRESS_CY7C63 is not set +# CONFIG_USB_CYTHERM is not set +# CONFIG_USB_IDMOUSE is not set +# CONFIG_USB_FTDI_ELAN is not set +# CONFIG_USB_APPLEDISPLAY is not set +# CONFIG_APPLE_MFI_FASTCHARGE is not set +# CONFIG_USB_SISUSBVGA is not set +# CONFIG_USB_LD is not set +# CONFIG_USB_TRANCEVIBRATOR is not set +# CONFIG_USB_IOWARRIOR is not set +# CONFIG_USB_TEST is not set +# CONFIG_USB_EHSET_TEST_FIXTURE is not set +# CONFIG_USB_ISIGHTFW is not set +# CONFIG_USB_YUREX is not set +# CONFIG_USB_EZUSB_FX2 is not set +# CONFIG_USB_HUB_USB251XB is not set +# CONFIG_USB_HSIC_USB3503 is not set +# CONFIG_USB_HSIC_USB4604 is not set +# CONFIG_USB_LINK_LAYER_TEST is not set +# CONFIG_USB_CHAOSKEY is not set + +# +# USB Physical Layer drivers +# +# CONFIG_NOP_USB_XCEIV is not set +# CONFIG_USB_GPIO_VBUS is not set +# CONFIG_USB_ISP1301 is not set +# CONFIG_USB_MXS_PHY is not set +CONFIG_USB_ULPI=y +CONFIG_USB_ULPI_VIEWPORT=y +# end of USB Physical Layer drivers + +# CONFIG_USB_GADGET is not set +# CONFIG_TYPEC is not set +CONFIG_USB_ROLE_SWITCH=y +CONFIG_MMC=y +CONFIG_PWRSEQ_EMMC=y +CONFIG_PWRSEQ_SIMPLE=y +CONFIG_MMC_BLOCK=y +CONFIG_MMC_BLOCK_MINORS=256 +# CONFIG_SDIO_UART is not set +# CONFIG_MMC_TEST is not set + +# +# MMC/SD/SDIO Host Controller Drivers +# +# CONFIG_MMC_DEBUG is not set +# CONFIG_MMC_ARMMMCI is not set +CONFIG_MMC_SDHCI=y +CONFIG_MMC_SDHCI_IO_ACCESSORS=y +# CONFIG_MMC_SDHCI_PCI is not set +CONFIG_MMC_SDHCI_PLTFM=y +# CONFIG_MMC_SDHCI_OF_ARASAN is not set +# CONFIG_MMC_SDHCI_OF_ASPEED is not set +# CONFIG_MMC_SDHCI_OF_AT91 is not set +CONFIG_MMC_SDHCI_OF_ESDHC=y +# CONFIG_MMC_SDHCI_OF_DWCMSHC is not set +# CONFIG_MMC_SDHCI_CADENCE is not set +CONFIG_MMC_SDHCI_ESDHC_IMX=y +# CONFIG_MMC_SDHCI_F_SDH30 is not set +# CONFIG_MMC_SDHCI_MILBEAUT is not set +# CONFIG_MMC_MXC is not set +# CONFIG_MMC_TIFM_SD is not set +# CONFIG_MMC_SPI is not set +# CONFIG_MMC_CB710 is not set +# CONFIG_MMC_VIA_SDMMC is not set +# CONFIG_MMC_DW is not set +# CONFIG_MMC_VUB300 is not set +# CONFIG_MMC_USHC is not set +# CONFIG_MMC_USDHI6ROL0 is not set +CONFIG_MMC_CQHCI=y +# CONFIG_MMC_HSQ is not set +# CONFIG_MMC_TOSHIBA_PCI is not set +# CONFIG_MMC_MTK is not set +# CONFIG_MMC_SDHCI_XENON is not set +# CONFIG_MMC_SDHCI_OMAP is not set +# CONFIG_MMC_SDHCI_AM654 is not set +# CONFIG_MEMSTICK is not set +CONFIG_NEW_LEDS=y +CONFIG_LEDS_CLASS=y +# CONFIG_LEDS_CLASS_FLASH is not set +# CONFIG_LEDS_CLASS_MULTICOLOR is not set +# CONFIG_LEDS_BRIGHTNESS_HW_CHANGED is not set + +# +# LED drivers +# +# CONFIG_LEDS_AN30259A is not set +# CONFIG_LEDS_AW2013 is not set +# CONFIG_LEDS_BCM6328 is not set +# CONFIG_LEDS_BCM6358 is not set +# CONFIG_LEDS_CR0014114 is not set +# CONFIG_LEDS_EL15203000 is not set +# CONFIG_LEDS_LM3530 is not set +# CONFIG_LEDS_LM3532 is not set +# CONFIG_LEDS_LM3642 is not set +# CONFIG_LEDS_LM3692X is not set +# CONFIG_LEDS_PCA9532 is not set +CONFIG_LEDS_GPIO=y +# CONFIG_LEDS_LP3944 is not set +# CONFIG_LEDS_LP3952 is not set +# CONFIG_LEDS_LP50XX is not set +# CONFIG_LEDS_LP55XX_COMMON is not set +# CONFIG_LEDS_LP8860 is not set +CONFIG_LEDS_PCA955X=y +CONFIG_LEDS_PCA955X_GPIO=y +# CONFIG_LEDS_PCA963X is not set +# CONFIG_LEDS_DAC124S085 is not set +# CONFIG_LEDS_PWM is not set +# CONFIG_LEDS_REGULATOR is not set +# CONFIG_LEDS_BD2802 is not set +# CONFIG_LEDS_LT3593 is not set +# CONFIG_LEDS_TCA6507 is not set +# CONFIG_LEDS_TLC591XX is not set +# CONFIG_LEDS_LM355x is not set +# CONFIG_LEDS_IS31FL319X is not set +# CONFIG_LEDS_IS31FL32XX is not set + +# +# LED driver for blink(1) USB RGB LED is under Special HID drivers (HID_THINGM) +# +# CONFIG_LEDS_BLINKM is not set +# CONFIG_LEDS_SYSCON is not set +# CONFIG_LEDS_MLXREG is not set +# CONFIG_LEDS_USER is not set +# CONFIG_LEDS_SPI_BYTE is not set +# CONFIG_LEDS_TI_LMU_COMMON is not set + +# +# Flash and Torch LED drivers +# + +# +# LED Triggers +# +CONFIG_LEDS_TRIGGERS=y +# CONFIG_LEDS_TRIGGER_TIMER is not set +# CONFIG_LEDS_TRIGGER_ONESHOT is not set +# CONFIG_LEDS_TRIGGER_HEARTBEAT is not set +# CONFIG_LEDS_TRIGGER_BACKLIGHT is not set +# CONFIG_LEDS_TRIGGER_CPU is not set +# CONFIG_LEDS_TRIGGER_ACTIVITY is not set +# CONFIG_LEDS_TRIGGER_GPIO is not set +# CONFIG_LEDS_TRIGGER_DEFAULT_ON is not set + +# +# iptables trigger is under Netfilter config (LED target) +# +# CONFIG_LEDS_TRIGGER_TRANSIENT is not set +# CONFIG_LEDS_TRIGGER_CAMERA is not set +# CONFIG_LEDS_TRIGGER_PANIC is not set +# CONFIG_LEDS_TRIGGER_NETDEV is not set +# CONFIG_LEDS_TRIGGER_PATTERN is not set +# CONFIG_LEDS_TRIGGER_AUDIO is not set +# CONFIG_ACCESSIBILITY is not set +# CONFIG_INFINIBAND is not set +CONFIG_EDAC_SUPPORT=y +# CONFIG_EDAC is not set +CONFIG_RTC_LIB=y +CONFIG_RTC_CLASS=y +CONFIG_RTC_HCTOSYS=y +CONFIG_RTC_HCTOSYS_DEVICE="rtc0" +CONFIG_RTC_SYSTOHC=y +CONFIG_RTC_SYSTOHC_DEVICE="rtc0" +# CONFIG_RTC_DEBUG is not set +# CONFIG_RTC_NVMEM is not set + +# +# RTC interfaces +# +CONFIG_RTC_INTF_SYSFS=y +CONFIG_RTC_INTF_PROC=y +CONFIG_RTC_INTF_DEV=y +# CONFIG_RTC_INTF_DEV_UIE_EMUL is not set +# CONFIG_RTC_DRV_TEST is not set + +# +# I2C RTC drivers +# +# CONFIG_RTC_DRV_ABB5ZES3 is not set +# CONFIG_RTC_DRV_ABEOZ9 is not set +# CONFIG_RTC_DRV_ABX80X is not set +# CONFIG_RTC_DRV_DS1307 is not set +# CONFIG_RTC_DRV_DS1374 is not set +# CONFIG_RTC_DRV_DS1672 is not set +# CONFIG_RTC_DRV_HYM8563 is not set +# CONFIG_RTC_DRV_MAX6900 is not set +# CONFIG_RTC_DRV_RS5C372 is not set +# CONFIG_RTC_DRV_ISL1208 is not set +# CONFIG_RTC_DRV_ISL12022 is not set +# CONFIG_RTC_DRV_ISL12026 is not set +# CONFIG_RTC_DRV_X1205 is not set +CONFIG_RTC_DRV_PCF8523=y +# CONFIG_RTC_DRV_PCF85063 is not set +# CONFIG_RTC_DRV_PCF85363 is not set +# CONFIG_RTC_DRV_PCF8563 is not set +# CONFIG_RTC_DRV_PCF8583 is not set +# CONFIG_RTC_DRV_M41T80 is not set +# CONFIG_RTC_DRV_BQ32K is not set +# CONFIG_RTC_DRV_S35390A is not set +# CONFIG_RTC_DRV_FM3130 is not set +# CONFIG_RTC_DRV_RX8010 is not set +# CONFIG_RTC_DRV_RX8581 is not set +# CONFIG_RTC_DRV_RX8025 is not set +# CONFIG_RTC_DRV_EM3027 is not set +# CONFIG_RTC_DRV_RV3028 is not set +# CONFIG_RTC_DRV_RV3032 is not set +# CONFIG_RTC_DRV_RV8803 is not set +# CONFIG_RTC_DRV_SD3078 is not set + +# +# SPI RTC drivers +# +# CONFIG_RTC_DRV_M41T93 is not set +# CONFIG_RTC_DRV_M41T94 is not set +# CONFIG_RTC_DRV_DS1302 is not set +# CONFIG_RTC_DRV_DS1305 is not set +# CONFIG_RTC_DRV_DS1343 is not set +# CONFIG_RTC_DRV_DS1347 is not set +# CONFIG_RTC_DRV_DS1390 is not set +# CONFIG_RTC_DRV_MAX6916 is not set +# CONFIG_RTC_DRV_R9701 is not set +# CONFIG_RTC_DRV_RX4581 is not set +# CONFIG_RTC_DRV_RS5C348 is not set +# CONFIG_RTC_DRV_MAX6902 is not set +# CONFIG_RTC_DRV_PCF2123 is not set +# CONFIG_RTC_DRV_MCP795 is not set +CONFIG_RTC_I2C_AND_SPI=y + +# +# SPI and I2C RTC drivers +# +# CONFIG_RTC_DRV_DS3232 is not set +# CONFIG_RTC_DRV_PCF2127 is not set +# CONFIG_RTC_DRV_RV3029C2 is not set +# CONFIG_RTC_DRV_RX6110 is not set + +# +# Platform RTC drivers +# +# CONFIG_RTC_DRV_DS1286 is not set +# CONFIG_RTC_DRV_DS1511 is not set +# CONFIG_RTC_DRV_DS1553 is not set +# CONFIG_RTC_DRV_DS1685_FAMILY is not set +# CONFIG_RTC_DRV_DS1742 is not set +# CONFIG_RTC_DRV_DS2404 is not set +# CONFIG_RTC_DRV_EFI is not set +# CONFIG_RTC_DRV_STK17TA8 is not set +# CONFIG_RTC_DRV_M48T86 is not set +# CONFIG_RTC_DRV_M48T35 is not set +# CONFIG_RTC_DRV_M48T59 is not set +# CONFIG_RTC_DRV_MSM6242 is not set +# CONFIG_RTC_DRV_BQ4802 is not set +# CONFIG_RTC_DRV_RP5C01 is not set +# CONFIG_RTC_DRV_V3020 is not set +# CONFIG_RTC_DRV_ZYNQMP is not set + +# +# on-CPU RTC drivers +# +# CONFIG_RTC_DRV_IMXDI is not set +# CONFIG_RTC_DRV_PL030 is not set +# CONFIG_RTC_DRV_PL031 is not set +# CONFIG_RTC_DRV_CADENCE is not set +# CONFIG_RTC_DRV_FTRTC010 is not set +# CONFIG_RTC_DRV_MXC is not set +# CONFIG_RTC_DRV_MXC_V2 is not set +CONFIG_RTC_DRV_SNVS=y +# CONFIG_RTC_DRV_R7301 is not set + +# +# HID Sensor RTC drivers +# +# CONFIG_RTC_DRV_GOLDFISH is not set +CONFIG_DMADEVICES=y +# CONFIG_DMADEVICES_DEBUG is not set + +# +# DMA Devices +# +CONFIG_DMA_ENGINE=y +CONFIG_DMA_VIRTUAL_CHANNELS=y +CONFIG_DMA_OF=y +# CONFIG_ALTERA_MSGDMA is not set +# CONFIG_AMBA_PL08X is not set +# CONFIG_DW_AXI_DMAC is not set +# CONFIG_FSL_EDMA is not set +# CONFIG_FSL_QDMA is not set +# CONFIG_HISI_DMA is not set +# CONFIG_IMX_DMA is not set +CONFIG_IMX_SDMA=y +# CONFIG_INTEL_IDMA64 is not set +# CONFIG_MV_XOR_V2 is not set +# CONFIG_MXS_DMA is not set +CONFIG_MX3_IPU=y +CONFIG_MX3_IPU_IRQS=4 +# CONFIG_PL330_DMA is not set +# CONFIG_PLX_DMA is not set +# CONFIG_XILINX_DMA is not set +# CONFIG_XILINX_ZYNQMP_DMA is not set +# CONFIG_XILINX_ZYNQMP_DPDMA is not set +# CONFIG_QCOM_HIDMA_MGMT is not set +# CONFIG_QCOM_HIDMA is not set +# CONFIG_DW_DMAC is not set +# CONFIG_DW_DMAC_PCI is not set +# CONFIG_DW_EDMA is not set +# CONFIG_DW_EDMA_PCIE is not set +# CONFIG_SF_PDMA is not set + +# +# DMA Clients +# +# CONFIG_ASYNC_TX_DMA is not set +# CONFIG_DMATEST is not set + +# +# DMABUF options +# +CONFIG_SYNC_FILE=y +# CONFIG_SW_SYNC is not set +# CONFIG_UDMABUF is not set +# CONFIG_DMABUF_MOVE_NOTIFY is not set +# CONFIG_DMABUF_SELFTESTS is not set +CONFIG_DMABUF_HEAPS=y +CONFIG_DMABUF_HEAPS_SYSTEM=y +CONFIG_DMABUF_HEAPS_CMA=y +# end of DMABUF options + +# CONFIG_AUXDISPLAY is not set +# CONFIG_UIO is not set +# CONFIG_VFIO is not set +CONFIG_VIRT_DRIVERS=y +CONFIG_VIRTIO=y +CONFIG_VIRTIO_MENU=y +CONFIG_VIRTIO_PCI=y +CONFIG_VIRTIO_PCI_LEGACY=y +CONFIG_VIRTIO_BALLOON=y +CONFIG_VIRTIO_INPUT=y +CONFIG_VIRTIO_MMIO=y +CONFIG_VIRTIO_MMIO_CMDLINE_DEVICES=y +CONFIG_VIRTIO_DMA_SHARED_BUFFER=y +# CONFIG_VDPA is not set +# CONFIG_VHOST_MENU is not set + +# +# Microsoft Hyper-V guest support +# +# end of Microsoft Hyper-V guest support + +# +# Xen driver support +# +# CONFIG_XEN_BALLOON is not set +# CONFIG_XEN_DEV_EVTCHN is not set +# CONFIG_XEN_BACKEND is not set +# CONFIG_XENFS is not set +# CONFIG_XEN_SYS_HYPERVISOR is not set +# CONFIG_XEN_GNTDEV is not set +# CONFIG_XEN_GRANT_DEV_ALLOC is not set +# CONFIG_XEN_GRANT_DMA_ALLOC is not set +CONFIG_SWIOTLB_XEN=y +# CONFIG_XEN_PVCALLS_FRONTEND is not set +CONFIG_XEN_PRIVCMD=m +CONFIG_XEN_EFI=y +CONFIG_XEN_AUTO_XLATE=y +# end of Xen driver support + +# CONFIG_GREYBUS is not set +CONFIG_STAGING=y +# CONFIG_PRISM2_USB is not set +# CONFIG_COMEDI is not set +# CONFIG_RTL8192U is not set +# CONFIG_RTLLIB is not set +# CONFIG_RTL8723BS is not set +# CONFIG_R8712U is not set +# CONFIG_R8188EU is not set +# CONFIG_RTS5208 is not set +# CONFIG_VT6655 is not set +# CONFIG_VT6656 is not set +# CONFIG_FB_SM750 is not set +CONFIG_STAGING_MEDIA=y +CONFIG_VIDEO_HANTRO=y +CONFIG_VIDEO_HANTRO_IMX8M=y +# CONFIG_VIDEO_ZORAN is not set + +# +# Android +# +CONFIG_ASHMEM=y +# end of Android + +# CONFIG_STAGING_BOARD is not set +# CONFIG_LTE_GDM724X is not set +# CONFIG_GS_FPGABOOT is not set +# CONFIG_UNISYSSPAR is not set +# CONFIG_FB_TFT is not set +# CONFIG_KS7010 is not set +# CONFIG_PI433 is not set + +# +# Gasket devices +# +# CONFIG_STAGING_GASKET_FRAMEWORK is not set +# end of Gasket devices + +# CONFIG_XIL_AXIS_FIFO is not set +# CONFIG_FIELDBUS_DEV is not set +# CONFIG_QLGE is not set +# CONFIG_WIMAX is not set +# CONFIG_WFX is not set +# CONFIG_GOLDFISH is not set +# CONFIG_CHROME_PLATFORMS is not set +# CONFIG_MELLANOX_PLATFORM is not set +CONFIG_HAVE_CLK=y +CONFIG_CLKDEV_LOOKUP=y +CONFIG_HAVE_CLK_PREPARE=y +CONFIG_COMMON_CLK=y +# CONFIG_COMMON_CLK_MAX9485 is not set +# CONFIG_COMMON_CLK_SI5341 is not set +# CONFIG_COMMON_CLK_SI5351 is not set +# CONFIG_COMMON_CLK_SI514 is not set +# CONFIG_COMMON_CLK_SI544 is not set +# CONFIG_COMMON_CLK_SI570 is not set +# CONFIG_COMMON_CLK_CDCE706 is not set +# CONFIG_COMMON_CLK_CDCE925 is not set +# CONFIG_COMMON_CLK_CS2000_CP is not set +# CONFIG_COMMON_CLK_XGENE is not set +# CONFIG_COMMON_CLK_PWM is not set +# CONFIG_COMMON_CLK_VC5 is not set +# CONFIG_COMMON_CLK_FIXED_MMIO is not set +CONFIG_MXC_CLK=y +# CONFIG_CLK_IMX8MM is not set +# CONFIG_CLK_IMX8MN is not set +# CONFIG_CLK_IMX8MP is not set +CONFIG_CLK_IMX8MQ=y +CONFIG_HWSPINLOCK=y + +# +# Clock Source drivers +# +CONFIG_TIMER_OF=y +CONFIG_TIMER_PROBE=y +CONFIG_ARM_ARCH_TIMER=y +CONFIG_ARM_ARCH_TIMER_EVTSTREAM=y +CONFIG_ARM_ARCH_TIMER_OOL_WORKAROUND=y +CONFIG_FSL_ERRATUM_A008585=y +# CONFIG_HISILICON_ERRATUM_161010101 is not set +CONFIG_ARM64_ERRATUM_858921=y +CONFIG_TIMER_IMX_SYS_CTR=y +# CONFIG_MICROCHIP_PIT64B is not set +# end of Clock Source drivers + +CONFIG_MAILBOX=y +# CONFIG_ARM_MHU is not set +# CONFIG_ARM_MHU_V2 is not set +CONFIG_IMX_MBOX=y +# CONFIG_PLATFORM_MHU is not set +# CONFIG_PL320_MBOX is not set +# CONFIG_ALTERA_MBOX is not set +# CONFIG_MAILBOX_TEST is not set +CONFIG_IOMMU_IOVA=y +CONFIG_IOMMU_API=y +CONFIG_IOMMU_SUPPORT=y + +# +# Generic IOMMU Pagetable Support +# +CONFIG_IOMMU_IO_PGTABLE=y +CONFIG_IOMMU_IO_PGTABLE_LPAE=y +# CONFIG_IOMMU_IO_PGTABLE_LPAE_SELFTEST is not set +CONFIG_IOMMU_IO_PGTABLE_ARMV7S=y +# CONFIG_IOMMU_IO_PGTABLE_ARMV7S_SELFTEST is not set +# end of Generic IOMMU Pagetable Support + +# CONFIG_IOMMU_DEBUGFS is not set +# CONFIG_IOMMU_DEFAULT_PASSTHROUGH is not set +CONFIG_OF_IOMMU=y +CONFIG_IOMMU_DMA=y +# CONFIG_ARM_SMMU is not set +# CONFIG_ARM_SMMU_V3 is not set +CONFIG_VIRTIO_IOMMU=y + +# +# Remoteproc drivers +# +# CONFIG_REMOTEPROC is not set +# end of Remoteproc drivers + +# +# Rpmsg drivers +# +CONFIG_RPMSG=y +# CONFIG_RPMSG_CHAR is not set +CONFIG_RPMSG_NS=y +# CONFIG_RPMSG_QCOM_GLINK_RPM is not set +CONFIG_RPMSG_VIRTIO=y +# end of Rpmsg drivers + +# CONFIG_SOUNDWIRE is not set + +# +# SOC (System On Chip) specific Drivers +# + +# +# Amlogic SoC drivers +# +# end of Amlogic SoC drivers + +# +# Broadcom SoC drivers +# +# CONFIG_SOC_BRCMSTB is not set +# end of Broadcom SoC drivers + +# +# NXP/Freescale QorIQ SoC drivers +# +# CONFIG_QUICC_ENGINE is not set +CONFIG_FSL_GUTS=y +# CONFIG_FSL_RCPM is not set +# end of NXP/Freescale QorIQ SoC drivers + +# +# i.MX SoC drivers +# +CONFIG_IMX_GPCV2_PM_DOMAINS=y +CONFIG_SOC_IMX8M=y +# end of i.MX SoC drivers + +# +# Enable LiteX SoC Builder specific drivers +# +# CONFIG_LITEX_SOC_CONTROLLER is not set +# end of Enable LiteX SoC Builder specific drivers + +# +# Qualcomm SoC drivers +# +# end of Qualcomm SoC drivers + +# CONFIG_SOC_TI is not set + +# +# Xilinx SoC drivers +# +# CONFIG_XILINX_VCU is not set +# end of Xilinx SoC drivers +# end of SOC (System On Chip) specific Drivers + +CONFIG_PM_DEVFREQ=y + +# +# DEVFREQ Governors +# +CONFIG_DEVFREQ_GOV_SIMPLE_ONDEMAND=y +# CONFIG_DEVFREQ_GOV_PERFORMANCE is not set +# CONFIG_DEVFREQ_GOV_POWERSAVE is not set +CONFIG_DEVFREQ_GOV_USERSPACE=y +# CONFIG_DEVFREQ_GOV_PASSIVE is not set + +# +# DEVFREQ Drivers +# +# CONFIG_ARM_IMX_BUS_DEVFREQ is not set +# CONFIG_ARM_IMX8M_DDRC_DEVFREQ is not set +# CONFIG_PM_DEVFREQ_EVENT is not set +# CONFIG_EXTCON is not set +# CONFIG_MEMORY is not set +# CONFIG_IIO is not set +# CONFIG_NTB is not set +# CONFIG_VME_BUS is not set +CONFIG_PWM=y +CONFIG_PWM_SYSFS=y +# CONFIG_PWM_DEBUG is not set +# CONFIG_PWM_ATMEL_TCB is not set +# CONFIG_PWM_DWC is not set +# CONFIG_PWM_FSL_FTM is not set +# CONFIG_PWM_IMX1 is not set +CONFIG_PWM_IMX27=y +# CONFIG_PWM_IMX_TPM is not set +# CONFIG_PWM_PCA9685 is not set + +# +# IRQ chip support +# +CONFIG_IRQCHIP=y +CONFIG_ARM_GIC=y +CONFIG_ARM_GIC_MAX_NR=1 +CONFIG_ARM_GIC_V2M=y +CONFIG_ARM_GIC_V3=y +CONFIG_ARM_GIC_V3_ITS=y +CONFIG_ARM_GIC_V3_ITS_PCI=y +# CONFIG_AL_FIC is not set +CONFIG_IMX_GPCV2=y +CONFIG_PARTITION_PERCPU=y +CONFIG_IMX_IRQSTEER=y +CONFIG_IMX_INTMUX=y +# end of IRQ chip support + +# CONFIG_IPACK_BUS is not set +CONFIG_RESET_CONTROLLER=y +# CONFIG_RESET_BRCMSTB_RESCAL is not set +CONFIG_RESET_IMX7=y +# CONFIG_RESET_INTEL_GW is not set +# CONFIG_RESET_TI_SYSCON is not set + +# +# PHY Subsystem +# +CONFIG_GENERIC_PHY=y +CONFIG_GENERIC_PHY_MIPI_DPHY=y +# CONFIG_PHY_XGENE is not set +# CONFIG_USB_LGM_PHY is not set +# CONFIG_BCM_KONA_USB2_PHY is not set +# CONFIG_PHY_CADENCE_TORRENT is not set +# CONFIG_PHY_CADENCE_DPHY is not set +# CONFIG_PHY_CADENCE_SIERRA is not set +# CONFIG_PHY_CADENCE_SALVO is not set +CONFIG_PHY_FSL_IMX8MQ_USB=y +CONFIG_PHY_MIXEL_MIPI_DPHY=y +# CONFIG_PHY_PXA_28NM_HSIC is not set +# CONFIG_PHY_PXA_28NM_USB2 is not set +# CONFIG_PHY_MAPPHONE_MDM6600 is not set +# CONFIG_PHY_OCELOT_SERDES is not set +# CONFIG_PHY_QCOM_USB_HS is not set +# CONFIG_PHY_QCOM_USB_HSIC is not set +# CONFIG_PHY_TUSB1210 is not set +# end of PHY Subsystem + +CONFIG_POWERCAP=y +CONFIG_IDLE_INJECT=y +# CONFIG_MCB is not set + +# +# Performance monitor support +# +# CONFIG_ARM_CCI_PMU is not set +# CONFIG_ARM_CCN is not set +# CONFIG_ARM_CMN is not set +CONFIG_ARM_PMU=y +# CONFIG_ARM_DSU_PMU is not set +CONFIG_FSL_IMX8_DDR_PMU=y +# CONFIG_ARM_SPE_PMU is not set +# end of Performance monitor support + +CONFIG_RAS=y +# CONFIG_USB4 is not set + +# +# Android +# +CONFIG_ANDROID=y +CONFIG_ANDROID_BINDER_IPC=y +CONFIG_ANDROID_BINDERFS=y +CONFIG_ANDROID_BINDER_DEVICES="binder,hwbinder,vndbinder" +# CONFIG_ANDROID_BINDER_IPC_SELFTEST is not set +# end of Android + +# CONFIG_LIBNVDIMM is not set +# CONFIG_DAX is not set +CONFIG_NVMEM=y +CONFIG_NVMEM_SYSFS=y +# CONFIG_NVMEM_IMX_IIM is not set +CONFIG_NVMEM_IMX_OCOTP=y +# CONFIG_NVMEM_SNVS_LPGPR is not set + +# +# HW tracing support +# +# CONFIG_STM is not set +# CONFIG_INTEL_TH is not set +# end of HW tracing support + +# CONFIG_FPGA is not set +# CONFIG_FSI is not set +# CONFIG_TEE is not set +CONFIG_MULTIPLEXER=y + +# +# Multiplexer drivers +# +# CONFIG_MUX_ADG792A is not set +# CONFIG_MUX_ADGS1408 is not set +CONFIG_MUX_GPIO=y +CONFIG_MUX_MMIO=y +# end of Multiplexer drivers + +CONFIG_PM_OPP=y +# CONFIG_SIOX is not set +# CONFIG_SLIMBUS is not set +CONFIG_INTERCONNECT=y +CONFIG_INTERCONNECT_IMX=y +# CONFIG_INTERCONNECT_IMX8MM is not set +# CONFIG_INTERCONNECT_IMX8MN is not set +CONFIG_INTERCONNECT_IMX8MQ=y +# CONFIG_COUNTER is not set +# end of Device Drivers + +# +# File systems +# +CONFIG_DCACHE_WORD_ACCESS=y +CONFIG_VALIDATE_FS_PARSER=y +CONFIG_FS_IOMAP=y +# CONFIG_EXT2_FS is not set +# CONFIG_EXT3_FS is not set +CONFIG_EXT4_FS=y +CONFIG_EXT4_USE_FOR_EXT2=y +CONFIG_EXT4_FS_POSIX_ACL=y +CONFIG_EXT4_FS_SECURITY=y +# CONFIG_EXT4_DEBUG is not set +CONFIG_JBD2=y +# CONFIG_JBD2_DEBUG is not set +CONFIG_FS_MBCACHE=y +# CONFIG_REISERFS_FS is not set +# CONFIG_JFS_FS is not set +# CONFIG_XFS_FS is not set +# CONFIG_GFS2_FS is not set +# CONFIG_BTRFS_FS is not set +# CONFIG_NILFS2_FS is not set +# CONFIG_F2FS_FS is not set +# CONFIG_FS_DAX is not set +CONFIG_FS_POSIX_ACL=y +CONFIG_EXPORTFS=y +CONFIG_EXPORTFS_BLOCK_OPS=y +CONFIG_FILE_LOCKING=y +CONFIG_MANDATORY_FILE_LOCKING=y +# CONFIG_FS_ENCRYPTION is not set +# CONFIG_FS_VERITY is not set +CONFIG_FSNOTIFY=y +CONFIG_DNOTIFY=y +CONFIG_INOTIFY_USER=y +CONFIG_FANOTIFY=y +# CONFIG_FANOTIFY_ACCESS_PERMISSIONS is not set +CONFIG_QUOTA=y +CONFIG_QUOTA_NETLINK_INTERFACE=y +CONFIG_PRINT_QUOTA_WARNING=y +# CONFIG_QUOTA_DEBUG is not set +# CONFIG_QFMT_V1 is not set +# CONFIG_QFMT_V2 is not set +CONFIG_QUOTACTL=y +# CONFIG_AUTOFS4_FS is not set +# CONFIG_AUTOFS_FS is not set +CONFIG_FUSE_FS=y +# CONFIG_CUSE is not set +CONFIG_VIRTIO_FS=y +CONFIG_OVERLAY_FS=y +# CONFIG_OVERLAY_FS_REDIRECT_DIR is not set +CONFIG_OVERLAY_FS_REDIRECT_ALWAYS_FOLLOW=y +# CONFIG_OVERLAY_FS_INDEX is not set +# CONFIG_OVERLAY_FS_XINO_AUTO is not set +# CONFIG_OVERLAY_FS_METACOPY is not set + +# +# Caches +# +CONFIG_FSCACHE=y +CONFIG_FSCACHE_STATS=y +# CONFIG_FSCACHE_HISTOGRAM is not set +# CONFIG_FSCACHE_DEBUG is not set +# CONFIG_FSCACHE_OBJECT_LIST is not set +CONFIG_CACHEFILES=y +# CONFIG_CACHEFILES_DEBUG is not set +# CONFIG_CACHEFILES_HISTOGRAM is not set +# end of Caches + +# +# CD-ROM/DVD Filesystems +# +CONFIG_ISO9660_FS=y +CONFIG_JOLIET=y +CONFIG_ZISOFS=y +CONFIG_UDF_FS=y +# end of CD-ROM/DVD Filesystems + +# +# DOS/FAT/EXFAT/NT Filesystems +# +CONFIG_FAT_FS=y +CONFIG_MSDOS_FS=y +CONFIG_VFAT_FS=y +CONFIG_FAT_DEFAULT_CODEPAGE=437 +CONFIG_FAT_DEFAULT_IOCHARSET="ascii" +CONFIG_FAT_DEFAULT_UTF8=y +CONFIG_EXFAT_FS=y +CONFIG_EXFAT_DEFAULT_IOCHARSET="utf8" +CONFIG_NTFS_FS=y +# CONFIG_NTFS_DEBUG is not set +CONFIG_NTFS_RW=y +# end of DOS/FAT/EXFAT/NT Filesystems + +# +# Pseudo filesystems +# +CONFIG_PROC_FS=y +CONFIG_PROC_KCORE=y +CONFIG_PROC_VMCORE=y +# CONFIG_PROC_VMCORE_DEVICE_DUMP is not set +CONFIG_PROC_SYSCTL=y +CONFIG_PROC_PAGE_MONITOR=y +CONFIG_PROC_CHILDREN=y +CONFIG_KERNFS=y +CONFIG_SYSFS=y +CONFIG_TMPFS=y +CONFIG_TMPFS_POSIX_ACL=y +CONFIG_TMPFS_XATTR=y +# CONFIG_TMPFS_INODE64 is not set +CONFIG_HUGETLBFS=y +CONFIG_HUGETLB_PAGE=y +CONFIG_MEMFD_CREATE=y +CONFIG_ARCH_HAS_GIGANTIC_PAGE=y +# CONFIG_CONFIGFS_FS is not set +# CONFIG_EFIVAR_FS is not set +# end of Pseudo filesystems + +CONFIG_MISC_FILESYSTEMS=y +# CONFIG_ORANGEFS_FS is not set +# CONFIG_ADFS_FS is not set +CONFIG_AFFS_FS=y +# CONFIG_ECRYPT_FS is not set +# CONFIG_HFS_FS is not set +# CONFIG_HFSPLUS_FS is not set +# CONFIG_BEFS_FS is not set +# CONFIG_BFS_FS is not set +# CONFIG_EFS_FS is not set +# CONFIG_CRAMFS is not set +CONFIG_SQUASHFS=y +CONFIG_SQUASHFS_FILE_CACHE=y +# CONFIG_SQUASHFS_FILE_DIRECT is not set +# CONFIG_SQUASHFS_DECOMP_SINGLE is not set +CONFIG_SQUASHFS_DECOMP_MULTI=y +# CONFIG_SQUASHFS_DECOMP_MULTI_PERCPU is not set +CONFIG_SQUASHFS_XATTR=y +CONFIG_SQUASHFS_ZLIB=y +CONFIG_SQUASHFS_LZ4=y +CONFIG_SQUASHFS_LZO=y +CONFIG_SQUASHFS_XZ=y +CONFIG_SQUASHFS_ZSTD=y +# CONFIG_SQUASHFS_4K_DEVBLK_SIZE is not set +# CONFIG_SQUASHFS_EMBEDDED is not set +CONFIG_SQUASHFS_FRAGMENT_CACHE_SIZE=3 +# CONFIG_VXFS_FS is not set +# CONFIG_MINIX_FS is not set +# CONFIG_OMFS_FS is not set +# CONFIG_HPFS_FS is not set +# CONFIG_QNX4FS_FS is not set +# CONFIG_QNX6FS_FS is not set +# CONFIG_ROMFS_FS is not set +CONFIG_PSTORE=y +CONFIG_PSTORE_DEFAULT_KMSG_BYTES=10240 +CONFIG_PSTORE_DEFLATE_COMPRESS=y +# CONFIG_PSTORE_LZO_COMPRESS is not set +# CONFIG_PSTORE_LZ4_COMPRESS is not set +# CONFIG_PSTORE_LZ4HC_COMPRESS is not set +# CONFIG_PSTORE_842_COMPRESS is not set +# CONFIG_PSTORE_ZSTD_COMPRESS is not set +CONFIG_PSTORE_COMPRESS=y +CONFIG_PSTORE_DEFLATE_COMPRESS_DEFAULT=y +CONFIG_PSTORE_COMPRESS_DEFAULT="deflate" +# CONFIG_PSTORE_CONSOLE is not set +# CONFIG_PSTORE_PMSG is not set +# CONFIG_PSTORE_FTRACE is not set +# CONFIG_PSTORE_RAM is not set +# CONFIG_PSTORE_BLK is not set +# CONFIG_SYSV_FS is not set +# CONFIG_UFS_FS is not set +# CONFIG_EROFS_FS is not set +CONFIG_NETWORK_FILESYSTEMS=y +# CONFIG_NFS_FS is not set +# CONFIG_NFSD is not set +# CONFIG_CEPH_FS is not set +# CONFIG_CIFS is not set +# CONFIG_CODA_FS is not set +# CONFIG_AFS_FS is not set +CONFIG_NLS=y +CONFIG_NLS_DEFAULT="utf8" +CONFIG_NLS_CODEPAGE_437=y +CONFIG_NLS_CODEPAGE_737=y +CONFIG_NLS_CODEPAGE_775=y +CONFIG_NLS_CODEPAGE_850=y +CONFIG_NLS_CODEPAGE_852=y +CONFIG_NLS_CODEPAGE_855=y +CONFIG_NLS_CODEPAGE_857=y +CONFIG_NLS_CODEPAGE_860=y +CONFIG_NLS_CODEPAGE_861=y +CONFIG_NLS_CODEPAGE_862=y +CONFIG_NLS_CODEPAGE_863=y +CONFIG_NLS_CODEPAGE_864=y +CONFIG_NLS_CODEPAGE_865=y +CONFIG_NLS_CODEPAGE_866=y +CONFIG_NLS_CODEPAGE_869=y +# CONFIG_NLS_CODEPAGE_936 is not set +# CONFIG_NLS_CODEPAGE_950 is not set +# CONFIG_NLS_CODEPAGE_932 is not set +# CONFIG_NLS_CODEPAGE_949 is not set +# CONFIG_NLS_CODEPAGE_874 is not set +# CONFIG_NLS_ISO8859_8 is not set +CONFIG_NLS_CODEPAGE_1250=y +CONFIG_NLS_CODEPAGE_1251=y +CONFIG_NLS_ASCII=y +CONFIG_NLS_ISO8859_1=y +# CONFIG_NLS_ISO8859_2 is not set +# CONFIG_NLS_ISO8859_3 is not set +# CONFIG_NLS_ISO8859_4 is not set +# CONFIG_NLS_ISO8859_5 is not set +# CONFIG_NLS_ISO8859_6 is not set +# CONFIG_NLS_ISO8859_7 is not set +# CONFIG_NLS_ISO8859_9 is not set +# CONFIG_NLS_ISO8859_13 is not set +# CONFIG_NLS_ISO8859_14 is not set +# CONFIG_NLS_ISO8859_15 is not set +# CONFIG_NLS_KOI8_R is not set +# CONFIG_NLS_KOI8_U is not set +# CONFIG_NLS_MAC_ROMAN is not set +# CONFIG_NLS_MAC_CELTIC is not set +# CONFIG_NLS_MAC_CENTEURO is not set +# CONFIG_NLS_MAC_CROATIAN is not set +# CONFIG_NLS_MAC_CYRILLIC is not set +# CONFIG_NLS_MAC_GAELIC is not set +# CONFIG_NLS_MAC_GREEK is not set +# CONFIG_NLS_MAC_ICELAND is not set +# CONFIG_NLS_MAC_INUIT is not set +# CONFIG_NLS_MAC_ROMANIAN is not set +# CONFIG_NLS_MAC_TURKISH is not set +CONFIG_NLS_UTF8=y +CONFIG_UNICODE=y +# CONFIG_UNICODE_NORMALIZATION_SELFTEST is not set +CONFIG_IO_WQ=y +# end of File systems + +# +# Security options +# +CONFIG_KEYS=y +# CONFIG_KEYS_REQUEST_CACHE is not set +# CONFIG_PERSISTENT_KEYRINGS is not set +# CONFIG_BIG_KEYS is not set +# CONFIG_ENCRYPTED_KEYS is not set +CONFIG_KEY_DH_OPERATIONS=y +# CONFIG_SECURITY_DMESG_RESTRICT is not set +CONFIG_SECURITY=y +CONFIG_SECURITYFS=y +CONFIG_SECURITY_NETWORK=y +# CONFIG_SECURITY_NETWORK_XFRM is not set +CONFIG_SECURITY_PATH=y +CONFIG_HAVE_HARDENED_USERCOPY_ALLOCATOR=y +CONFIG_HARDENED_USERCOPY=y +# CONFIG_HARDENED_USERCOPY_FALLBACK is not set +# CONFIG_HARDENED_USERCOPY_PAGESPAN is not set +CONFIG_FORTIFY_SOURCE=y +# CONFIG_STATIC_USERMODEHELPER is not set +# CONFIG_SECURITY_SELINUX is not set +# CONFIG_SECURITY_SMACK is not set +# CONFIG_SECURITY_TOMOYO is not set +CONFIG_SECURITY_APPARMOR=y +CONFIG_SECURITY_APPARMOR_HASH=y +CONFIG_SECURITY_APPARMOR_HASH_DEFAULT=y +# CONFIG_SECURITY_APPARMOR_DEBUG is not set +# CONFIG_SECURITY_LOADPIN is not set +# CONFIG_SECURITY_YAMA is not set +# CONFIG_SECURITY_SAFESETID is not set +# CONFIG_SECURITY_LOCKDOWN_LSM is not set +CONFIG_INTEGRITY=y +# CONFIG_INTEGRITY_SIGNATURE is not set +CONFIG_INTEGRITY_AUDIT=y +# CONFIG_IMA is not set +# CONFIG_IMA_SECURE_AND_OR_TRUSTED_BOOT is not set +# CONFIG_EVM is not set +# CONFIG_DEFAULT_SECURITY_APPARMOR is not set +CONFIG_DEFAULT_SECURITY_DAC=y +CONFIG_LSM="loadpin,safesetid,smack,apparmor" + +# +# Kernel hardening options +# + +# +# Memory initialization +# +CONFIG_INIT_STACK_NONE=y +# CONFIG_INIT_ON_ALLOC_DEFAULT_ON is not set +# CONFIG_INIT_ON_FREE_DEFAULT_ON is not set +# end of Memory initialization +# end of Kernel hardening options +# end of Security options + +CONFIG_CRYPTO=y + +# +# Crypto core or helper +# +CONFIG_CRYPTO_FIPS=y +CONFIG_CRYPTO_ALGAPI=y +CONFIG_CRYPTO_ALGAPI2=y +CONFIG_CRYPTO_AEAD=y +CONFIG_CRYPTO_AEAD2=y +CONFIG_CRYPTO_SKCIPHER=y +CONFIG_CRYPTO_SKCIPHER2=y +CONFIG_CRYPTO_HASH=y +CONFIG_CRYPTO_HASH2=y +CONFIG_CRYPTO_RNG=y +CONFIG_CRYPTO_RNG2=y +CONFIG_CRYPTO_RNG_DEFAULT=y +CONFIG_CRYPTO_AKCIPHER2=y +CONFIG_CRYPTO_AKCIPHER=y +CONFIG_CRYPTO_KPP2=y +CONFIG_CRYPTO_KPP=y +CONFIG_CRYPTO_ACOMP2=y +CONFIG_CRYPTO_MANAGER=y +CONFIG_CRYPTO_MANAGER2=y +# CONFIG_CRYPTO_USER is not set +# CONFIG_CRYPTO_MANAGER_DISABLE_TESTS is not set +# CONFIG_CRYPTO_MANAGER_EXTRA_TESTS is not set +CONFIG_CRYPTO_GF128MUL=y +CONFIG_CRYPTO_NULL=y +CONFIG_CRYPTO_NULL2=y +CONFIG_CRYPTO_PCRYPT=y +CONFIG_CRYPTO_CRYPTD=y +CONFIG_CRYPTO_AUTHENC=y +# CONFIG_CRYPTO_TEST is not set +CONFIG_CRYPTO_SIMD=y +CONFIG_CRYPTO_ENGINE=y + +# +# Public-key cryptography +# +CONFIG_CRYPTO_RSA=y +CONFIG_CRYPTO_DH=y +CONFIG_CRYPTO_ECC=y +CONFIG_CRYPTO_ECDH=y +CONFIG_CRYPTO_ECRDSA=y +# CONFIG_CRYPTO_SM2 is not set +CONFIG_CRYPTO_CURVE25519=y + +# +# Authenticated Encryption with Associated Data +# +CONFIG_CRYPTO_CCM=y +CONFIG_CRYPTO_GCM=y +# CONFIG_CRYPTO_CHACHA20POLY1305 is not set +# CONFIG_CRYPTO_AEGIS128 is not set +CONFIG_CRYPTO_SEQIV=y +CONFIG_CRYPTO_ECHAINIV=y + +# +# Block modes +# +CONFIG_CRYPTO_CBC=y +# CONFIG_CRYPTO_CFB is not set +CONFIG_CRYPTO_CTR=y +# CONFIG_CRYPTO_CTS is not set +CONFIG_CRYPTO_ECB=y +# CONFIG_CRYPTO_LRW is not set +# CONFIG_CRYPTO_OFB is not set +# CONFIG_CRYPTO_PCBC is not set +CONFIG_CRYPTO_XTS=y +# CONFIG_CRYPTO_KEYWRAP is not set +# CONFIG_CRYPTO_ADIANTUM is not set +CONFIG_CRYPTO_ESSIV=y + +# +# Hash modes +# +CONFIG_CRYPTO_CMAC=y +CONFIG_CRYPTO_HMAC=y +# CONFIG_CRYPTO_XCBC is not set +# CONFIG_CRYPTO_VMAC is not set + +# +# Digest +# +CONFIG_CRYPTO_CRC32C=y +# CONFIG_CRYPTO_CRC32 is not set +# CONFIG_CRYPTO_XXHASH is not set +# CONFIG_CRYPTO_BLAKE2B is not set +# CONFIG_CRYPTO_BLAKE2S is not set +CONFIG_CRYPTO_CRCT10DIF=y +CONFIG_CRYPTO_GHASH=y +# CONFIG_CRYPTO_POLY1305 is not set +# CONFIG_CRYPTO_MD4 is not set +CONFIG_CRYPTO_MD5=y +# CONFIG_CRYPTO_MICHAEL_MIC is not set +# CONFIG_CRYPTO_RMD128 is not set +# CONFIG_CRYPTO_RMD160 is not set +# CONFIG_CRYPTO_RMD256 is not set +# CONFIG_CRYPTO_RMD320 is not set +CONFIG_CRYPTO_SHA1=y +CONFIG_CRYPTO_SHA256=y +# CONFIG_CRYPTO_SHA512 is not set +CONFIG_CRYPTO_SHA3=y +# CONFIG_CRYPTO_SM3 is not set +CONFIG_CRYPTO_STREEBOG=y +# CONFIG_CRYPTO_TGR192 is not set +# CONFIG_CRYPTO_WP512 is not set + +# +# Ciphers +# +CONFIG_CRYPTO_AES=y +# CONFIG_CRYPTO_AES_TI is not set +# CONFIG_CRYPTO_ANUBIS is not set +CONFIG_CRYPTO_ARC4=y +CONFIG_CRYPTO_BLOWFISH=y +CONFIG_CRYPTO_BLOWFISH_COMMON=y +# CONFIG_CRYPTO_CAMELLIA is not set +# CONFIG_CRYPTO_CAST5 is not set +# CONFIG_CRYPTO_CAST6 is not set +CONFIG_CRYPTO_DES=y +# CONFIG_CRYPTO_FCRYPT is not set +# CONFIG_CRYPTO_KHAZAD is not set +# CONFIG_CRYPTO_SALSA20 is not set +# CONFIG_CRYPTO_CHACHA20 is not set +# CONFIG_CRYPTO_SEED is not set +# CONFIG_CRYPTO_SERPENT is not set +# CONFIG_CRYPTO_SM4 is not set +# CONFIG_CRYPTO_TEA is not set +# CONFIG_CRYPTO_TWOFISH is not set + +# +# Compression +# +CONFIG_CRYPTO_DEFLATE=y +CONFIG_CRYPTO_LZO=y +# CONFIG_CRYPTO_842 is not set +# CONFIG_CRYPTO_LZ4 is not set +# CONFIG_CRYPTO_LZ4HC is not set +# CONFIG_CRYPTO_ZSTD is not set + +# +# Random Number Generation +# +CONFIG_CRYPTO_ANSI_CPRNG=y +CONFIG_CRYPTO_DRBG_MENU=y +CONFIG_CRYPTO_DRBG_HMAC=y +# CONFIG_CRYPTO_DRBG_HASH is not set +# CONFIG_CRYPTO_DRBG_CTR is not set +CONFIG_CRYPTO_DRBG=y +CONFIG_CRYPTO_JITTERENTROPY=y +CONFIG_CRYPTO_USER_API=y +CONFIG_CRYPTO_USER_API_HASH=y +CONFIG_CRYPTO_USER_API_SKCIPHER=y +CONFIG_CRYPTO_USER_API_RNG=y +# CONFIG_CRYPTO_USER_API_RNG_CAVP is not set +CONFIG_CRYPTO_USER_API_AEAD=y +CONFIG_CRYPTO_USER_API_ENABLE_OBSOLETE=y +CONFIG_CRYPTO_HASH_INFO=y + +# +# Crypto library routines +# +CONFIG_CRYPTO_LIB_AES=y +CONFIG_CRYPTO_LIB_ARC4=y +CONFIG_CRYPTO_LIB_BLAKE2S_GENERIC=y +CONFIG_CRYPTO_LIB_BLAKE2S=y +CONFIG_CRYPTO_ARCH_HAVE_LIB_CHACHA=y +CONFIG_CRYPTO_LIB_CHACHA_GENERIC=y +CONFIG_CRYPTO_LIB_CHACHA=y +CONFIG_CRYPTO_LIB_CURVE25519_GENERIC=y +CONFIG_CRYPTO_LIB_CURVE25519=y +CONFIG_CRYPTO_LIB_DES=y +CONFIG_CRYPTO_LIB_POLY1305_RSIZE=9 +CONFIG_CRYPTO_ARCH_HAVE_LIB_POLY1305=y +CONFIG_CRYPTO_LIB_POLY1305=y +CONFIG_CRYPTO_LIB_CHACHA20POLY1305=y +CONFIG_CRYPTO_LIB_SHA256=y +CONFIG_CRYPTO_HW=y +CONFIG_CRYPTO_DEV_FSL_CAAM_COMMON=y +CONFIG_CRYPTO_DEV_FSL_CAAM_CRYPTO_API_DESC=y +CONFIG_CRYPTO_DEV_FSL_CAAM_AHASH_API_DESC=y +CONFIG_CRYPTO_DEV_FSL_CAAM=y +# CONFIG_CRYPTO_DEV_FSL_CAAM_DEBUG is not set +CONFIG_CRYPTO_DEV_FSL_CAAM_JR=y +CONFIG_CRYPTO_DEV_FSL_CAAM_RINGSIZE=9 +# CONFIG_CRYPTO_DEV_FSL_CAAM_INTC is not set +CONFIG_CRYPTO_DEV_FSL_CAAM_CRYPTO_API=y +CONFIG_CRYPTO_DEV_FSL_CAAM_AHASH_API=y +CONFIG_CRYPTO_DEV_FSL_CAAM_PKC_API=y +CONFIG_CRYPTO_DEV_FSL_CAAM_RNG_API=y +# CONFIG_CRYPTO_DEV_SAHARA is not set +# CONFIG_CRYPTO_DEV_ATMEL_ECC is not set +# CONFIG_CRYPTO_DEV_ATMEL_SHA204A is not set +# CONFIG_CRYPTO_DEV_CCP is not set +# CONFIG_CRYPTO_DEV_MXS_DCP is not set +# CONFIG_CRYPTO_DEV_NITROX_CNN55XX is not set +# CONFIG_CRYPTO_DEV_CAVIUM_ZIP is not set +CONFIG_CRYPTO_DEV_VIRTIO=y +# CONFIG_CRYPTO_DEV_SAFEXCEL is not set +# CONFIG_CRYPTO_DEV_CCREE is not set +# CONFIG_CRYPTO_DEV_HISI_SEC is not set +# CONFIG_CRYPTO_DEV_AMLOGIC_GXL is not set +CONFIG_ASYMMETRIC_KEY_TYPE=y +CONFIG_ASYMMETRIC_PUBLIC_KEY_SUBTYPE=y +CONFIG_X509_CERTIFICATE_PARSER=y +# CONFIG_PKCS8_PRIVATE_KEY_PARSER is not set +CONFIG_PKCS7_MESSAGE_PARSER=y +# CONFIG_PKCS7_TEST_KEY is not set +# CONFIG_SIGNED_PE_FILE_VERIFICATION is not set + +# +# Certificates for signature checking +# +CONFIG_MODULE_SIG_KEY="" +CONFIG_SYSTEM_TRUSTED_KEYRING=y +CONFIG_SYSTEM_TRUSTED_KEYS="" +# CONFIG_SYSTEM_EXTRA_CERTIFICATE is not set +# CONFIG_SECONDARY_TRUSTED_KEYRING is not set +# CONFIG_SYSTEM_BLACKLIST_KEYRING is not set +# end of Certificates for signature checking + +CONFIG_BINARY_PRINTF=y + +# +# Library routines +# +CONFIG_LINEAR_RANGES=y +# CONFIG_PACKING is not set +CONFIG_BITREVERSE=y +CONFIG_HAVE_ARCH_BITREVERSE=y +CONFIG_GENERIC_STRNCPY_FROM_USER=y +CONFIG_GENERIC_STRNLEN_USER=y +CONFIG_GENERIC_NET_UTILS=y +CONFIG_CORDIC=y +# CONFIG_PRIME_NUMBERS is not set +CONFIG_RATIONAL=y +CONFIG_GENERIC_PCI_IOMAP=y +CONFIG_ARCH_USE_CMPXCHG_LOCKREF=y +CONFIG_ARCH_HAS_FAST_MULTIPLIER=y +CONFIG_ARCH_USE_SYM_ANNOTATIONS=y +# CONFIG_INDIRECT_PIO is not set +# CONFIG_CRC_CCITT is not set +CONFIG_CRC16=y +CONFIG_CRC_T10DIF=y +CONFIG_CRC_ITU_T=y +CONFIG_CRC32=y +# CONFIG_CRC32_SELFTEST is not set +CONFIG_CRC32_SLICEBY8=y +# CONFIG_CRC32_SLICEBY4 is not set +# CONFIG_CRC32_SARWATE is not set +# CONFIG_CRC32_BIT is not set +# CONFIG_CRC64 is not set +# CONFIG_CRC4 is not set +# CONFIG_CRC7 is not set +CONFIG_LIBCRC32C=y +# CONFIG_CRC8 is not set +CONFIG_XXHASH=y +CONFIG_AUDIT_GENERIC=y +CONFIG_AUDIT_ARCH_COMPAT_GENERIC=y +CONFIG_AUDIT_COMPAT_GENERIC=y +# CONFIG_RANDOM32_SELFTEST is not set +CONFIG_ZLIB_INFLATE=y +CONFIG_ZLIB_DEFLATE=y +CONFIG_LZO_COMPRESS=y +CONFIG_LZO_DECOMPRESS=y +CONFIG_LZ4_DECOMPRESS=y +CONFIG_ZSTD_DECOMPRESS=y +CONFIG_XZ_DEC=y +# CONFIG_XZ_DEC_X86 is not set +# CONFIG_XZ_DEC_POWERPC is not set +# CONFIG_XZ_DEC_IA64 is not set +# CONFIG_XZ_DEC_ARM is not set +# CONFIG_XZ_DEC_ARMTHUMB is not set +# CONFIG_XZ_DEC_SPARC is not set +# CONFIG_XZ_DEC_TEST is not set +CONFIG_DECOMPRESS_GZIP=y +CONFIG_DECOMPRESS_BZIP2=y +CONFIG_DECOMPRESS_LZMA=y +CONFIG_DECOMPRESS_XZ=y +CONFIG_DECOMPRESS_LZO=y +CONFIG_DECOMPRESS_LZ4=y +CONFIG_DECOMPRESS_ZSTD=y +CONFIG_GENERIC_ALLOCATOR=y +CONFIG_INTERVAL_TREE=y +CONFIG_XARRAY_MULTI=y +CONFIG_ASSOCIATIVE_ARRAY=y +CONFIG_HAS_IOMEM=y +CONFIG_HAS_IOPORT_MAP=y +CONFIG_HAS_DMA=y +CONFIG_DMA_OPS=y +CONFIG_NEED_SG_DMA_LENGTH=y +CONFIG_NEED_DMA_MAP_STATE=y +CONFIG_ARCH_DMA_ADDR_T_64BIT=y +CONFIG_DMA_DECLARE_COHERENT=y +CONFIG_ARCH_HAS_SETUP_DMA_OPS=y +CONFIG_ARCH_HAS_TEARDOWN_DMA_OPS=y +CONFIG_ARCH_HAS_SYNC_DMA_FOR_DEVICE=y +CONFIG_ARCH_HAS_SYNC_DMA_FOR_CPU=y +CONFIG_ARCH_HAS_DMA_PREP_COHERENT=y +CONFIG_SWIOTLB=y +CONFIG_DMA_NONCOHERENT_MMAP=y +CONFIG_DMA_COHERENT_POOL=y +CONFIG_DMA_REMAP=y +CONFIG_DMA_DIRECT_REMAP=y +CONFIG_DMA_CMA=y +CONFIG_DMA_PERNUMA_CMA=y + +# +# Default contiguous memory area size: +# +CONFIG_CMA_SIZE_MBYTES=512 +CONFIG_CMA_SIZE_SEL_MBYTES=y +# CONFIG_CMA_SIZE_SEL_PERCENTAGE is not set +# CONFIG_CMA_SIZE_SEL_MIN is not set +# CONFIG_CMA_SIZE_SEL_MAX is not set +CONFIG_CMA_ALIGNMENT=8 +# CONFIG_DMA_API_DEBUG is not set +# CONFIG_DMA_MAP_BENCHMARK is not set +CONFIG_SGL_ALLOC=y +CONFIG_CPU_RMAP=y +CONFIG_DQL=y +CONFIG_GLOB=y +# CONFIG_GLOB_SELFTEST is not set +CONFIG_NLATTR=y +CONFIG_CLZ_TAB=y +CONFIG_IRQ_POLL=y +CONFIG_MPILIB=y +CONFIG_LIBFDT=y +CONFIG_OID_REGISTRY=y +CONFIG_UCS2_STRING=y +CONFIG_HAVE_GENERIC_VDSO=y +CONFIG_GENERIC_GETTIMEOFDAY=y +CONFIG_GENERIC_VDSO_TIME_NS=y +CONFIG_FONT_SUPPORT=y +# CONFIG_FONTS is not set +CONFIG_FONT_8x8=y +CONFIG_FONT_8x16=y +CONFIG_SG_POOL=y +CONFIG_ARCH_STACKWALK=y +CONFIG_SBITMAP=y +# CONFIG_STRING_SELFTEST is not set +# end of Library routines + +CONFIG_GENERIC_LIB_DEVMEM_IS_ALLOWED=y + +# +# Kernel hacking +# + +# +# printk and dmesg options +# +CONFIG_PRINTK_TIME=y +# CONFIG_PRINTK_CALLER is not set +CONFIG_CONSOLE_LOGLEVEL_DEFAULT=7 +CONFIG_CONSOLE_LOGLEVEL_QUIET=4 +CONFIG_MESSAGE_LOGLEVEL_DEFAULT=4 +CONFIG_BOOT_PRINTK_DELAY=y +CONFIG_DYNAMIC_DEBUG=y +CONFIG_DYNAMIC_DEBUG_CORE=y +CONFIG_SYMBOLIC_ERRNAME=y +CONFIG_DEBUG_BUGVERBOSE=y +# end of printk and dmesg options + +# +# Compile-time checks and compiler options +# +CONFIG_DEBUG_INFO=y +# CONFIG_DEBUG_INFO_REDUCED is not set +# CONFIG_DEBUG_INFO_COMPRESSED is not set +# CONFIG_DEBUG_INFO_SPLIT is not set +# CONFIG_DEBUG_INFO_DWARF4 is not set +# CONFIG_DEBUG_INFO_BTF is not set +# CONFIG_GDB_SCRIPTS is not set +CONFIG_FRAME_WARN=2048 +CONFIG_STRIP_ASM_SYMS=y +# CONFIG_READABLE_ASM is not set +# CONFIG_HEADERS_INSTALL is not set +# CONFIG_DEBUG_SECTION_MISMATCH is not set +CONFIG_SECTION_MISMATCH_WARN_ONLY=y +# CONFIG_DEBUG_FORCE_FUNCTION_ALIGN_32B is not set +CONFIG_ARCH_WANT_FRAME_POINTERS=y +CONFIG_FRAME_POINTER=y +# CONFIG_DEBUG_FORCE_WEAK_PER_CPU is not set +# end of Compile-time checks and compiler options + +# +# Generic Kernel Debugging Instruments +# +CONFIG_MAGIC_SYSRQ=y +CONFIG_MAGIC_SYSRQ_DEFAULT_ENABLE=0x1 +CONFIG_MAGIC_SYSRQ_SERIAL=y +CONFIG_MAGIC_SYSRQ_SERIAL_SEQUENCE="" +CONFIG_DEBUG_FS=y +CONFIG_DEBUG_FS_ALLOW_ALL=y +# CONFIG_DEBUG_FS_DISALLOW_MOUNT is not set +# CONFIG_DEBUG_FS_ALLOW_NONE is not set +CONFIG_HAVE_ARCH_KGDB=y +CONFIG_KGDB=y +CONFIG_KGDB_HONOUR_BLOCKLIST=y +CONFIG_KGDB_SERIAL_CONSOLE=y +# CONFIG_KGDB_TESTS is not set +CONFIG_KGDB_KDB=y +CONFIG_KDB_DEFAULT_ENABLE=0x1 +# CONFIG_KDB_KEYBOARD is not set +CONFIG_KDB_CONTINUE_CATASTROPHIC=0 +CONFIG_ARCH_HAS_UBSAN_SANITIZE_ALL=y +# CONFIG_UBSAN is not set +# end of Generic Kernel Debugging Instruments + +CONFIG_DEBUG_KERNEL=y +CONFIG_DEBUG_MISC=y + +# +# Memory Debugging +# +CONFIG_PAGE_EXTENSION=y +# CONFIG_DEBUG_PAGEALLOC is not set +# CONFIG_PAGE_OWNER is not set +CONFIG_PAGE_POISONING=y +# CONFIG_DEBUG_PAGE_REF is not set +# CONFIG_DEBUG_RODATA_TEST is not set +CONFIG_ARCH_HAS_DEBUG_WX=y +CONFIG_DEBUG_WX=y +CONFIG_GENERIC_PTDUMP=y +CONFIG_PTDUMP_CORE=y +# CONFIG_PTDUMP_DEBUGFS is not set +# CONFIG_DEBUG_OBJECTS is not set +# CONFIG_SLUB_DEBUG_ON is not set +# CONFIG_SLUB_STATS is not set +CONFIG_HAVE_DEBUG_KMEMLEAK=y +# CONFIG_DEBUG_KMEMLEAK is not set +# CONFIG_DEBUG_STACK_USAGE is not set +CONFIG_SCHED_STACK_END_CHECK=y +CONFIG_ARCH_HAS_DEBUG_VM_PGTABLE=y +# CONFIG_DEBUG_VM is not set +# CONFIG_DEBUG_VM_PGTABLE is not set +CONFIG_ARCH_HAS_DEBUG_VIRTUAL=y +# CONFIG_DEBUG_VIRTUAL is not set +CONFIG_DEBUG_MEMORY_INIT=y +# CONFIG_DEBUG_PER_CPU_MAPS is not set +CONFIG_HAVE_ARCH_KASAN=y +CONFIG_HAVE_ARCH_KASAN_SW_TAGS=y +CONFIG_HAVE_ARCH_KASAN_HW_TAGS=y +CONFIG_CC_HAS_KASAN_GENERIC=y +CONFIG_CC_HAS_WORKING_NOSANITIZE_ADDRESS=y +# CONFIG_KASAN is not set +# end of Memory Debugging + +# CONFIG_DEBUG_SHIRQ is not set + +# +# Debug Oops, Lockups and Hangs +# +# CONFIG_PANIC_ON_OOPS is not set +CONFIG_PANIC_ON_OOPS_VALUE=0 +CONFIG_PANIC_TIMEOUT=0 +CONFIG_LOCKUP_DETECTOR=y +CONFIG_SOFTLOCKUP_DETECTOR=y +# CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC is not set +CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC_VALUE=0 +CONFIG_DETECT_HUNG_TASK=y +CONFIG_DEFAULT_HUNG_TASK_TIMEOUT=120 +# CONFIG_BOOTPARAM_HUNG_TASK_PANIC is not set +CONFIG_BOOTPARAM_HUNG_TASK_PANIC_VALUE=0 +# CONFIG_WQ_WATCHDOG is not set +# CONFIG_TEST_LOCKUP is not set +# end of Debug Oops, Lockups and Hangs + +# +# Scheduler Debugging +# +CONFIG_SCHED_DEBUG=y +CONFIG_SCHED_INFO=y +CONFIG_SCHEDSTATS=y +# end of Scheduler Debugging + +# CONFIG_DEBUG_TIMEKEEPING is not set +CONFIG_DEBUG_PREEMPT=y + +# +# Lock Debugging (spinlocks, mutexes, etc...) +# +CONFIG_LOCK_DEBUGGING_SUPPORT=y +# CONFIG_PROVE_LOCKING is not set +# CONFIG_LOCK_STAT is not set +# CONFIG_DEBUG_RT_MUTEXES is not set +# CONFIG_DEBUG_SPINLOCK is not set +# CONFIG_DEBUG_MUTEXES is not set +# CONFIG_DEBUG_WW_MUTEX_SLOWPATH is not set +# CONFIG_DEBUG_RWSEMS is not set +# CONFIG_DEBUG_LOCK_ALLOC is not set +# CONFIG_DEBUG_ATOMIC_SLEEP is not set +# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set +# CONFIG_LOCK_TORTURE_TEST is not set +# CONFIG_WW_MUTEX_SELFTEST is not set +# CONFIG_SCF_TORTURE_TEST is not set +# CONFIG_CSD_LOCK_WAIT_DEBUG is not set +# end of Lock Debugging (spinlocks, mutexes, etc...) + +CONFIG_STACKTRACE=y +# CONFIG_WARN_ALL_UNSEEDED_RANDOM is not set +# CONFIG_DEBUG_KOBJECT is not set +CONFIG_HAVE_DEBUG_BUGVERBOSE=y + +# +# Debug kernel data structures +# +CONFIG_DEBUG_LIST=y +# CONFIG_DEBUG_PLIST is not set +# CONFIG_DEBUG_SG is not set +# CONFIG_DEBUG_NOTIFIERS is not set +CONFIG_BUG_ON_DATA_CORRUPTION=y +# end of Debug kernel data structures + +# CONFIG_DEBUG_CREDENTIALS is not set + +# +# RCU Debugging +# +# CONFIG_RCU_SCALE_TEST is not set +# CONFIG_RCU_TORTURE_TEST is not set +# CONFIG_RCU_REF_SCALE_TEST is not set +CONFIG_RCU_CPU_STALL_TIMEOUT=21 +# CONFIG_RCU_TRACE is not set +# CONFIG_RCU_EQS_DEBUG is not set +# end of RCU Debugging + +# CONFIG_DEBUG_WQ_FORCE_RR_CPU is not set +# CONFIG_DEBUG_BLOCK_EXT_DEVT is not set +# CONFIG_CPU_HOTPLUG_STATE_CONTROL is not set +# CONFIG_LATENCYTOP is not set +CONFIG_NOP_TRACER=y +CONFIG_HAVE_FUNCTION_TRACER=y +CONFIG_HAVE_FUNCTION_GRAPH_TRACER=y +CONFIG_HAVE_DYNAMIC_FTRACE=y +CONFIG_HAVE_DYNAMIC_FTRACE_WITH_REGS=y +CONFIG_HAVE_FTRACE_MCOUNT_RECORD=y +CONFIG_HAVE_SYSCALL_TRACEPOINTS=y +CONFIG_HAVE_C_RECORDMCOUNT=y +CONFIG_TRACER_MAX_TRACE=y +CONFIG_TRACE_CLOCK=y +CONFIG_RING_BUFFER=y +CONFIG_EVENT_TRACING=y +CONFIG_CONTEXT_SWITCH_TRACER=y +CONFIG_TRACING=y +CONFIG_GENERIC_TRACER=y +CONFIG_TRACING_SUPPORT=y +CONFIG_FTRACE=y +# CONFIG_BOOTTIME_TRACING is not set +CONFIG_FUNCTION_TRACER=y +CONFIG_FUNCTION_GRAPH_TRACER=y +CONFIG_DYNAMIC_FTRACE=y +CONFIG_DYNAMIC_FTRACE_WITH_REGS=y +# CONFIG_FUNCTION_PROFILER is not set +CONFIG_STACK_TRACER=y +# CONFIG_IRQSOFF_TRACER is not set +# CONFIG_PREEMPT_TRACER is not set +# CONFIG_SCHED_TRACER is not set +# CONFIG_HWLAT_TRACER is not set +CONFIG_FTRACE_SYSCALLS=y +CONFIG_TRACER_SNAPSHOT=y +# CONFIG_TRACER_SNAPSHOT_PER_CPU_SWAP is not set +CONFIG_BRANCH_PROFILE_NONE=y +# CONFIG_PROFILE_ANNOTATED_BRANCHES is not set +CONFIG_BLK_DEV_IO_TRACE=y +CONFIG_KPROBE_EVENTS=y +# CONFIG_KPROBE_EVENTS_ON_NOTRACE is not set +CONFIG_UPROBE_EVENTS=y +CONFIG_BPF_EVENTS=y +CONFIG_DYNAMIC_EVENTS=y +CONFIG_PROBE_EVENTS=y +# CONFIG_BPF_KPROBE_OVERRIDE is not set +CONFIG_FTRACE_MCOUNT_RECORD=y +# CONFIG_SYNTH_EVENTS is not set +# CONFIG_HIST_TRIGGERS is not set +# CONFIG_TRACE_EVENT_INJECT is not set +# CONFIG_TRACEPOINT_BENCHMARK is not set +# CONFIG_RING_BUFFER_BENCHMARK is not set +# CONFIG_TRACE_EVAL_MAP_FILE is not set +# CONFIG_FTRACE_RECORD_RECURSION is not set +# CONFIG_FTRACE_STARTUP_TEST is not set +# CONFIG_RING_BUFFER_STARTUP_TEST is not set +# CONFIG_RING_BUFFER_VALIDATE_TIME_DELTAS is not set +# CONFIG_PREEMPTIRQ_DELAY_TEST is not set +# CONFIG_KPROBE_EVENT_GEN_TEST is not set +# CONFIG_SAMPLES is not set +# CONFIG_STRICT_DEVMEM is not set + +# +# arm64 Debugging +# +# CONFIG_PID_IN_CONTEXTIDR is not set +# CONFIG_DEBUG_EFI is not set +# CONFIG_ARM64_RELOC_TEST is not set +# CONFIG_CORESIGHT is not set +# end of arm64 Debugging + +# +# Kernel Testing and Coverage +# +# CONFIG_KUNIT is not set +# CONFIG_NOTIFIER_ERROR_INJECTION is not set +CONFIG_FUNCTION_ERROR_INJECTION=y +# CONFIG_FAULT_INJECTION is not set +CONFIG_ARCH_HAS_KCOV=y +CONFIG_CC_HAS_SANCOV_TRACE_PC=y +# CONFIG_KCOV is not set +# CONFIG_RUNTIME_TESTING_MENU is not set +CONFIG_MEMTEST=y +# end of Kernel Testing and Coverage +# end of Kernel hacking diff --git a/src/make_kernel.sh b/src/make_kernel.sh new file mode 100755 index 0000000..2f52094 --- /dev/null +++ b/src/make_kernel.sh @@ -0,0 +1,73 @@ +#!/bin/bash + +set -e + +function usage { + + cat < + + : kernel version to compile. This argument is not require if you +define KERNEL_VERSION environment variable. +EOF + +} + +function error { + >&2 printf "\e[31mE\e[0m %s\n" "$1" +} + +export ARCH=arm64 +#export LOADADDR=0x40480000 +export CROSS_COMPILE=aarch64-linux-gnu- +GIT_URL="https://github.com/torvalds/linux/" + +if [ ! -z $1 ] +then + KERNEL_VERSION="$1" +fi + +if [ -z "$KERNEL_VERSION" ] +then + error "You need to define KERNEL_VERSION env variable" + usage + exit 10 +fi + +if [ ! -d linux ] +then + printf "Cloning Linux...\n" + # temporary linux 5.11rc7 commit + if ! git clone --depth 1 --branch=v${KERNEL_VERSION} $GIT_URL + then + error "Can't clone Linux, check version" + exit 11 + fi +fi + +cp ./dts/*.dts ./linux/arch/arm64/boot/dts/freescale/ +cp ./kernel-config ./linux/.config + +cd linux + +for PATCHFILE in ../patches/*.patch +do + printf "Apply patch %s\n" $PATCHFILE + if git apply --check $PATCHFILE + then + git apply $PATCHFILE + else + error "Kernel patch already applied or cannot apply: $PATCHFILE" + fi +done + +make -j$(nproc) Image freescale/imx8mq-mnt-reform2.dtb freescale/imx8mq-mnt-reform2-hdmi.dtb +cd .. + +exit 0 diff --git a/src/patches/0001-nwl-dsi-fixup-mode-only-for-LCDIF-input-not-DCSS.patch b/src/patches/0001-nwl-dsi-fixup-mode-only-for-LCDIF-input-not-DCSS.patch new file mode 100644 index 0000000..bb9b5bd --- /dev/null +++ b/src/patches/0001-nwl-dsi-fixup-mode-only-for-LCDIF-input-not-DCSS.patch @@ -0,0 +1,37 @@ +From 7443b914832c05cfe3707555b7d1ca1f3c6d7783 Mon Sep 17 00:00:00 2001 +From: mntmn +Date: Tue, 24 Nov 2020 00:49:16 +0100 +Subject: [PATCH 1/8] nwl-dsi: fixup mode only for LCDIF input, not DCSS + +The inversion of HSYNC and VSYNC should not be done when the input +source is DCSS, or internal display does not work on MNT Reform 2.0. +--- + drivers/gpu/drm/bridge/nwl-dsi.c | 12 +++++++++--- + 1 file changed, 9 insertions(+), 3 deletions(-) + +diff --git a/drivers/gpu/drm/bridge/nwl-dsi.c b/drivers/gpu/drm/bridge/nwl-dsi.c +index 66b67402f..6735ab2a2 100644 +--- a/drivers/gpu/drm/bridge/nwl-dsi.c ++++ b/drivers/gpu/drm/bridge/nwl-dsi.c +@@ -807,9 +807,15 @@ static bool nwl_dsi_bridge_mode_fixup(struct drm_bridge *bridge, + const struct drm_display_mode *mode, + struct drm_display_mode *adjusted_mode) + { +- /* At least LCDIF + NWL needs active high sync */ +- adjusted_mode->flags |= (DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC); +- adjusted_mode->flags &= ~(DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC); ++ struct device_node *remote; ++ struct nwl_dsi *dsi = bridge_to_dsi(bridge); ++ remote = of_graph_get_remote_node(dsi->dev->of_node, 0, ++ NWL_DSI_ENDPOINT_LCDIF); ++ if (remote) { ++ /* At least LCDIF + NWL needs active high sync */ ++ adjusted_mode->flags |= (DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC); ++ adjusted_mode->flags &= ~(DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC); ++ } + + return true; + } +-- +2.28.0 + diff --git a/src/patches/0005-pci-imx6-add-support-for-internal-refclk-imx8mq.patch b/src/patches/0005-pci-imx6-add-support-for-internal-refclk-imx8mq.patch new file mode 100644 index 0000000..4b1bd67 --- /dev/null +++ b/src/patches/0005-pci-imx6-add-support-for-internal-refclk-imx8mq.patch @@ -0,0 +1,99 @@ +From 30d25ce7792fd1aa37e839a513b7fcf7447fd813 Mon Sep 17 00:00:00 2001 +From: mntmn +Date: Tue, 24 Nov 2020 01:01:42 +0100 +Subject: [PATCH 5/8] pci-imx6: add support for internal refclk (imx8mq) + +NXP i.MX8MQ supports feeding an internal refclk to the PCIe root +controller(s). This is required to make use of the first PCIe controller +on the Boundary Devices Nitrogen8M SoM, which is the standard processor +module of MNT Reform 2.0. + +The patch adds a new boolean property "internal_refclk" for the pcie +nodes. + +The actual generation of the clock requires poking a register of ANATOP. +The code for this is taken from the (fsl) vendor kernel. +--- + drivers/pci/controller/dwc/pci-imx6.c | 43 ++++++++++++++++++++++++++- + 1 file changed, 42 insertions(+), 1 deletion(-) + +diff --git a/drivers/pci/controller/dwc/pci-imx6.c b/drivers/pci/controller/dwc/pci-imx6.c +index 5cf1ef12f..2f1ed228d 100644 +--- a/drivers/pci/controller/dwc/pci-imx6.c ++++ b/drivers/pci/controller/dwc/pci-imx6.c +@@ -64,6 +64,7 @@ struct imx6_pcie { + struct dw_pcie *pci; + int reset_gpio; + bool gpio_active_high; ++ bool internal_refclk; + struct clk *pcie_bus; + struct clk *pcie_phy; + struct clk *pcie_inbound_axi; +@@ -609,8 +610,45 @@ static void imx6_pcie_configure_type(struct imx6_pcie *imx6_pcie) + regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR12, mask, val); + } + ++#define IMX8MQ_ANA_PLLOUT_REG 0x74 ++#define IMX8MQ_ANA_PLLOUT_CKE BIT(4) ++#define IMX8MQ_ANA_PLLOUT_SEL_MASK 0xF ++#define IMX8MQ_ANA_PLLOUT_SEL_SYSPLL1 0xB ++#define IMX8MQ_ANA_PLLOUT_DIV_REG 0x7C ++#define IMX8MQ_ANA_PLLOUT_SYSPLL1_DIV 0x7 ++ ++static void imx6_pcie_enable_internal_refclk(void) ++{ ++ uint32_t val; ++ struct device_node* np; ++ void __iomem *base; ++ ++ np = of_find_compatible_node(NULL, NULL, ++ "fsl,imx8mq-anatop"); ++ base = of_iomap(np, 0); ++ WARN_ON(!base); ++ ++ val = readl(base + IMX8MQ_ANA_PLLOUT_REG); ++ val &= ~IMX8MQ_ANA_PLLOUT_SEL_MASK; ++ val |= IMX8MQ_ANA_PLLOUT_SEL_SYSPLL1; ++ writel(val, base + IMX8MQ_ANA_PLLOUT_REG); ++ /* SYS_PLL1 is 800M, PCIE REF CLK is 100M */ ++ val = readl(base + IMX8MQ_ANA_PLLOUT_DIV_REG); ++ val |= IMX8MQ_ANA_PLLOUT_SYSPLL1_DIV; ++ writel(val, base + IMX8MQ_ANA_PLLOUT_DIV_REG); ++ ++ val = readl(base + IMX8MQ_ANA_PLLOUT_REG); ++ val |= IMX8MQ_ANA_PLLOUT_CKE; ++ writel(val, base + IMX8MQ_ANA_PLLOUT_REG); ++ ++ usleep_range(9000,10000); ++} ++ + static void imx6_pcie_init_phy(struct imx6_pcie *imx6_pcie) + { ++ if (imx6_pcie->internal_refclk) ++ imx6_pcie_enable_internal_refclk(); ++ + switch (imx6_pcie->drvdata->variant) { + case IMX8MQ: + /* +@@ -620,7 +658,8 @@ static void imx6_pcie_init_phy(struct imx6_pcie *imx6_pcie) + regmap_update_bits(imx6_pcie->iomuxc_gpr, + imx6_pcie_grp_offset(imx6_pcie), + IMX8MQ_GPR_PCIE_REF_USE_PAD, +- IMX8MQ_GPR_PCIE_REF_USE_PAD); ++ (imx6_pcie->internal_refclk ? ++ 0 : IMX8MQ_GPR_PCIE_REF_USE_PAD)); + break; + case IMX7D: + regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR12, +@@ -1087,6 +1126,8 @@ static int imx6_pcie_probe(struct platform_device *pdev) + if (IS_ERR(imx6_pcie->pcie_aux)) + return dev_err_probe(dev, PTR_ERR(imx6_pcie->pcie_aux), + "pcie_aux clock source missing or invalid\n"); ++ imx6_pcie->internal_refclk = of_property_read_bool(node, ++ "internal-refclk"); + fallthrough; + case IMX7D: + if (dbi_base->start == IMX8MQ_PCIE2_BASE_ADDR) +-- +2.28.0 + diff --git a/src/patches/0009-revert-58074b08c04af1817ab34be986a80279e7267d07-edid.patch b/src/patches/0009-revert-58074b08c04af1817ab34be986a80279e7267d07-edid.patch new file mode 100644 index 0000000..80cdf68 --- /dev/null +++ b/src/patches/0009-revert-58074b08c04af1817ab34be986a80279e7267d07-edid.patch @@ -0,0 +1,52 @@ +diff --git a/drivers/gpu/drm/bridge/ti-sn65dsi86.c b/drivers/gpu/drm/bridge/ti-sn65dsi86.c +index f27306c51e4d..42ac796ac053 100644 +--- a/drivers/gpu/drm/bridge/ti-sn65dsi86.c ++++ b/drivers/gpu/drm/bridge/ti-sn65dsi86.c +@@ -121,7 +121,6 @@ + * @debugfs: Used for managing our debugfs. + * @host_node: Remote DSI node. + * @dsi: Our MIPI DSI source. +- * @edid: Detected EDID of eDP panel. + * @refclk: Our reference clock. + * @panel: Our panel. + * @enable_gpio: The GPIO we toggle to enable the bridge. +@@ -147,7 +146,6 @@ struct ti_sn_bridge { + struct drm_bridge bridge; + struct drm_connector connector; + struct dentry *debugfs; +- struct edid *edid; + struct device_node *host_node; + struct mipi_dsi_device *dsi; + struct clk *refclk; +@@ -269,23 +267,6 @@ connector_to_ti_sn_bridge(struct drm_connector *connector) + static int ti_sn_bridge_connector_get_modes(struct drm_connector *connector) + { + struct ti_sn_bridge *pdata = connector_to_ti_sn_bridge(connector); +- struct edid *edid = pdata->edid; +- int num, ret; +- +- if (!edid) { +- pm_runtime_get_sync(pdata->dev); +- edid = pdata->edid = drm_get_edid(connector, &pdata->aux.ddc); +- pm_runtime_put(pdata->dev); +- } +- +- if (edid && drm_edid_is_valid(edid)) { +- ret = drm_connector_update_edid_property(connector, edid); +- if (!ret) { +- num = drm_add_edid_modes(connector, edid); +- if (num) +- return num; +- } +- } + + return drm_panel_get_modes(pdata->panel, connector); + } +@@ -1306,7 +1287,6 @@ static int ti_sn_bridge_remove(struct i2c_client *client) + if (!pdata) + return -EINVAL; + +- kfree(pdata->edid); + ti_sn_debugfs_remove(pdata); + + of_node_put(pdata->host_node); diff --git a/src/patches/mnt3004-MNT-Reform-imx8mq-add-PHY_27M-clock.patch b/src/patches/mnt3004-MNT-Reform-imx8mq-add-PHY_27M-clock.patch new file mode 100644 index 0000000..f59f39a --- /dev/null +++ b/src/patches/mnt3004-MNT-Reform-imx8mq-add-PHY_27M-clock.patch @@ -0,0 +1,30 @@ +From b9b161fcc88ab6fa0642aa3f533be3e0aac6978b Mon Sep 17 00:00:00 2001 +From: mntmn +Date: Thu, 28 May 2020 22:51:46 +0200 +Subject: [PATCH] MNT Reform: imx8mq: add PHY_27M clock +--- + drivers/clk/imx/clk-imx8mq.c | 8 +++++++- + 1 file changed, 7 insertions(+), 1 deletion(-) + +diff --git a/drivers/clk/imx/clk-imx8mq.c b/drivers/clk/imx/clk-imx8mq.c +index fdc68db68de5..a9e2d2f09864 100644 +--- a/drivers/clk/imx/clk-imx8mq.c ++++ b/drivers/clk/imx/clk-imx8mq.c +@@ -25,7 +25,7 @@ static u32 share_count_sai6; + static u32 share_count_dcss; + static u32 share_count_nand; + +-static const char * const pll_ref_sels[] = { "osc_25m", "osc_27m", "dummy", "dummy", }; ++static const char * const pll_ref_sels[] = { "osc_25m", "osc_27m", "phy_27m", "dummy", }; + static const char * const arm_pll_bypass_sels[] = {"arm_pll", "arm_pll_ref_sel", }; + static const char * const gpu_pll_bypass_sels[] = {"gpu_pll", "gpu_pll_ref_sel", }; + static const char * const vpu_pll_bypass_sels[] = {"vpu_pll", "vpu_pll_ref_sel", }; +@@ -304,6 +304,7 @@ static int imx8mq_clocks_probe(struct platform_device *pdev) + hws[IMX8MQ_CLK_EXT2] = imx_obtain_fixed_clk_hw(np, "clk_ext2"); + hws[IMX8MQ_CLK_EXT3] = imx_obtain_fixed_clk_hw(np, "clk_ext3"); + hws[IMX8MQ_CLK_EXT4] = imx_obtain_fixed_clk_hw(np, "clk_ext4"); ++ hws[IMX8MQ_CLK_PHY_27MHZ] = imx_clk_hw_fixed("phy_27m", 27000000); + + np = of_find_compatible_node(NULL, NULL, "fsl,imx8mq-anatop"); + base = of_iomap(np, 0); + diff --git a/src/patches/mnt3006-MNT-Reform-imx8mq-add-PHY_27M-clock-missing-define.patch b/src/patches/mnt3006-MNT-Reform-imx8mq-add-PHY_27M-clock-missing-define.patch new file mode 100644 index 0000000..0748274 --- /dev/null +++ b/src/patches/mnt3006-MNT-Reform-imx8mq-add-PHY_27M-clock-missing-define.patch @@ -0,0 +1,27 @@ +From 5bbfbc478adc68ae7e9fb1d5b0239d3ba93c8471 Mon Sep 17 00:00:00 2001 +From: mntmn +Date: Thu, 28 May 2020 23:22:18 +0200 +Subject: [PATCH] MNT Reform: imx8mq: add PHY_27M clock: missing define + +--- + include/dt-bindings/clock/imx8mq-clock.h | 5 ++++- + 1 file changed, 4 insertions(+), 1 deletion(-) + +diff --git a/include/dt-bindings/clock/imx8mq-clock.h b/include/dt-bindings/clock/imx8mq-clock.h +index 9b8045d75b8b..29b86c579b40 100644 +--- a/include/dt-bindings/clock/imx8mq-clock.h ++++ b/include/dt-bindings/clock/imx8mq-clock.h +@@ -431,6 +431,9 @@ + + #define IMX8MQ_CLK_A53_CORE 289 + +-#define IMX8MQ_CLK_END 290 ++#define IMX8MQ_CLK_PHY_27MHZ 290 ++ ++#define IMX8MQ_CLK_END 291 ++ + + #endif /* __DT_BINDINGS_CLOCK_IMX8MQ_H */ +-- +2.26.2 + diff --git a/src/patches/mnt4000-limit-fslsai-to-48khz.patch b/src/patches/mnt4000-limit-fslsai-to-48khz.patch new file mode 100644 index 0000000..8faec48 --- /dev/null +++ b/src/patches/mnt4000-limit-fslsai-to-48khz.patch @@ -0,0 +1,15 @@ +diff --git a/sound/soc/fsl/fsl_sai.c b/sound/soc/fsl/fsl_sai.c +index f3d3d20d35d7..449af79e2640 100644 +--- a/sound/soc/fsl/fsl_sai.c ++++ b/sound/soc/fsl/fsl_sai.c +@@ -27,9 +27,7 @@ + FSL_SAI_CSR_FEIE) + + static const unsigned int fsl_sai_rates[] = { +- 8000, 11025, 12000, 16000, 22050, +- 24000, 32000, 44100, 48000, 64000, +- 88200, 96000, 176400, 192000 ++ 48000, 96000, 192000 + }; + + static const struct snd_pcm_hw_constraint_list fsl_sai_rate_constraints = { diff --git a/src/patches/mnt4001-lcdif-fix-pcie-interference.patch b/src/patches/mnt4001-lcdif-fix-pcie-interference.patch new file mode 100644 index 0000000..e083558 --- /dev/null +++ b/src/patches/mnt4001-lcdif-fix-pcie-interference.patch @@ -0,0 +1,58 @@ +diff --git a/drivers/gpu/drm/mxsfb/mxsfb_kms.c b/drivers/gpu/drm/mxsfb/mxsfb_kms.c +index 3e1bb0aefb87..13128b6f2770 100644 +--- a/drivers/gpu/drm/mxsfb/mxsfb_kms.c ++++ b/drivers/gpu/drm/mxsfb/mxsfb_kms.c +@@ -212,7 +212,7 @@ static void mxsfb_crtc_mode_set_nofb(struct mxsfb_drm_private *mxsfb) + + mxsfb_set_formats(mxsfb); + +- clk_set_rate(mxsfb->clk, m->crtc_clock * 1000); ++ clk_set_rate(mxsfb->clk, m->crtc_clock * 660); + + if (mxsfb->bridge && mxsfb->bridge->timings) + bus_flags = mxsfb->bridge->timings->input_bus_flags; +@@ -540,12 +540,44 @@ static const uint64_t mxsfb_modifiers[] = { + * Initialization + */ + ++void imx8mq_pcie_qos_for_lcdif(void) ++{ ++ void __iomem *qosc = ioremap(0x307f0000, 0x2100); ++ // clock and unlock QoSC registers ++ writel(0x0, qosc); ++ writel(0x1, qosc); ++ writel(0x0, qosc+0x60); ++ ++ // limit number of outstanding transactions for PCIe1 ++ writel(0x0, qosc+0x1000); ++ writel(0x1, qosc+0x1000); ++ writel(0x01010100, qosc+0x1050); ++ writel(0x01010100, qosc+0x1060); ++ writel(0x01010100, qosc+0x1070); ++ writel(0x1, qosc+0x1000); ++ ++ // limit number of outstanding transactions for PCIe2 ++ writel(0x0, qosc+0x2000); ++ writel(0x1, qosc+0x2000); ++ writel(0x01010100, qosc+0x2050); ++ writel(0x01010100, qosc+0x2060); ++ writel(0x01010100, qosc+0x2070); ++ writel(0x1, qosc+0x2000); ++ ++ iounmap(qosc); ++} ++ + int mxsfb_kms_init(struct mxsfb_drm_private *mxsfb) + { + struct drm_encoder *encoder = &mxsfb->encoder; + struct drm_crtc *crtc = &mxsfb->crtc; + int ret; + ++ /* ++ FIXME Workaround to fix PCIe interfering with LCDIF refresh (MNT Reform) ++ */ ++ imx8mq_pcie_qos_for_lcdif(); ++ + drm_plane_helper_add(&mxsfb->planes.primary, + &mxsfb_plane_primary_helper_funcs); + ret = drm_universal_plane_init(mxsfb->drm, &mxsfb->planes.primary, 1, diff --git a/src/patches/mnt4002-imx-gpcv2-wake-smccc.patch b/src/patches/mnt4002-imx-gpcv2-wake-smccc.patch new file mode 100644 index 0000000..5de0ec7 --- /dev/null +++ b/src/patches/mnt4002-imx-gpcv2-wake-smccc.patch @@ -0,0 +1,82 @@ +diff --git a/drivers/irqchip/irq-imx-gpcv2.c b/drivers/irqchip/irq-imx-gpcv2.c +index 7031ef44de4f..9cba81b5050d 100644 +--- a/drivers/irqchip/irq-imx-gpcv2.c ++++ b/drivers/irqchip/irq-imx-gpcv2.c +@@ -3,6 +3,7 @@ + * Copyright (C) 2015 Freescale Semiconductor, Inc. + */ + ++#include + #include + #include + #include +@@ -17,6 +18,13 @@ + #define GPC_IMR1_CORE2 0x1c0 + #define GPC_IMR1_CORE3 0x1d0 + ++#define FSL_SIP_GPC 0xC2000000 ++#define FSL_SIP_CONFIG_GPC_MASK 0x00 ++#define FSL_SIP_CONFIG_GPC_UNMASK 0x01 ++#define FSL_SIP_CONFIG_GPC_SET_WAKE 0x02 ++#define FSL_SIP_CONFIG_GPC_PM_DOMAIN 0x03 ++#define FSL_SIP_CONFIG_GPC_SET_AFF 0x04 ++#define FSL_SIP_CONFIG_GPC_CORE_WAKE 0x05 + + struct gpcv2_irqchip_data { + struct raw_spinlock rlock; +@@ -76,12 +84,17 @@ static int imx_gpcv2_irq_set_wake(struct irq_data *d, unsigned int on) + unsigned int idx = d->hwirq / 32; + unsigned long flags; + u32 mask, val; ++ struct arm_smccc_res res; + + raw_spin_lock_irqsave(&cd->rlock, flags); + mask = BIT(d->hwirq % 32); + val = cd->wakeup_sources[idx]; + + cd->wakeup_sources[idx] = on ? (val & ~mask) : (val | mask); ++ ++ // save wakeup config in vendor tf-a ++ arm_smccc_smc(FSL_SIP_GPC, FSL_SIP_CONFIG_GPC_SET_WAKE, d->hwirq, on, 0, 0, 0, 0, &res); ++ + raw_spin_unlock_irqrestore(&cd->rlock, flags); + + /* +@@ -97,6 +110,7 @@ static void imx_gpcv2_irq_unmask(struct irq_data *d) + struct gpcv2_irqchip_data *cd = d->chip_data; + void __iomem *reg; + u32 val; ++ struct arm_smccc_res res; + + raw_spin_lock(&cd->rlock); + reg = gpcv2_idx_to_reg(cd, d->hwirq / 32); +@@ -105,6 +119,10 @@ static void imx_gpcv2_irq_unmask(struct irq_data *d) + writel_relaxed(val, reg); + raw_spin_unlock(&cd->rlock); + ++ // call into vendor tf-a ++ //arm_smccc_smc(FSL_SIP_GPC, FSL_SIP_CONFIG_GPC_UNMASK, ++ // d->hwirq, 0, 0, 0, 0, 0, &res); ++ + irq_chip_unmask_parent(d); + } + +@@ -113,12 +131,18 @@ static void imx_gpcv2_irq_mask(struct irq_data *d) + struct gpcv2_irqchip_data *cd = d->chip_data; + void __iomem *reg; + u32 val; ++ struct arm_smccc_res res; + + raw_spin_lock(&cd->rlock); + reg = gpcv2_idx_to_reg(cd, d->hwirq / 32); + val = readl_relaxed(reg); + val |= BIT(d->hwirq % 32); + writel_relaxed(val, reg); ++ ++ // call into vendor tf-a ++ //arm_smccc_smc(FSL_SIP_GPC, FSL_SIP_CONFIG_GPC_MASK, ++ // d->hwirq, 0, 0, 0, 0, 0, &res); ++ + raw_spin_unlock(&cd->rlock); + + irq_chip_mask_parent(d); diff --git a/src/patches/mnt4003-emmc-clockgate.patch b/src/patches/mnt4003-emmc-clockgate.patch new file mode 100644 index 0000000..01c0e5c --- /dev/null +++ b/src/patches/mnt4003-emmc-clockgate.patch @@ -0,0 +1,21 @@ +diff --git a/drivers/clk/imx/clk-imx8mq.c b/drivers/clk/imx/clk-imx8mq.c +index 779ea69e6..62ba6fb0d 100644 +--- a/drivers/clk/imx/clk-imx8mq.c ++++ b/drivers/clk/imx/clk-imx8mq.c +@@ -364,7 +365,6 @@ static int imx8mq_clocks_probe(struct platform_device *pdev) + hws[IMX8MQ_SYS1_PLL_133M_CG] = imx_clk_hw_gate("sys1_pll_133m_cg", "sys1_pll_out", base + 0x30, 15); + hws[IMX8MQ_SYS1_PLL_160M_CG] = imx_clk_hw_gate("sys1_pll_160m_cg", "sys1_pll_out", base + 0x30, 17); + hws[IMX8MQ_SYS1_PLL_200M_CG] = imx_clk_hw_gate("sys1_pll_200m_cg", "sys1_pll_out", base + 0x30, 19); +- hws[IMX8MQ_SYS1_PLL_266M_CG] = imx_clk_hw_gate("sys1_pll_266m_cg", "sys1_pll_out", base + 0x30, 21); + hws[IMX8MQ_SYS1_PLL_400M_CG] = imx_clk_hw_gate("sys1_pll_400m_cg", "sys1_pll_out", base + 0x30, 23); + hws[IMX8MQ_SYS1_PLL_800M_CG] = imx_clk_hw_gate("sys1_pll_800m_cg", "sys1_pll_out", base + 0x30, 25); + +@@ -374,7 +374,7 @@ static int imx8mq_clocks_probe(struct platform_device *pdev) + hws[IMX8MQ_SYS1_PLL_133M] = imx_clk_hw_fixed_factor("sys1_pll_133m", "sys1_pll_133m_cg", 1, 6); + hws[IMX8MQ_SYS1_PLL_160M] = imx_clk_hw_fixed_factor("sys1_pll_160m", "sys1_pll_160m_cg", 1, 5); + hws[IMX8MQ_SYS1_PLL_200M] = imx_clk_hw_fixed_factor("sys1_pll_200m", "sys1_pll_200m_cg", 1, 4); +- hws[IMX8MQ_SYS1_PLL_266M] = imx_clk_hw_fixed_factor("sys1_pll_266m", "sys1_pll_266m_cg", 1, 3); ++ hws[IMX8MQ_SYS1_PLL_266M] = imx_clk_hw_fixed_factor("sys1_pll_266m", "sys1_pll_out", 1, 3); + hws[IMX8MQ_SYS1_PLL_400M] = imx_clk_hw_fixed_factor("sys1_pll_400m", "sys1_pll_400m_cg", 1, 2); + hws[IMX8MQ_SYS1_PLL_800M] = imx_clk_hw_fixed_factor("sys1_pll_800m", "sys1_pll_800m_cg", 1, 1); + diff --git a/src/patches/mnt5000-imx8mq-import-HDMI-driver-and-make-DCSS-compatible.patch b/src/patches/mnt5000-imx8mq-import-HDMI-driver-and-make-DCSS-compatible.patch new file mode 100644 index 0000000..f6e1272 --- /dev/null +++ b/src/patches/mnt5000-imx8mq-import-HDMI-driver-and-make-DCSS-compatible.patch @@ -0,0 +1,6877 @@ +From ad68506bf8fe69e6da8848c5a592c448d202b389 Mon Sep 17 00:00:00 2001 +From: "Lukas F. Hartmann" +Date: Tue, 23 Feb 2021 19:30:04 +0100 +Subject: [PATCH] MNT Reform: imx8mq: import HDMI driver and make DCSS + compatible with both HDMI and LCDIF + +--- + drivers/gpu/drm/bridge/cadence/Kconfig | 27 + + drivers/gpu/drm/bridge/cadence/Makefile | 10 + + drivers/gpu/drm/bridge/cadence/cdns-dp-core.c | 590 +++++++++ + .../gpu/drm/bridge/cadence/cdns-hdmi-core.c | 688 +++++++++++ + .../gpu/drm/bridge/cadence/cdns-mhdp-audio.c | 393 ++++++ + .../gpu/drm/bridge/cadence/cdns-mhdp-cec.c | 341 ++++++ + .../gpu/drm/bridge/cadence/cdns-mhdp-common.c | 1060 +++++++++++++++++ + .../gpu/drm/bridge/cadence/cdns-mhdp-hdmi.c | 357 ++++++ + drivers/gpu/drm/bridge/cadence/cdns-mhdp.h | 209 ++++ + drivers/gpu/drm/imx/Kconfig | 9 + + drivers/gpu/drm/imx/Makefile | 4 + + drivers/gpu/drm/imx/cdn-mhdp-dp-phy.c | 529 ++++++++ + drivers/gpu/drm/imx/cdn-mhdp-hdmi-phy.c | 777 ++++++++++++ + drivers/gpu/drm/imx/cdn-mhdp-imxdrv.c | 211 ++++ + drivers/gpu/drm/imx/cdn-mhdp-phy.h | 155 +++ + drivers/gpu/drm/imx/cdns-mhdp-imx.h | 75 ++ + drivers/gpu/drm/imx/dcss/dcss-dev.c | 20 +- + drivers/gpu/drm/imx/dcss/dcss-dev.h | 1 + + drivers/gpu/drm/imx/dcss/dcss-drv.c | 95 +- + drivers/gpu/drm/imx/dcss/dcss-dtg.c | 25 +- + drivers/gpu/drm/imx/dcss/dcss-kms.c | 46 +- + drivers/gpu/drm/imx/dcss/dcss-kms.h | 4 +- + include/drm/bridge/cdns-mhdp-cbs.h | 29 + + include/drm/bridge/cdns-mhdp-common.h | 812 +++++++++++++ + 24 files changed, 6424 insertions(+), 43 deletions(-) + create mode 100644 drivers/gpu/drm/bridge/cadence/cdns-dp-core.c + create mode 100644 drivers/gpu/drm/bridge/cadence/cdns-hdmi-core.c + create mode 100644 drivers/gpu/drm/bridge/cadence/cdns-mhdp-audio.c + create mode 100644 drivers/gpu/drm/bridge/cadence/cdns-mhdp-cec.c + create mode 100644 drivers/gpu/drm/bridge/cadence/cdns-mhdp-common.c + create mode 100644 drivers/gpu/drm/bridge/cadence/cdns-mhdp-hdmi.c + create mode 100644 drivers/gpu/drm/bridge/cadence/cdns-mhdp.h + create mode 100644 drivers/gpu/drm/imx/cdn-mhdp-dp-phy.c + create mode 100644 drivers/gpu/drm/imx/cdn-mhdp-hdmi-phy.c + create mode 100644 drivers/gpu/drm/imx/cdn-mhdp-imxdrv.c + create mode 100644 drivers/gpu/drm/imx/cdn-mhdp-phy.h + create mode 100644 drivers/gpu/drm/imx/cdns-mhdp-imx.h + create mode 100644 include/drm/bridge/cdns-mhdp-cbs.h + create mode 100755 include/drm/bridge/cdns-mhdp-common.h + +diff --git a/drivers/gpu/drm/bridge/cadence/Kconfig b/drivers/gpu/drm/bridge/cadence/Kconfig +index ef8c230e0f62..e5204d0f8d3f 100644 +--- a/drivers/gpu/drm/bridge/cadence/Kconfig ++++ b/drivers/gpu/drm/bridge/cadence/Kconfig +@@ -22,3 +22,30 @@ config DRM_CDNS_MHDP8546_J721E + initializes the J721E Display Port and sets up the + clock and data muxes. + endif ++ ++config DRM_CDNS_MHDP ++ tristate "Cadence MHDP COMMON API driver" ++ select DRM_KMS_HELPER ++ select DRM_PANEL_BRIDGE ++ depends on OF ++ help ++ Support Cadence MHDP API library. ++ ++config DRM_CDNS_HDMI ++ tristate "Cadence HDMI DRM driver" ++ depends on DRM_CDNS_MHDP ++ ++config DRM_CDNS_DP ++ tristate "Cadence DP DRM driver" ++ depends on DRM_CDNS_MHDP ++ ++config DRM_CDNS_AUDIO ++ tristate "Cadence MHDP Audio driver" ++ depends on DRM_CDNS_MHDP ++ ++config DRM_CDNS_HDMI_CEC ++ tristate "Cadence MHDP HDMI CEC driver" ++ depends on DRM_CDNS_HDMI ++ select CEC_CORE ++ select CEC_NOTIFIER ++ +diff --git a/drivers/gpu/drm/bridge/cadence/Makefile b/drivers/gpu/drm/bridge/cadence/Makefile +index 8f647991b374..a80daffb4f59 100644 +--- a/drivers/gpu/drm/bridge/cadence/Makefile ++++ b/drivers/gpu/drm/bridge/cadence/Makefile +@@ -2,3 +2,13 @@ + obj-$(CONFIG_DRM_CDNS_MHDP8546) += cdns-mhdp8546.o + cdns-mhdp8546-y := cdns-mhdp8546-core.o + cdns-mhdp8546-$(CONFIG_DRM_CDNS_MHDP8546_J721E) += cdns-mhdp8546-j721e.o ++ ++cdns_mhdp_drmcore-y := cdns-mhdp-common.o cdns-mhdp-hdmi.o ++ ++cdns_mhdp_drmcore-$(CONFIG_DRM_CDNS_HDMI) += cdns-hdmi-core.o ++#cdns_mhdp_drmcore-$(CONFIG_DRM_CDNS_DP) += cdns-dp-core.o ++cdns_mhdp_drmcore-$(CONFIG_DRM_CDNS_AUDIO) += cdns-mhdp-audio.o ++cdns_mhdp_drmcore-$(CONFIG_DRM_CDNS_HDMI_CEC) += cdns-mhdp-cec.o ++ ++obj-$(CONFIG_DRM_CDNS_MHDP) += cdns_mhdp_drmcore.o ++ +diff --git a/drivers/gpu/drm/bridge/cadence/cdns-dp-core.c b/drivers/gpu/drm/bridge/cadence/cdns-dp-core.c +new file mode 100644 +index 000000000000..42e0d94ef0fc +--- /dev/null ++++ b/drivers/gpu/drm/bridge/cadence/cdns-dp-core.c +@@ -0,0 +1,590 @@ ++/* ++ * Cadence Display Port Interface (DP) driver ++ * ++ * Copyright (C) 2019 NXP Semiconductor, Inc. ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License as published by ++ * the Free Software Foundation; either version 2 of the License, or ++ * (at your option) any later version. ++ * ++ */ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++/* ++ * This function only implements native DPDC reads and writes ++ */ ++static ssize_t dp_aux_transfer(struct drm_dp_aux *aux, ++ struct drm_dp_aux_msg *msg) ++{ ++ struct cdns_mhdp_device *mhdp = dev_get_drvdata(aux->dev); ++ bool native = msg->request & (DP_AUX_NATIVE_WRITE & DP_AUX_NATIVE_READ); ++ int ret; ++ ++ /* Ignore address only message */ ++ if ((msg->size == 0) || (msg->buffer == NULL)) { ++ msg->reply = native ? ++ DP_AUX_NATIVE_REPLY_ACK : DP_AUX_I2C_REPLY_ACK; ++ return msg->size; ++ } ++ ++ if (!native) { ++ dev_err(mhdp->dev, "%s: only native messages supported\n", __func__); ++ return -EINVAL; ++ } ++ ++ /* msg sanity check */ ++ if (msg->size > DP_AUX_MAX_PAYLOAD_BYTES) { ++ dev_err(mhdp->dev, "%s: invalid msg: size(%zu), request(%x)\n", ++ __func__, msg->size, (unsigned int)msg->request); ++ return -EINVAL; ++ } ++ ++ if (msg->request == DP_AUX_NATIVE_WRITE) { ++ const u8 *buf = msg->buffer; ++ int i; ++ for (i = 0; i < msg->size; ++i) { ++ ret = cdns_mhdp_dpcd_write(mhdp, ++ msg->address + i, buf[i]); ++ if (!ret) ++ continue; ++ ++ DRM_DEV_ERROR(mhdp->dev, "Failed to write DPCD\n"); ++ ++ return ret; ++ } ++ } ++ ++ if (msg->request == DP_AUX_NATIVE_READ) { ++ ret = cdns_mhdp_dpcd_read(mhdp, msg->address, msg->buffer, msg->size); ++ if (ret < 0) ++ return -EIO; ++ msg->reply = DP_AUX_NATIVE_REPLY_ACK; ++ return msg->size; ++ } ++ return 0; ++} ++ ++static int dp_aux_init(struct cdns_mhdp_device *mhdp, ++ struct device *dev) ++{ ++ int ret; ++ ++ mhdp->dp.aux.name = "imx_dp_aux"; ++ mhdp->dp.aux.dev = dev; ++ mhdp->dp.aux.transfer = dp_aux_transfer; ++ ++ ret = drm_dp_aux_register(&mhdp->dp.aux); ++ ++ return ret; ++} ++ ++static int dp_aux_destroy(struct cdns_mhdp_device *mhdp) ++{ ++ drm_dp_aux_unregister(&mhdp->dp.aux); ++ return 0; ++} ++ ++static void dp_pixel_clk_reset(struct cdns_mhdp_device *mhdp) ++{ ++ u32 val; ++ ++ /* reset pixel clk */ ++ val = cdns_mhdp_reg_read(mhdp, SOURCE_HDTX_CAR); ++ cdns_mhdp_reg_write(mhdp, SOURCE_HDTX_CAR, val & 0xFD); ++ cdns_mhdp_reg_write(mhdp, SOURCE_HDTX_CAR, val); ++} ++ ++static void cdns_dp_mode_set(struct cdns_mhdp_device *mhdp) ++{ ++ u32 lane_mapping = mhdp->lane_mapping; ++ struct drm_dp_link *link = &mhdp->dp.link; ++ char linkid[6]; ++ int ret; ++ ++ cdns_mhdp_plat_call(mhdp, pclk_rate); ++ ++ /* delay for DP FW stable after pixel clock relock */ ++ msleep(50); ++ ++ dp_pixel_clk_reset(mhdp); ++ ++ ret = drm_dp_downstream_id(&mhdp->dp.aux, linkid); ++ if (ret < 0) { ++ DRM_INFO("Failed to Get DP link ID: %d\n", ret); ++ return; ++ } ++ DRM_INFO("DP link id: %s, 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x\n", ++ linkid, linkid[0], linkid[1], linkid[2], linkid[3], linkid[4], ++ linkid[5]); ++ ++ /* Check dp link */ ++ ret = drm_dp_link_probe(&mhdp->dp.aux, link); ++ if (ret < 0) { ++ DRM_INFO("Failed to probe DP link: %d\n", ret); ++ return; ++ } ++ DRM_INFO("DP revision: 0x%x\n", link->revision); ++ DRM_INFO("DP rate: %d Mbps\n", link->rate); ++ DRM_INFO("DP number of lanes: %d\n", link->num_lanes); ++ DRM_INFO("DP capabilities: 0x%lx\n", link->capabilities); ++ ++ /* check the max link rate */ ++ if (link->rate > CDNS_DP_MAX_LINK_RATE) ++ link->rate = CDNS_DP_MAX_LINK_RATE; ++ ++ drm_dp_link_power_up(&mhdp->dp.aux, link); ++ if (ret < 0) { ++ DRM_INFO("Failed to power DP link: %d\n", ret); ++ return; ++ } ++ ++ /* Initialize link rate/num_lanes as panel max link rate/max_num_lanes */ ++ cdns_mhdp_plat_call(mhdp, phy_set); ++ ++ /* Video off */ ++ ret = cdns_mhdp_set_video_status(mhdp, CONTROL_VIDEO_IDLE); ++ if (ret) { ++ DRM_DEV_ERROR(mhdp->dev, "Failed to valid video %d\n", ret); ++ return; ++ } ++ ++ /* Line swaping */ ++ cdns_mhdp_reg_write(mhdp, LANES_CONFIG, 0x00400000 | lane_mapping); ++ ++ /* Set DP host capability */ ++ ret = cdns_mhdp_set_host_cap(mhdp, false); ++ if (ret) { ++ DRM_DEV_ERROR(mhdp->dev, "Failed to set host cap %d\n", ret); ++ return; ++ } ++ ++ ret = cdns_mhdp_config_video(mhdp); ++ if (ret) { ++ DRM_DEV_ERROR(mhdp->dev, "Failed to config video %d\n", ret); ++ return; ++ } ++ ++ return; ++} ++ ++/* ----------------------------------------------------------------------------- ++ * dp TX Setup ++ */ ++static enum drm_connector_status ++cdns_dp_connector_detect(struct drm_connector *connector, bool force) ++{ ++ struct cdns_mhdp_device *mhdp = container_of(connector, ++ struct cdns_mhdp_device, connector.base); ++ u8 hpd = 0xf; ++ ++ hpd = cdns_mhdp_read_hpd(mhdp); ++ if (hpd == 1) ++ /* Cable Connected */ ++ return connector_status_connected; ++ else if (hpd == 0) ++ /* Cable Disconnedted */ ++ return connector_status_disconnected; ++ else { ++ /* Cable status unknown */ ++ DRM_INFO("Unknow cable status, hdp=%u\n", hpd); ++ return connector_status_unknown; ++ } ++} ++ ++static int cdns_dp_connector_get_modes(struct drm_connector *connector) ++{ ++ struct cdns_mhdp_device *mhdp = container_of(connector, ++ struct cdns_mhdp_device, connector.base); ++ int num_modes = 0; ++ struct edid *edid; ++ ++ edid = drm_do_get_edid(&mhdp->connector.base, ++ cdns_mhdp_get_edid_block, mhdp); ++ if (edid) { ++ dev_info(mhdp->dev, "%x,%x,%x,%x,%x,%x,%x,%x\n", ++ edid->header[0], edid->header[1], ++ edid->header[2], edid->header[3], ++ edid->header[4], edid->header[5], ++ edid->header[6], edid->header[7]); ++ drm_connector_update_edid_property(connector, edid); ++ num_modes = drm_add_edid_modes(connector, edid); ++ kfree(edid); ++ } ++ ++ if (num_modes == 0) ++ DRM_ERROR("Invalid edid\n"); ++ return num_modes; ++} ++ ++static const struct drm_connector_funcs cdns_dp_connector_funcs = { ++ .fill_modes = drm_helper_probe_single_connector_modes, ++ .detect = cdns_dp_connector_detect, ++ .destroy = drm_connector_cleanup, ++ .reset = drm_atomic_helper_connector_reset, ++ .atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state, ++ .atomic_destroy_state = drm_atomic_helper_connector_destroy_state, ++}; ++ ++static const struct drm_connector_helper_funcs cdns_dp_connector_helper_funcs = { ++ .get_modes = cdns_dp_connector_get_modes, ++}; ++ ++static int cdns_dp_bridge_attach(struct drm_bridge *bridge) ++{ ++ struct cdns_mhdp_device *mhdp = bridge->driver_private; ++ struct drm_encoder *encoder = bridge->encoder; ++ struct drm_connector *connector = &mhdp->connector.base; ++ ++ connector->interlace_allowed = 1; ++ ++ if (mhdp->is_hpd) ++ connector->polled = DRM_CONNECTOR_POLL_HPD; ++ else ++ connector->polled = DRM_CONNECTOR_POLL_CONNECT | ++ DRM_CONNECTOR_POLL_DISCONNECT; ++ ++ drm_connector_helper_add(connector, &cdns_dp_connector_helper_funcs); ++ ++ drm_connector_init(bridge->dev, connector, &cdns_dp_connector_funcs, ++ DRM_MODE_CONNECTOR_DisplayPort); ++ ++ drm_connector_attach_encoder(connector, encoder); ++ ++ return 0; ++} ++ ++static enum drm_mode_status ++cdns_dp_bridge_mode_valid(struct drm_bridge *bridge, ++ const struct drm_display_mode *mode) ++{ ++ enum drm_mode_status mode_status = MODE_OK; ++ ++ /* We don't support double-clocked modes */ ++ if (mode->flags & DRM_MODE_FLAG_DBLCLK || ++ mode->flags & DRM_MODE_FLAG_INTERLACE) ++ return MODE_BAD; ++ ++ /* MAX support pixel clock rate 594MHz */ ++ if (mode->clock > 594000) ++ return MODE_CLOCK_HIGH; ++ ++ /* 4096x2160 is not supported now */ ++ if (mode->hdisplay > 3840) ++ return MODE_BAD_HVALUE; ++ ++ if (mode->vdisplay > 2160) ++ return MODE_BAD_VVALUE; ++ ++ return mode_status; ++} ++ ++static void cdns_dp_bridge_mode_set(struct drm_bridge *bridge, ++ const struct drm_display_mode *orig_mode, ++ const struct drm_display_mode *mode) ++{ ++ struct cdns_mhdp_device *mhdp = bridge->driver_private; ++ struct drm_display_info *display_info = &mhdp->connector.base.display_info; ++ struct video_info *video = &mhdp->video_info; ++ ++ switch (display_info->bpc) { ++ case 10: ++ video->color_depth = 10; ++ break; ++ case 6: ++ video->color_depth = 6; ++ break; ++ default: ++ video->color_depth = 8; ++ break; ++ } ++ ++ video->color_fmt = PXL_RGB; ++ video->v_sync_polarity = !!(mode->flags & DRM_MODE_FLAG_NVSYNC); ++ video->h_sync_polarity = !!(mode->flags & DRM_MODE_FLAG_NHSYNC); ++ ++ DRM_INFO("Mode: %dx%dp%d\n", mode->hdisplay, mode->vdisplay, mode->clock); ++ memcpy(&mhdp->mode, mode, sizeof(struct drm_display_mode)); ++ ++ mutex_lock(&mhdp->lock); ++ cdns_dp_mode_set(mhdp); ++ mutex_unlock(&mhdp->lock); ++ ++ /* reset force mode set flag */ ++ mhdp->force_mode_set = false; ++} ++ ++static void cdn_dp_bridge_enable(struct drm_bridge *bridge) ++{ ++ struct cdns_mhdp_device *mhdp = bridge->driver_private; ++ int ret; ++ ++ drm_dp_link_power_up(&mhdp->dp.aux, &mhdp->dp.link); ++ ++ /* Link trainning */ ++ ret = cdns_mhdp_train_link(mhdp); ++ if (ret) { ++ DRM_DEV_ERROR(mhdp->dev, "Failed link train %d\n", ret); ++ return; ++ } ++ ++ ret = cdns_mhdp_set_video_status(mhdp, CONTROL_VIDEO_VALID); ++ if (ret) { ++ DRM_DEV_ERROR(mhdp->dev, "Failed to valid video %d\n", ret); ++ return; ++ } ++} ++ ++static void cdn_dp_bridge_disable(struct drm_bridge *bridge) ++{ ++ struct cdns_mhdp_device *mhdp = bridge->driver_private; ++ ++ cdns_mhdp_set_video_status(mhdp, CONTROL_VIDEO_IDLE); ++} ++ ++static const struct drm_bridge_funcs cdns_dp_bridge_funcs = { ++ .attach = cdns_dp_bridge_attach, ++ .enable = cdn_dp_bridge_enable, ++ .disable = cdn_dp_bridge_disable, ++ .mode_set = cdns_dp_bridge_mode_set, ++ .mode_valid = cdns_dp_bridge_mode_valid, ++}; ++ ++static void hotplug_work_func(struct work_struct *work) ++{ ++ struct cdns_mhdp_device *mhdp = container_of(work, ++ struct cdns_mhdp_device, hotplug_work.work); ++ struct drm_connector *connector = &mhdp->connector.base; ++ ++ drm_helper_hpd_irq_event(connector->dev); ++ ++ if (connector->status == connector_status_connected) { ++ /* Cable connedted */ ++ DRM_INFO("HDMI/DP Cable Plug In\n"); ++ enable_irq(mhdp->irq[IRQ_OUT]); ++ } else if (connector->status == connector_status_disconnected) { ++ /* Cable Disconnedted */ ++ DRM_INFO("HDMI/DP Cable Plug Out\n"); ++ /* force mode set for cable replugin to recovery DP video modes */ ++ mhdp->force_mode_set = true; ++ enable_irq(mhdp->irq[IRQ_IN]); ++ } ++} ++ ++static irqreturn_t cdns_dp_irq_thread(int irq, void *data) ++{ ++ struct cdns_mhdp_device *mhdp = data; ++ ++ disable_irq_nosync(irq); ++ ++ mod_delayed_work(system_wq, &mhdp->hotplug_work, ++ msecs_to_jiffies(HOTPLUG_DEBOUNCE_MS)); ++ ++ return IRQ_HANDLED; ++} ++ ++static void cdns_dp_parse_dt(struct cdns_mhdp_device *mhdp) ++{ ++ struct device_node *of_node = mhdp->dev->of_node; ++ int ret; ++ ++ ret = of_property_read_u32(of_node, "lane-mapping", ++ &mhdp->lane_mapping); ++ if (ret) { ++ mhdp->lane_mapping = 0xc6; ++ dev_warn(mhdp->dev, "Failed to get lane_mapping - using default 0xc6\n"); ++ } ++ dev_info(mhdp->dev, "lane-mapping 0x%02x\n", mhdp->lane_mapping); ++} ++ ++static int __cdns_dp_probe(struct platform_device *pdev, ++ struct cdns_mhdp_device *mhdp) ++{ ++ struct device *dev = &pdev->dev; ++ struct resource *iores = NULL; ++ int ret; ++ ++ mutex_init(&mhdp->lock); ++ mutex_init(&mhdp->iolock); ++ ++ INIT_DELAYED_WORK(&mhdp->hotplug_work, hotplug_work_func); ++ ++ iores = platform_get_resource(pdev, IORESOURCE_MEM, 0); ++ if (iores) { ++ mhdp->regs_base = devm_ioremap(dev, iores->start, ++ resource_size(iores)); ++ if (IS_ERR(mhdp->regs_base)) ++ return -ENOMEM; ++ } ++ ++ iores = platform_get_resource(pdev, IORESOURCE_MEM, 1); ++ if (iores) { ++ mhdp->regs_sec = devm_ioremap(dev, iores->start, ++ resource_size(iores)); ++ if (IS_ERR(mhdp->regs_sec)) ++ return -ENOMEM; ++ } ++ ++ mhdp->is_hpd = true; ++ mhdp->is_ls1028a = false; ++ ++ mhdp->irq[IRQ_IN] = platform_get_irq_byname(pdev, "plug_in"); ++ if (mhdp->irq[IRQ_IN] < 0) { ++ mhdp->is_hpd = false; ++ dev_info(dev, "No plug_in irq number\n"); ++ } ++ ++ mhdp->irq[IRQ_OUT] = platform_get_irq_byname(pdev, "plug_out"); ++ if (mhdp->irq[IRQ_OUT] < 0) { ++ mhdp->is_hpd = false; ++ dev_info(dev, "No plug_out irq number\n"); ++ } ++ ++ cdns_dp_parse_dt(mhdp); ++ ++ if (of_device_is_compatible(dev->of_node, "cdn,ls1028a-dp")) ++ mhdp->is_ls1028a = true; ++ ++ cdns_mhdp_plat_call(mhdp, power_on); ++ ++ cdns_mhdp_plat_call(mhdp, firmware_init); ++ ++ /* DP FW alive check */ ++ ret = cdns_mhdp_check_alive(mhdp); ++ if (ret == false) { ++ DRM_ERROR("NO dp FW running\n"); ++ return -ENXIO; ++ } ++ ++ /* DP PHY init before AUX init */ ++ cdns_mhdp_plat_call(mhdp, phy_set); ++ ++ /* Enable Hotplug Detect IRQ thread */ ++ if (mhdp->is_hpd) { ++ irq_set_status_flags(mhdp->irq[IRQ_IN], IRQ_NOAUTOEN); ++ ret = devm_request_threaded_irq(dev, mhdp->irq[IRQ_IN], ++ NULL, cdns_dp_irq_thread, ++ IRQF_ONESHOT, dev_name(dev), ++ mhdp); ++ ++ if (ret) { ++ dev_err(dev, "can't claim irq %d\n", ++ mhdp->irq[IRQ_IN]); ++ return -EINVAL; ++ } ++ ++ irq_set_status_flags(mhdp->irq[IRQ_OUT], IRQ_NOAUTOEN); ++ ret = devm_request_threaded_irq(dev, mhdp->irq[IRQ_OUT], ++ NULL, cdns_dp_irq_thread, ++ IRQF_ONESHOT, dev_name(dev), ++ mhdp); ++ ++ if (ret) { ++ dev_err(dev, "can't claim irq %d\n", ++ mhdp->irq[IRQ_OUT]); ++ return -EINVAL; ++ } ++ ++ if (cdns_mhdp_read_hpd(mhdp)) ++ enable_irq(mhdp->irq[IRQ_OUT]); ++ else ++ enable_irq(mhdp->irq[IRQ_IN]); ++ } ++ ++ mhdp->bridge.base.driver_private = mhdp; ++ mhdp->bridge.base.funcs = &cdns_dp_bridge_funcs; ++#ifdef CONFIG_OF ++ mhdp->bridge.base.of_node = dev->of_node; ++#endif ++ ++ dev_set_drvdata(dev, mhdp); ++ ++ /* register audio driver */ ++ cdns_mhdp_register_audio_driver(dev); ++ ++ dp_aux_init(mhdp, dev); ++ ++ return 0; ++} ++ ++static void __cdns_dp_remove(struct cdns_mhdp_device *mhdp) ++{ ++ dp_aux_destroy(mhdp); ++ cdns_mhdp_unregister_audio_driver(mhdp->dev); ++} ++ ++/* ----------------------------------------------------------------------------- ++ * Probe/remove API, used from platforms based on the DRM bridge API. ++ */ ++int cdns_dp_probe(struct platform_device *pdev, ++ struct cdns_mhdp_device *mhdp) ++{ ++ int ret; ++ ++ ret = __cdns_dp_probe(pdev, mhdp); ++ if (ret) ++ return ret; ++ ++ drm_bridge_add(&mhdp->bridge.base); ++ ++ return 0; ++} ++EXPORT_SYMBOL_GPL(cdns_dp_probe); ++ ++void cdns_dp_remove(struct platform_device *pdev) ++{ ++ struct cdns_mhdp_device *mhdp = platform_get_drvdata(pdev); ++ ++ drm_bridge_remove(&mhdp->bridge.base); ++ ++ __cdns_dp_remove(mhdp); ++} ++EXPORT_SYMBOL_GPL(cdns_dp_remove); ++ ++/* ----------------------------------------------------------------------------- ++ * Bind/unbind API, used from platforms based on the component framework. ++ */ ++int cdns_dp_bind(struct platform_device *pdev, struct drm_encoder *encoder, ++ struct cdns_mhdp_device *mhdp) ++{ ++ int ret; ++ ++ ret = __cdns_dp_probe(pdev, mhdp); ++ if (ret < 0) ++ return ret; ++ ++ ret = drm_bridge_attach(encoder, &mhdp->bridge.base, NULL); ++ if (ret) { ++ cdns_dp_remove(pdev); ++ DRM_ERROR("Failed to initialize bridge with drm\n"); ++ return ret; ++ } ++ ++ return 0; ++} ++EXPORT_SYMBOL_GPL(cdns_dp_bind); ++ ++void cdns_dp_unbind(struct device *dev) ++{ ++ struct cdns_mhdp_device *mhdp = dev_get_drvdata(dev); ++ ++ __cdns_dp_remove(mhdp); ++} ++EXPORT_SYMBOL_GPL(cdns_dp_unbind); ++ ++MODULE_AUTHOR("Sandor Yu "); ++MODULE_DESCRIPTION("Cadence Display Port transmitter driver"); ++MODULE_LICENSE("GPL"); ++MODULE_ALIAS("platform:cdn-dp"); +diff --git a/drivers/gpu/drm/bridge/cadence/cdns-hdmi-core.c b/drivers/gpu/drm/bridge/cadence/cdns-hdmi-core.c +new file mode 100644 +index 000000000000..25e8717795bf +--- /dev/null ++++ b/drivers/gpu/drm/bridge/cadence/cdns-hdmi-core.c +@@ -0,0 +1,688 @@ ++/* ++ * Cadence High-Definition Multimedia Interface (HDMI) driver ++ * ++ * Copyright (C) 2019 NXP Semiconductor, Inc. ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License as published by ++ * the Free Software Foundation; either version 2 of the License, or ++ * (at your option) any later version. ++ * ++ */ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++static void hdmi_sink_config(struct cdns_mhdp_device *mhdp) ++{ ++ struct drm_scdc *scdc = &mhdp->connector.base.display_info.hdmi.scdc; ++ u8 buff = 0; ++ ++ /* Default work in HDMI1.4 */ ++ mhdp->hdmi.hdmi_type = MODE_HDMI_1_4; ++ ++ /* check sink support SCDC or not */ ++ if (scdc->supported != true) { ++ printk(KERN_ALERT "cdns-hdmi-core: Sink Not Support SCDC\n"); ++ return; ++ } ++ ++ if (mhdp->hdmi.char_rate > 340000) { ++ /* ++ * TMDS Character Rate above 340MHz should working in HDMI2.0 ++ * Enable scrambling and TMDS_Bit_Clock_Ratio ++ */ ++ buff = SCDC_TMDS_BIT_CLOCK_RATIO_BY_40 | SCDC_SCRAMBLING_ENABLE; ++ mhdp->hdmi.hdmi_type = MODE_HDMI_2_0; ++ } else if (scdc->scrambling.low_rates) { ++ /* ++ * Enable scrambling and HDMI2.0 when scrambling capability of sink ++ * be indicated in the HF-VSDB LTE_340Mcsc_scramble bit ++ */ ++ buff = SCDC_SCRAMBLING_ENABLE; ++ mhdp->hdmi.hdmi_type = MODE_HDMI_2_0; ++ } ++ ++ /* TMDS config */ ++ cdns_hdmi_scdc_write(mhdp, 0x20, buff); ++} ++ ++static void hdmi_lanes_config(struct cdns_mhdp_device *mhdp) ++{ ++ /* Line swapping */ ++ cdns_mhdp_reg_write(mhdp, LANES_CONFIG, 0x00400000 | mhdp->lane_mapping); ++} ++ ++static int hdmi_avi_info_set(struct cdns_mhdp_device *mhdp, ++ struct drm_display_mode *mode) ++{ ++ struct hdmi_avi_infoframe frame; ++ int format = mhdp->video_info.color_fmt; ++ struct drm_connector_state *conn_state = mhdp->connector.base.state; ++ struct drm_display_mode *adj_mode; ++ enum hdmi_quantization_range qr; ++ u8 buf[32]; ++ int ret; ++ ++ /* Initialise info frame from DRM mode */ ++ drm_hdmi_avi_infoframe_from_display_mode(&frame, &mhdp->connector.base, ++ mode); ++ ++ switch (format) { ++ case YCBCR_4_4_4: ++ frame.colorspace = HDMI_COLORSPACE_YUV444; ++ break; ++ case YCBCR_4_2_2: ++ frame.colorspace = HDMI_COLORSPACE_YUV422; ++ break; ++ case YCBCR_4_2_0: ++ frame.colorspace = HDMI_COLORSPACE_YUV420; ++ break; ++ default: ++ frame.colorspace = HDMI_COLORSPACE_RGB; ++ break; ++ } ++ ++ drm_hdmi_avi_infoframe_colorspace(&frame, conn_state); ++ ++ adj_mode = &mhdp->bridge.base.encoder->crtc->state->adjusted_mode; ++ ++ qr = drm_default_rgb_quant_range(adj_mode); ++ ++ drm_hdmi_avi_infoframe_quant_range(&frame, &mhdp->connector.base, ++ adj_mode, qr); ++ ++ ret = hdmi_avi_infoframe_check(&frame); ++ if (WARN_ON(ret)) ++ return false; ++ ++ ret = hdmi_avi_infoframe_pack(&frame, buf + 1, sizeof(buf) - 1); ++ if (ret < 0) { ++ printk(KERN_ALERT "cdns-hdmi-core: failed to pack AVI infoframe: %d\n", ret); ++ return -1; ++ } ++ ++ buf[0] = 0; ++ cdns_mhdp_infoframe_set(mhdp, 0, sizeof(buf), buf, HDMI_INFOFRAME_TYPE_AVI); ++ return 0; ++} ++ ++static void hdmi_vendor_info_set(struct cdns_mhdp_device *mhdp, ++ struct drm_display_mode *mode) ++{ ++ struct hdmi_vendor_infoframe frame; ++ u8 buf[32]; ++ int ret; ++ ++ /* Initialise vendor frame from DRM mode */ ++ ret = drm_hdmi_vendor_infoframe_from_display_mode(&frame, &mhdp->connector.base, mode); ++ if (ret < 0) { ++ printk(KERN_ALERT "cdns-hdmi-core: No vendor infoframe\n"); ++ return; ++ } ++ ++ ret = hdmi_vendor_infoframe_pack(&frame, buf + 1, sizeof(buf) - 1); ++ if (ret < 0) { ++ printk(KERN_ALERT "cdns-hdmi-core: Unable to pack vendor infoframe: %d\n", ret); ++ return; ++ } ++ ++ buf[0] = 0; ++ cdns_mhdp_infoframe_set(mhdp, 3, sizeof(buf), buf, HDMI_INFOFRAME_TYPE_VENDOR); ++} ++ ++static void hdmi_drm_info_set(struct cdns_mhdp_device *mhdp) ++{ ++ struct drm_connector_state *conn_state; ++ struct hdmi_drm_infoframe frame; ++ u8 buf[32]; ++ int ret; ++ ++ conn_state = mhdp->connector.base.state; ++ ++ if (!conn_state->hdr_output_metadata) ++ return; ++ ++ ret = drm_hdmi_infoframe_set_hdr_metadata(&frame, conn_state); ++ if (ret < 0) { ++ printk(KERN_ALERT "cdns-hdmi-core: couldn't set HDR metadata in infoframe\n"); ++ return; ++ } ++ ++ ret = hdmi_drm_infoframe_pack(&frame, buf + 1, sizeof(buf) - 1); ++ if (ret < 0) { ++ printk(KERN_ALERT "cdns-hdmi-core: couldn't pack HDR infoframe\n"); ++ return; ++ } ++ ++ buf[0] = 0; ++ cdns_mhdp_infoframe_set(mhdp, 3, sizeof(buf), ++ buf, HDMI_INFOFRAME_TYPE_DRM); ++} ++ ++void cdns_hdmi_mode_set(struct cdns_mhdp_device *mhdp) ++{ ++ struct drm_display_mode *mode = &mhdp->mode; ++ int ret; ++ ++ /* video mode valid check */ ++ if (mode->clock == 0 || mode->hdisplay == 0 || mode->vdisplay == 0) ++ return; ++ ++ hdmi_lanes_config(mhdp); ++ ++ cdns_mhdp_plat_call(mhdp, pclk_rate); ++ ++ /* delay for HDMI FW stable after pixel clock relock */ ++ msleep(20); ++ ++ cdns_mhdp_plat_call(mhdp, phy_set); ++ ++ hdmi_sink_config(mhdp); ++ ++ ret = cdns_hdmi_ctrl_init(mhdp, mhdp->hdmi.hdmi_type, mhdp->hdmi.char_rate); ++ if (ret < 0) { ++ printk(KERN_ALERT "cdns-hdmi-core: %s, ret = %d\n", __func__, ret); ++ return; ++ } ++ ++ /* Config GCP */ ++ if (mhdp->video_info.color_depth == 8) ++ cdns_hdmi_disable_gcp(mhdp); ++ else ++ cdns_hdmi_enable_gcp(mhdp); ++ ++ ret = hdmi_avi_info_set(mhdp, mode); ++ if (ret < 0) { ++ printk(KERN_ALERT "cdns-hdmi-core: %s ret = %d\n", __func__, ret); ++ return; ++ } ++ ++ /* vendor info frame is enable only when HDMI1.4 4K mode */ ++ hdmi_vendor_info_set(mhdp, mode); ++ ++ hdmi_drm_info_set(mhdp); ++ ++ ret = cdns_hdmi_mode_config(mhdp, mode, &mhdp->video_info); ++ if (ret < 0) { ++ printk(KERN_ALERT "cdns-hdmi-core: CDN_API_HDMITX_SetVic_blocking ret = %d\n", ret); ++ return; ++ } ++} ++ ++static enum drm_connector_status ++cdns_hdmi_connector_detect(struct drm_connector *connector, bool force) ++{ ++ struct cdns_mhdp_device *mhdp = ++ container_of(connector, struct cdns_mhdp_device, connector.base); ++ ++ u8 hpd = 0xf; ++ ++ hpd = cdns_mhdp_read_hpd(mhdp); ++ ++ if (hpd == 1) ++ /* Cable Connected */ ++ return connector_status_connected; ++ else if (hpd == 0) ++ /* Cable Disconnedted */ ++ return connector_status_disconnected; ++ else { ++ /* Cable status unknown */ ++ printk(KERN_ALERT "cdns-hdmi-core: Unknown cable status, hdp=%u\n", hpd); ++ return connector_status_unknown; ++ } ++} ++ ++static int cdns_hdmi_connector_get_modes(struct drm_connector *connector) ++{ ++ struct cdns_mhdp_device *mhdp = ++ container_of(connector, struct cdns_mhdp_device, connector.base); ++ int num_modes = 0; ++ struct edid *edid; ++ ++ edid = drm_do_get_edid(&mhdp->connector.base, ++ cdns_hdmi_get_edid_block, mhdp); ++ if (edid) { ++ dev_info(mhdp->dev, "%x,%x,%x,%x,%x,%x,%x,%x\n", ++ edid->header[0], edid->header[1], ++ edid->header[2], edid->header[3], ++ edid->header[4], edid->header[5], ++ edid->header[6], edid->header[7]); ++ drm_connector_update_edid_property(connector, edid); ++ num_modes = drm_add_edid_modes(connector, edid); ++ kfree(edid); ++ } ++ ++ if (num_modes == 0) ++ printk(KERN_ALERT "cdns-hdmi-core: Invalid edid\n"); ++ return num_modes; ++} ++ ++static bool blob_equal(const struct drm_property_blob *a, ++ const struct drm_property_blob *b) ++{ ++ if (a && b) ++ return a->length == b->length && ++ !memcmp(a->data, b->data, a->length); ++ ++ return !a == !b; ++} ++ ++static int cdns_hdmi_connector_atomic_check(struct drm_connector *connector, ++ struct drm_atomic_state *state) ++{ ++ struct drm_connector_state *new_con_state = ++ drm_atomic_get_new_connector_state(state, connector); ++ struct drm_connector_state *old_con_state = ++ drm_atomic_get_old_connector_state(state, connector); ++ struct drm_crtc *crtc = new_con_state->crtc; ++ struct drm_crtc_state *new_crtc_state; ++ ++ if (!blob_equal(new_con_state->hdr_output_metadata, ++ old_con_state->hdr_output_metadata) || ++ new_con_state->colorspace != old_con_state->colorspace) { ++ new_crtc_state = drm_atomic_get_crtc_state(state, crtc); ++ if (IS_ERR(new_crtc_state)) ++ return PTR_ERR(new_crtc_state); ++ ++ new_crtc_state->mode_changed = ++ !new_con_state->hdr_output_metadata || ++ !old_con_state->hdr_output_metadata || ++ new_con_state->colorspace != old_con_state->colorspace; ++ } ++ ++ return 0; ++} ++ ++static const struct drm_connector_funcs cdns_hdmi_connector_funcs = { ++ .fill_modes = drm_helper_probe_single_connector_modes, ++ .detect = cdns_hdmi_connector_detect, ++ .destroy = drm_connector_cleanup, ++ .reset = drm_atomic_helper_connector_reset, ++ .atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state, ++ .atomic_destroy_state = drm_atomic_helper_connector_destroy_state, ++}; ++ ++static const struct drm_connector_helper_funcs cdns_hdmi_connector_helper_funcs = { ++ .get_modes = cdns_hdmi_connector_get_modes, ++ .atomic_check = cdns_hdmi_connector_atomic_check, ++}; ++ ++static int cdns_hdmi_bridge_attach(struct drm_bridge *bridge, enum drm_bridge_attach_flags flags) ++{ ++ struct cdns_mhdp_device *mhdp = bridge->driver_private; ++ struct drm_mode_config *config = &bridge->dev->mode_config; ++ struct drm_encoder *encoder = bridge->encoder; ++ struct drm_connector *connector = &mhdp->connector.base; ++ ++ connector->interlace_allowed = 1; ++ connector->polled = DRM_CONNECTOR_POLL_HPD; ++ ++ drm_connector_helper_add(connector, &cdns_hdmi_connector_helper_funcs); ++ ++ drm_connector_init(bridge->dev, connector, &cdns_hdmi_connector_funcs, ++ DRM_MODE_CONNECTOR_HDMIA); ++ ++ if (!strncmp("imx8mq-hdmi", mhdp->plat_data->plat_name, 11)) { ++ drm_object_attach_property(&connector->base, ++ config->hdr_output_metadata_property, ++ 0); ++ ++ if (!drm_mode_create_hdmi_colorspace_property(connector)) ++ drm_object_attach_property(&connector->base, ++ connector->colorspace_property, ++ 0); ++ } ++ ++ drm_connector_attach_encoder(connector, encoder); ++ ++ return 0; ++} ++ ++static enum drm_mode_status ++cdns_hdmi_bridge_mode_valid(struct drm_bridge *bridge, ++ const struct drm_display_info *info, ++ const struct drm_display_mode *mode) ++{ ++ struct cdns_mhdp_device *mhdp = bridge->driver_private; ++ enum drm_mode_status mode_status = MODE_OK; ++ int ret; ++ ++ /* We don't support double-clocked and Interlaced modes */ ++ if (mode->flags & DRM_MODE_FLAG_DBLCLK || ++ mode->flags & DRM_MODE_FLAG_INTERLACE) ++ return MODE_BAD; ++ ++ /* MAX support pixel clock rate 594MHz */ ++ if (mode->clock > 594000) ++ return MODE_CLOCK_HIGH; ++ ++ /* 4096x2160 is not supported */ ++ if (mode->hdisplay > 3840 || mode->vdisplay > 2160) ++ return MODE_BAD_HVALUE; ++ ++ mhdp->valid_mode = mode; ++ ret = cdns_mhdp_plat_call(mhdp, phy_video_valid); ++ if (ret == false) ++ return MODE_CLOCK_RANGE; ++ ++ return mode_status; ++} ++ ++static void cdns_hdmi_bridge_mode_set(struct drm_bridge *bridge, ++ const struct drm_display_mode *orig_mode, ++ const struct drm_display_mode *mode) ++{ ++ struct cdns_mhdp_device *mhdp = bridge->driver_private; ++ struct video_info *video = &mhdp->video_info; ++ ++ video->v_sync_polarity = !!(mode->flags & DRM_MODE_FLAG_NVSYNC); ++ video->h_sync_polarity = !!(mode->flags & DRM_MODE_FLAG_NHSYNC); ++ ++ printk(KERN_ALERT "cdns-hdmi-core: Mode: %dx%dp%d\n", mode->hdisplay, mode->vdisplay, mode->clock); ++ memcpy(&mhdp->mode, mode, sizeof(struct drm_display_mode)); ++ ++ mutex_lock(&mhdp->lock); ++ cdns_hdmi_mode_set(mhdp); ++ mutex_unlock(&mhdp->lock); ++ /* reset force mode set flag */ ++ mhdp->force_mode_set = false; ++} ++ ++bool cdns_hdmi_bridge_mode_fixup(struct drm_bridge *bridge, ++ const struct drm_display_mode *mode, ++ struct drm_display_mode *adjusted_mode) ++{ ++ struct cdns_mhdp_device *mhdp = bridge->driver_private; ++ struct drm_display_info *di = &mhdp->connector.base.display_info; ++ struct video_info *video = &mhdp->video_info; ++ int vic = drm_match_cea_mode(mode); ++ ++ video->color_depth = 8; ++ video->color_fmt = PXL_RGB; ++ ++ /* for all other platforms, other than imx8mq */ ++ if (strncmp("imx8mq-hdmi", mhdp->plat_data->plat_name, 11)) { ++ if (di->bpc == 10 || di->bpc == 6) ++ video->color_depth = di->bpc; ++ ++ return true; ++ } ++ ++ /* imx8mq */ ++ if (vic == 97 || vic == 96) { ++ if (di->hdmi.y420_dc_modes & DRM_EDID_YCBCR420_DC_36) ++ video->color_depth = 12; ++ else if (di->hdmi.y420_dc_modes & DRM_EDID_YCBCR420_DC_30) ++ video->color_depth = 10; ++ ++ if (drm_mode_is_420_only(di, mode) || ++ (drm_mode_is_420_also(di, mode) && ++ video->color_depth > 8)) { ++ video->color_fmt = YCBCR_4_2_0; ++ ++ // FIXME ++ //adjusted_mode->private_flags = 1; ++ return true; ++ } ++ ++ video->color_depth = 8; ++ return true; ++ } ++ ++ /* Any defined maximum tmds clock limit we must not exceed*/ ++ if ((di->edid_hdmi_dc_modes & DRM_EDID_HDMI_DC_36) && ++ (mode->clock * 3 / 2 <= di->max_tmds_clock)) ++ video->color_depth = 12; ++ else if ((di->edid_hdmi_dc_modes & DRM_EDID_HDMI_DC_30) && ++ (mode->clock * 5 / 4 <= di->max_tmds_clock)) ++ video->color_depth = 10; ++ ++ /* 10-bit color depth for the following modes is not supported */ ++ if ((vic == 95 || vic == 94 || vic == 93) && video->color_depth == 10) ++ video->color_depth = 8; ++ ++ return true; ++} ++ ++static const struct drm_bridge_funcs cdns_hdmi_bridge_funcs = { ++ .attach = cdns_hdmi_bridge_attach, ++ .mode_set = cdns_hdmi_bridge_mode_set, ++ .mode_valid = cdns_hdmi_bridge_mode_valid, ++ .mode_fixup = cdns_hdmi_bridge_mode_fixup, ++}; ++ ++static void hotplug_work_func(struct work_struct *work) ++{ ++ struct cdns_mhdp_device *mhdp = container_of(work, ++ struct cdns_mhdp_device, hotplug_work.work); ++ struct drm_connector *connector = &mhdp->connector.base; ++ ++ drm_helper_hpd_irq_event(connector->dev); ++ ++ if (connector->status == connector_status_connected) { ++ printk(KERN_ALERT "cdns-hdmi-core: HDMI Cable Plug In\n"); ++ enable_irq(mhdp->irq[IRQ_OUT]); ++ } else if (connector->status == connector_status_disconnected) { ++ /* Cable Disconnedted */ ++ printk(KERN_ALERT "cdns-hdmi-core: HDMI Cable Plug Out\n"); ++ /* force mode set for cable replugin to recovery HDMI2.0 video modes */ ++ mhdp->force_mode_set = true; ++ enable_irq(mhdp->irq[IRQ_IN]); ++ } ++} ++ ++static irqreturn_t cdns_hdmi_irq_thread(int irq, void *data) ++{ ++ struct cdns_mhdp_device *mhdp = data; ++ ++ disable_irq_nosync(irq); ++ ++ mod_delayed_work(system_wq, &mhdp->hotplug_work, ++ msecs_to_jiffies(HOTPLUG_DEBOUNCE_MS)); ++ ++ return IRQ_HANDLED; ++} ++ ++static void cdns_hdmi_parse_dt(struct cdns_mhdp_device *mhdp) ++{ ++ struct device_node *of_node = mhdp->dev->of_node; ++ int ret; ++ ++ ret = of_property_read_u32(of_node, "lane-mapping", &mhdp->lane_mapping); ++ if (ret) { ++ mhdp->lane_mapping = 0xc6; ++ dev_warn(mhdp->dev, "Failed to get lane_mapping - using default 0xc6\n"); ++ } ++ dev_info(mhdp->dev, "lane-mapping 0x%02x\n", mhdp->lane_mapping); ++} ++ ++static int __cdns_hdmi_probe(struct platform_device *pdev, ++ struct cdns_mhdp_device *mhdp) ++{ ++ struct device *dev = &pdev->dev; ++ struct platform_device_info pdevinfo; ++ struct resource *iores = NULL; ++ int ret; ++ ++ mutex_init(&mhdp->lock); ++ mutex_init(&mhdp->iolock); ++ ++ INIT_DELAYED_WORK(&mhdp->hotplug_work, hotplug_work_func); ++ ++ iores = platform_get_resource(pdev, IORESOURCE_MEM, 0); ++ mhdp->regs_base = devm_ioremap(dev, iores->start, resource_size(iores)); ++ if (IS_ERR(mhdp->regs_base)) { ++ dev_err(dev, "No regs_base memory\n"); ++ return -ENOMEM; ++ } ++ ++ /* sec register base */ ++ iores = platform_get_resource(pdev, IORESOURCE_MEM, 1); ++ mhdp->regs_sec = devm_ioremap(dev, iores->start, resource_size(iores)); ++ if (IS_ERR(mhdp->regs_sec)) { ++ dev_err(dev, "No regs_sec memory\n"); ++ return -ENOMEM; ++ } ++ ++ mhdp->irq[IRQ_IN] = platform_get_irq_byname(pdev, "plug_in"); ++ if (mhdp->irq[IRQ_IN] < 0) { ++ dev_info(dev, "No plug_in irq number\n"); ++ return -EPROBE_DEFER; ++ } ++ ++ mhdp->irq[IRQ_OUT] = platform_get_irq_byname(pdev, "plug_out"); ++ if (mhdp->irq[IRQ_OUT] < 0) { ++ dev_info(dev, "No plug_out irq number\n"); ++ return -EPROBE_DEFER; ++ } ++ ++ cdns_mhdp_plat_call(mhdp, power_on); ++ ++ /* Initialize FW */ ++ cdns_mhdp_plat_call(mhdp, firmware_init); ++ ++ /* HDMI FW alive check */ ++ ret = cdns_mhdp_check_alive(mhdp); ++ if (ret == false) { ++ dev_err(dev, "NO HDMI FW running\n"); ++ return -ENXIO; ++ } ++ ++ /* Enable Hotplug Detect thread */ ++ irq_set_status_flags(mhdp->irq[IRQ_IN], IRQ_NOAUTOEN); ++ ret = devm_request_threaded_irq(dev, mhdp->irq[IRQ_IN], ++ NULL, cdns_hdmi_irq_thread, ++ IRQF_ONESHOT, dev_name(dev), ++ mhdp); ++ if (ret < 0) { ++ dev_err(dev, "can't claim irq %d\n", ++ mhdp->irq[IRQ_IN]); ++ return -EINVAL; ++ } ++ ++ irq_set_status_flags(mhdp->irq[IRQ_OUT], IRQ_NOAUTOEN); ++ ret = devm_request_threaded_irq(dev, mhdp->irq[IRQ_OUT], ++ NULL, cdns_hdmi_irq_thread, ++ IRQF_ONESHOT, dev_name(dev), ++ mhdp); ++ if (ret < 0) { ++ dev_err(dev, "can't claim irq %d\n", ++ mhdp->irq[IRQ_OUT]); ++ return -EINVAL; ++ } ++ ++ cdns_hdmi_parse_dt(mhdp); ++ ++ if (cdns_mhdp_read_hpd(mhdp)) ++ enable_irq(mhdp->irq[IRQ_OUT]); ++ else ++ enable_irq(mhdp->irq[IRQ_IN]); ++ ++ mhdp->bridge.base.driver_private = mhdp; ++ mhdp->bridge.base.funcs = &cdns_hdmi_bridge_funcs; ++#ifdef CONFIG_OF ++ mhdp->bridge.base.of_node = dev->of_node; ++#endif ++ ++ memset(&pdevinfo, 0, sizeof(pdevinfo)); ++ pdevinfo.parent = dev; ++ pdevinfo.id = PLATFORM_DEVID_AUTO; ++ ++ dev_set_drvdata(dev, mhdp); ++ ++ /* register audio driver */ ++ //cdns_mhdp_register_audio_driver(dev); ++ ++ /* register cec driver */ ++#ifdef CONFIG_DRM_CDNS_HDMI_CEC ++ cdns_mhdp_register_cec_driver(dev); ++#endif ++ ++ return 0; ++} ++ ++static void __cdns_hdmi_remove(struct cdns_mhdp_device *mhdp) ++{ ++ /* unregister cec driver */ ++#ifdef CONFIG_DRM_CDNS_HDMI_CEC ++ cdns_mhdp_unregister_cec_driver(mhdp->dev); ++#endif ++ //cdns_mhdp_unregister_audio_driver(mhdp->dev); ++} ++ ++/* ----------------------------------------------------------------------------- ++ * Probe/remove API, used from platforms based on the DRM bridge API. ++ */ ++int cdns_hdmi_probe(struct platform_device *pdev, ++ struct cdns_mhdp_device *mhdp) ++{ ++ int ret; ++ ++ ret = __cdns_hdmi_probe(pdev, mhdp); ++ if (ret < 0) ++ return ret; ++ ++ drm_bridge_add(&mhdp->bridge.base); ++ ++ return 0; ++} ++EXPORT_SYMBOL_GPL(cdns_hdmi_probe); ++ ++void cdns_hdmi_remove(struct platform_device *pdev) ++{ ++ struct cdns_mhdp_device *mhdp = platform_get_drvdata(pdev); ++ ++ drm_bridge_remove(&mhdp->bridge.base); ++ ++ __cdns_hdmi_remove(mhdp); ++} ++EXPORT_SYMBOL_GPL(cdns_hdmi_remove); ++ ++/* ----------------------------------------------------------------------------- ++ * Bind/unbind API, used from platforms based on the component framework. ++ */ ++int cdns_hdmi_bind(struct platform_device *pdev, struct drm_encoder *encoder, ++ struct cdns_mhdp_device *mhdp) ++{ ++ int ret; ++ ++ ret = __cdns_hdmi_probe(pdev, mhdp); ++ if (ret) ++ return ret; ++ ++ ret = drm_bridge_attach(encoder, &mhdp->bridge.base, NULL, 0); // FIXME flags? ++ if (ret) { ++ cdns_hdmi_remove(pdev); ++ printk(KERN_ALERT "cdns-hdmi-core: Failed to initialize bridge with drm\n"); ++ return ret; ++ } ++ ++ return 0; ++} ++EXPORT_SYMBOL_GPL(cdns_hdmi_bind); ++ ++void cdns_hdmi_unbind(struct device *dev) ++{ ++ struct cdns_mhdp_device *mhdp = dev_get_drvdata(dev); ++ ++ __cdns_hdmi_remove(mhdp); ++} ++EXPORT_SYMBOL_GPL(cdns_hdmi_unbind); ++ ++MODULE_AUTHOR("Sandor Yu "); ++MODULE_DESCRIPTION("Cadence HDMI transmitter driver"); ++MODULE_LICENSE("GPL"); ++MODULE_ALIAS("platform:cdn-hdmi"); +diff --git a/drivers/gpu/drm/bridge/cadence/cdns-mhdp-audio.c b/drivers/gpu/drm/bridge/cadence/cdns-mhdp-audio.c +new file mode 100644 +index 000000000000..5e71848ea30d +--- /dev/null ++++ b/drivers/gpu/drm/bridge/cadence/cdns-mhdp-audio.c +@@ -0,0 +1,393 @@ ++// SPDX-License-Identifier: GPL-2.0 ++/* ++ * Copyright (C) Fuzhou Rockchip Electronics Co.Ltd ++ * Author: Chris Zhong ++ * ++ * This software is licensed under the terms of the GNU General Public ++ * License version 2, as published by the Free Software Foundation, and ++ * may be copied, distributed, and modified under those terms. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ */ ++#include ++#include ++#include ++#include ++#include ++ ++#define CDNS_DP_SPDIF_CLK 200000000 ++ ++static u32 TMDS_rate_table[7] = { ++ 25200, 27000, 54000, 74250, 148500, 297000, 594000, ++}; ++ ++static u32 N_table_32k[7] = { ++/* 25200/27000/54000/74250/148500/297000/594000 */ ++ 4096, 4096, 4096, 4096, 4096, 3072, 3072, ++}; ++ ++static u32 N_table_44k[7] = { ++ 6272, 6272, 6272, 6272, 6272, 4704, 9408, ++}; ++ ++static u32 N_table_48k[7] = { ++ 6144, 6144, 6144, 6144, 6144, 5120, 6144, ++}; ++ ++static int select_N_index(u32 pclk) ++{ ++ int num = sizeof(TMDS_rate_table)/sizeof(int); ++ int i = 0; ++ ++ for (i = 0; i < num ; i++) ++ if (pclk == TMDS_rate_table[i]) ++ break; ++ ++ if (i == num) { ++ printk("cdn-mhdp-audio: pclkc %d is not supported!\n", pclk); ++ return num-1; ++ } ++ ++ return i; ++} ++ ++static void hdmi_audio_avi_set(struct cdns_mhdp_device *mhdp, ++ u32 channels) ++{ ++ struct hdmi_audio_infoframe frame; ++ u8 buf[32]; ++ int ret; ++ ++ hdmi_audio_infoframe_init(&frame); ++ ++ frame.channels = channels; ++ frame.coding_type = HDMI_AUDIO_CODING_TYPE_STREAM; ++ ++ if (channels == 2) ++ frame.channel_allocation = 0; ++ else if (channels == 4) ++ frame.channel_allocation = 0x3; ++ else if (channels == 8) ++ frame.channel_allocation = 0x13; ++ ++ ret = hdmi_audio_infoframe_pack(&frame, buf + 1, sizeof(buf) - 1); ++ if (ret < 0) { ++ printk("cdns-mhdp-audio: failed to pack audio infoframe: %d\n", ret); ++ return; ++ } ++ ++ buf[0] = 0; ++ ++ cdns_mhdp_infoframe_set(mhdp, 1, sizeof(buf), buf, HDMI_INFOFRAME_TYPE_AUDIO); ++} ++ ++int cdns_mhdp_audio_stop(struct cdns_mhdp_device *mhdp, ++ struct audio_info *audio) ++{ ++ int ret; ++ ++ if (audio->connector_type == DRM_MODE_CONNECTOR_DisplayPort) { ++ ret = cdns_mhdp_reg_write(mhdp, AUDIO_PACK_CONTROL, 0); ++ if (ret) { ++ dev_err(mhdp->dev, "audio stop failed: %d\n", ret); ++ return ret; ++ } ++ } ++ ++ cdns_mhdp_bus_write(0, mhdp, SPDIF_CTRL_ADDR); ++ ++ /* clearn the audio config and reset */ ++ cdns_mhdp_bus_write(0, mhdp, AUDIO_SRC_CNTL); ++ cdns_mhdp_bus_write(0, mhdp, AUDIO_SRC_CNFG); ++ cdns_mhdp_bus_write(AUDIO_SW_RST, mhdp, AUDIO_SRC_CNTL); ++ cdns_mhdp_bus_write(0, mhdp, AUDIO_SRC_CNTL); ++ ++ /* reset smpl2pckt component */ ++ cdns_mhdp_bus_write(0, mhdp, SMPL2PKT_CNTL); ++ cdns_mhdp_bus_write(AUDIO_SW_RST, mhdp, SMPL2PKT_CNTL); ++ cdns_mhdp_bus_write(0, mhdp, SMPL2PKT_CNTL); ++ ++ /* reset FIFO */ ++ cdns_mhdp_bus_write(AUDIO_SW_RST, mhdp, FIFO_CNTL); ++ cdns_mhdp_bus_write(0, mhdp, FIFO_CNTL); ++ ++ if (audio->format == AFMT_SPDIF_INT) ++ clk_disable_unprepare(mhdp->spdif_clk); ++ ++ return 0; ++} ++EXPORT_SYMBOL(cdns_mhdp_audio_stop); ++ ++int cdns_mhdp_audio_mute(struct cdns_mhdp_device *mhdp, bool enable) ++{ ++ struct audio_info *audio = &mhdp->audio_info; ++ int ret = true; ++ ++ if (audio->connector_type == DRM_MODE_CONNECTOR_DisplayPort) { ++ ret = cdns_mhdp_reg_write_bit(mhdp, DP_VB_ID, 4, 1, enable); ++ if (ret) ++ dev_err(mhdp->dev, "audio mute failed: %d\n", ret); ++ } ++ ++ return ret; ++} ++EXPORT_SYMBOL(cdns_mhdp_audio_mute); ++ ++static void cdns_mhdp_audio_config_i2s(struct cdns_mhdp_device *mhdp, ++ struct audio_info *audio) ++{ ++ int sub_pckt_num = 1, i2s_port_en_val = 0xf, i; ++ int idx = select_N_index(mhdp->mode.clock); ++ u32 val, ncts; ++ ++ if (audio->channels == 2) { ++ if (mhdp->dp.link.num_lanes == 1) ++ sub_pckt_num = 2; ++ else ++ sub_pckt_num = 4; ++ ++ i2s_port_en_val = 1; ++ } else if (audio->channels == 4) { ++ i2s_port_en_val = 3; ++ } ++ ++ cdns_mhdp_bus_write(0x0, mhdp, SPDIF_CTRL_ADDR); ++ ++ cdns_mhdp_bus_write(SYNC_WR_TO_CH_ZERO, mhdp, FIFO_CNTL); ++ ++ val = MAX_NUM_CH(audio->channels); ++ val |= NUM_OF_I2S_PORTS(audio->channels); ++ val |= AUDIO_TYPE_LPCM; ++ val |= CFG_SUB_PCKT_NUM(sub_pckt_num); ++ cdns_mhdp_bus_write(val, mhdp, SMPL2PKT_CNFG); ++ ++ if (audio->sample_width == 16) ++ val = 0; ++ else if (audio->sample_width == 24) ++ val = 1 << 9; ++ else ++ val = 2 << 9; ++ ++ val |= AUDIO_CH_NUM(audio->channels); ++ val |= I2S_DEC_PORT_EN(i2s_port_en_val); ++ val |= TRANS_SMPL_WIDTH_32; ++ cdns_mhdp_bus_write(val, mhdp, AUDIO_SRC_CNFG); ++ ++ for (i = 0; i < (audio->channels + 1) / 2; i++) { ++ if (audio->sample_width == 16) ++ val = (0x02 << 8) | (0x02 << 20); ++ else if (audio->sample_width == 24) ++ val = (0x0b << 8) | (0x0b << 20); ++ ++ val |= ((2 * i) << 4) | ((2 * i + 1) << 16); ++ cdns_mhdp_bus_write(val, mhdp, STTS_BIT_CH(i)); ++ } ++ ++ switch (audio->sample_rate) { ++ case 32000: ++ val = SAMPLING_FREQ(3) | ++ ORIGINAL_SAMP_FREQ(0xc); ++ ncts = N_table_32k[idx]; ++ break; ++ case 44100: ++ val = SAMPLING_FREQ(0) | ++ ORIGINAL_SAMP_FREQ(0xf); ++ ncts = N_table_44k[idx]; ++ break; ++ case 48000: ++ val = SAMPLING_FREQ(2) | ++ ORIGINAL_SAMP_FREQ(0xd); ++ ncts = N_table_48k[idx]; ++ break; ++ case 88200: ++ val = SAMPLING_FREQ(8) | ++ ORIGINAL_SAMP_FREQ(0x7); ++ ncts = N_table_44k[idx] * 2; ++ break; ++ case 96000: ++ val = SAMPLING_FREQ(0xa) | ++ ORIGINAL_SAMP_FREQ(5); ++ ncts = N_table_48k[idx] * 2; ++ break; ++ case 176400: ++ val = SAMPLING_FREQ(0xc) | ++ ORIGINAL_SAMP_FREQ(3); ++ ncts = N_table_44k[idx] * 4; ++ break; ++ case 192000: ++ default: ++ val = SAMPLING_FREQ(0xe) | ++ ORIGINAL_SAMP_FREQ(1); ++ ncts = N_table_48k[idx] * 4; ++ break; ++ } ++ val |= 4; ++ cdns_mhdp_bus_write(val, mhdp, COM_CH_STTS_BITS); ++ ++ if (audio->connector_type == DRM_MODE_CONNECTOR_HDMIA) ++ cdns_mhdp_reg_write(mhdp, CM_I2S_CTRL, ncts | 0x4000000); ++ ++ cdns_mhdp_bus_write(SMPL2PKT_EN, mhdp, SMPL2PKT_CNTL); ++ cdns_mhdp_bus_write(I2S_DEC_START, mhdp, AUDIO_SRC_CNTL); ++} ++ ++static void cdns_mhdp_audio_config_spdif(struct cdns_mhdp_device *mhdp) ++{ ++ u32 val; ++ ++ cdns_mhdp_bus_write(SYNC_WR_TO_CH_ZERO, mhdp, FIFO_CNTL); ++ ++ val = MAX_NUM_CH(2) | AUDIO_TYPE_LPCM | CFG_SUB_PCKT_NUM(4); ++ cdns_mhdp_bus_write(val, mhdp, SMPL2PKT_CNFG); ++ cdns_mhdp_bus_write(SMPL2PKT_EN, mhdp, SMPL2PKT_CNTL); ++ ++ val = SPDIF_ENABLE | SPDIF_AVG_SEL | SPDIF_JITTER_BYPASS; ++ cdns_mhdp_bus_write(val, mhdp, SPDIF_CTRL_ADDR); ++ ++ clk_prepare_enable(mhdp->spdif_clk); ++ clk_set_rate(mhdp->spdif_clk, CDNS_DP_SPDIF_CLK); ++} ++ ++int cdns_mhdp_audio_config(struct cdns_mhdp_device *mhdp, ++ struct audio_info *audio) ++{ ++ int ret; ++ ++ /* reset the spdif clk before config */ ++ if (audio->format == AFMT_SPDIF_INT) { ++ reset_control_assert(mhdp->spdif_rst); ++ reset_control_deassert(mhdp->spdif_rst); ++ } ++ ++ if (audio->connector_type == DRM_MODE_CONNECTOR_DisplayPort) { ++ ret = cdns_mhdp_reg_write(mhdp, CM_LANE_CTRL, LANE_REF_CYC); ++ if (ret) ++ goto err_audio_config; ++ ++ ret = cdns_mhdp_reg_write(mhdp, CM_CTRL, 0); ++ if (ret) ++ goto err_audio_config; ++ } else { ++ /* HDMI Mode */ ++ ret = cdns_mhdp_reg_write(mhdp, CM_CTRL, 8); ++ if (ret) ++ goto err_audio_config; ++ } ++ ++ if (audio->format == AFMT_I2S) ++ cdns_mhdp_audio_config_i2s(mhdp, audio); ++ else if (audio->format == AFMT_SPDIF_INT) ++ cdns_mhdp_audio_config_spdif(mhdp); ++ ++ if (audio->connector_type == DRM_MODE_CONNECTOR_DisplayPort) ++ ret = cdns_mhdp_reg_write(mhdp, AUDIO_PACK_CONTROL, AUDIO_PACK_EN); ++ ++ if (audio->connector_type == DRM_MODE_CONNECTOR_HDMIA) ++ hdmi_audio_avi_set(mhdp, audio->channels); ++ ++err_audio_config: ++ if (ret) ++ dev_err(mhdp->dev, "audio config failed: %d\n", ret); ++ return ret; ++} ++EXPORT_SYMBOL(cdns_mhdp_audio_config); ++ ++static int audio_hw_params(struct device *dev, void *data, ++ struct hdmi_codec_daifmt *daifmt, ++ struct hdmi_codec_params *params) ++{ ++ struct cdns_mhdp_device *mhdp = dev_get_drvdata(dev); ++ struct audio_info audio = { ++ .sample_width = params->sample_width, ++ .sample_rate = params->sample_rate, ++ .channels = params->channels, ++ .connector_type = mhdp->connector.base.connector_type, ++ }; ++ int ret; ++ ++ switch (daifmt->fmt) { ++ case HDMI_I2S: ++ audio.format = AFMT_I2S; ++ break; ++ case HDMI_SPDIF: ++ audio.format = AFMT_SPDIF_EXT; ++ break; ++ default: ++ dev_err(dev, "Invalid format %d\n", daifmt->fmt); ++ ret = -EINVAL; ++ goto out; ++ } ++ ++ ret = cdns_mhdp_audio_config(mhdp, &audio); ++ if (!ret) ++ mhdp->audio_info = audio; ++ ++out: ++ return ret; ++} ++ ++static void audio_shutdown(struct device *dev, void *data) ++{ ++ struct cdns_mhdp_device *mhdp = dev_get_drvdata(dev); ++ int ret; ++ ++ ret = cdns_mhdp_audio_stop(mhdp, &mhdp->audio_info); ++ if (!ret) ++ mhdp->audio_info.format = AFMT_UNUSED; ++} ++ ++static int audio_digital_mute(struct device *dev, void *data, ++ bool enable) ++{ ++ struct cdns_mhdp_device *mhdp = dev_get_drvdata(dev); ++ int ret; ++ ++ ret = cdns_mhdp_audio_mute(mhdp, enable); ++ ++ return ret; ++} ++ ++static int audio_get_eld(struct device *dev, void *data, ++ u8 *buf, size_t len) ++{ ++ struct cdns_mhdp_device *mhdp = dev_get_drvdata(dev); ++ ++ memcpy(buf, mhdp->connector.base.eld, ++ min(sizeof(mhdp->connector.base.eld), len)); ++ ++ return 0; ++} ++ ++static const struct hdmi_codec_ops audio_codec_ops = { ++ .hw_params = audio_hw_params, ++ .audio_shutdown = audio_shutdown, ++//.digital_mute = audio_digital_mute, ++ .get_eld = audio_get_eld, ++}; ++ ++int cdns_mhdp_register_audio_driver(struct device *dev) ++{ ++ struct cdns_mhdp_device *mhdp = dev_get_drvdata(dev); ++ struct hdmi_codec_pdata codec_data = { ++ .i2s = 1, ++ .spdif = 1, ++ .ops = &audio_codec_ops, ++ .max_i2s_channels = 8, ++ }; ++ ++ mhdp->audio_pdev = platform_device_register_data( ++ dev, HDMI_CODEC_DRV_NAME, 1, ++ &codec_data, sizeof(codec_data)); ++ ++ return PTR_ERR_OR_ZERO(mhdp->audio_pdev); ++} ++ ++void cdns_mhdp_unregister_audio_driver(struct device *dev) ++{ ++ struct cdns_mhdp_device *mhdp = dev_get_drvdata(dev); ++ ++ platform_device_unregister(mhdp->audio_pdev); ++} +diff --git a/drivers/gpu/drm/bridge/cadence/cdns-mhdp-cec.c b/drivers/gpu/drm/bridge/cadence/cdns-mhdp-cec.c +new file mode 100644 +index 000000000000..af8506444f6e +--- /dev/null ++++ b/drivers/gpu/drm/bridge/cadence/cdns-mhdp-cec.c +@@ -0,0 +1,341 @@ ++/* ++ * Copyright 2019 NXP ++ * ++ * This program is free software; you can redistribute it and/or ++ * modify it under the terms of the GNU General Public License ++ * as published by the Free Software Foundation; either version 2 ++ * of the License, or (at your option) any later version. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ */ ++#include ++#include ++#include ++#include ++#include ++ ++#define CEC_NAME "cdns-mhdp-cec" ++ ++#define REG_ADDR_OFF 4 ++ ++/* regsiter define */ ++#define TX_MSG_HEADER 0x33800 ++#define TX_MSG_LENGTH 0x33840 ++#define TX_MSG_CMD 0x33844 ++#define RX_MSG_CMD 0x33850 ++#define RX_CLEAR_BUF 0x33854 ++#define LOGICAL_ADDRESS_LA0 0x33858 ++ ++#define CLK_DIV_MSB 0x3386c ++#define CLK_DIV_LSB 0x33870 ++#define RX_MSG_DATA1 0x33900 ++#define RX_MSG_LENGTH 0x33940 ++#define RX_MSG_STATUS 0x33944 ++#define NUM_OF_MSG_RX_BUF 0x33948 ++#define TX_MSG_STATUS 0x3394c ++#define DB_L_TIMER 0x33980 ++ ++/** ++ * CEC Transceiver operation. ++ */ ++enum { ++ CEC_TX_STOP, ++ CEC_TX_TRANSMIT, ++ CEC_TX_ABORT, ++ CEC_TX_ABORT_AND_TRANSMIT ++}; ++ ++/** ++ * CEC Transceiver status. ++ */ ++enum { ++ CEC_STS_IDLE, ++ CEC_STS_BUSY, ++ CEC_STS_SUCCESS, ++ CEC_STS_ERROR ++}; ++ ++/** ++ * CEC Receiver operation. ++ */ ++enum { ++ CEC_RX_STOP, ++ CEC_RX_READ, ++ CEC_RX_DISABLE, ++ CEC_RX_ABORT_AND_CLR_FIFO ++}; ++/** ++ * Maximum number of Messages in the RX Buffers. ++ */ ++#define CEC_MAX_RX_MSGS 2 ++ ++static u32 mhdp_cec_read(struct cdns_mhdp_cec *cec, u32 offset) ++{ ++ struct cdns_mhdp_device *mhdp = ++ container_of(cec, struct cdns_mhdp_device, hdmi.cec); ++ return cdns_mhdp_bus_read(mhdp, offset); ++} ++ ++static void mhdp_cec_write(struct cdns_mhdp_cec *cec, u32 offset, u32 val) ++{ ++ struct cdns_mhdp_device *mhdp = ++ container_of(cec, struct cdns_mhdp_device, hdmi.cec); ++ cdns_mhdp_bus_write(val, mhdp, offset); ++} ++ ++static void mhdp_cec_clear_rx_buffer(struct cdns_mhdp_cec *cec) ++{ ++ mhdp_cec_write(cec, RX_CLEAR_BUF, 1); ++ mhdp_cec_write(cec, RX_CLEAR_BUF, 0); ++} ++ ++static void mhdp_cec_set_divider(struct cdns_mhdp_cec *cec) ++{ ++ struct cdns_mhdp_device *mhdp = ++ container_of(cec, struct cdns_mhdp_device, hdmi.cec); ++ u32 clk_div; ++ ++ /* Set clock divider */ ++ clk_div = cdns_mhdp_get_fw_clk(mhdp) * 10; ++ ++ mhdp_cec_write(cec, CLK_DIV_MSB, ++ (clk_div >> 8) & 0xFF); ++ mhdp_cec_write(cec, CLK_DIV_LSB, clk_div & 0xFF); ++} ++ ++static u32 mhdp_cec_read_message(struct cdns_mhdp_cec *cec) ++{ ++ struct cec_msg *msg = &cec->msg; ++ int len; ++ int i; ++ ++ mhdp_cec_write(cec, RX_MSG_CMD, CEC_RX_READ); ++ ++ len = mhdp_cec_read(cec, RX_MSG_LENGTH); ++ msg->len = len + 1; ++ dev_dbg(cec->dev, "RX MSG len =%d\n", len); ++ ++ /* Read RX MSG bytes */ ++ for (i = 0; i < msg->len; ++i) { ++ msg->msg[i] = (u8) mhdp_cec_read(cec, RX_MSG_DATA1 + (i * REG_ADDR_OFF)); ++ dev_dbg(cec->dev, "RX MSG[%d]=0x%x\n", i, msg->msg[i]); ++ } ++ ++ mhdp_cec_write(cec, RX_MSG_CMD, CEC_RX_STOP); ++ ++ return true; ++} ++ ++static u32 mhdp_cec_write_message(struct cdns_mhdp_cec *cec, struct cec_msg *msg) ++{ ++ u8 i; ++ ++ mhdp_cec_write(cec, TX_MSG_CMD, CEC_TX_STOP); ++ ++ if (msg->len > CEC_MAX_MSG_SIZE) { ++ dev_err(cec->dev, "Invalid MSG size!\n"); ++ return -EINVAL; ++ } ++ ++ for (i = 0; i < msg->len; ++i) ++ printk("msg[%d]=0x%x\n",i, msg->msg[i]); ++ ++ /* Write Message to register */ ++ for (i = 0; i < msg->len; ++i) { ++ mhdp_cec_write(cec, TX_MSG_HEADER + (i * REG_ADDR_OFF), ++ msg->msg[i]); ++ } ++ /* Write Message Length (payload + opcode) */ ++ mhdp_cec_write(cec, TX_MSG_LENGTH, msg->len - 1); ++ ++ mhdp_cec_write(cec, TX_MSG_CMD, CEC_TX_TRANSMIT); ++ ++ return true; ++} ++ ++static int mhdp_cec_set_logical_addr(struct cdns_mhdp_cec *cec, u32 la) ++{ ++ u8 la_reg; ++ u8 i; ++ ++ if (la == CEC_LOG_ADDR_INVALID) ++ /* invalid all LA address */ ++ for (i = 0; i < CEC_MAX_LOG_ADDRS; ++i) { ++ mhdp_cec_write(cec, LOGICAL_ADDRESS_LA0 + (i * REG_ADDR_OFF), 0); ++ return 0; ++ } ++ ++ /* In fact cdns mhdp cec could support max 5 La address */ ++ for (i = 0; i < CEC_MAX_LOG_ADDRS; ++i) { ++ la_reg = mhdp_cec_read(cec, LOGICAL_ADDRESS_LA0 + (i * REG_ADDR_OFF)); ++ /* Check LA already used */ ++ if (la_reg & 0x10) ++ continue; ++ ++ if ((la_reg & 0xF) == la) { ++ dev_warn(cec->dev, "Warning. LA already in use.\n"); ++ return 0; ++ } ++ ++ la = (la & 0xF) | (1 << 4); ++ ++ mhdp_cec_write(cec, LOGICAL_ADDRESS_LA0 + (i * REG_ADDR_OFF), la); ++ return 0; ++ } ++ ++ dev_warn(cec->dev, "All LA in use\n"); ++ ++ return -ENXIO; ++} ++ ++static int mhdp_cec_poll_worker(void *_cec) ++{ ++ struct cdns_mhdp_cec *cec = (struct cdns_mhdp_cec *)_cec; ++ int num_rx_msgs, i; ++ int sts; ++ ++ set_freezable(); ++ ++ for (;;) { ++ if (kthread_freezable_should_stop(NULL)) ++ break; ++ ++ /* Check TX State */ ++ sts = mhdp_cec_read(cec, TX_MSG_STATUS); ++ switch (sts) { ++ case CEC_STS_SUCCESS: ++ cec_transmit_done(cec->adap, CEC_TX_STATUS_OK, 0, 0, 0, ++ 0); ++ mhdp_cec_write(cec, TX_MSG_CMD, CEC_TX_STOP); ++ break; ++ case CEC_STS_ERROR: ++ mhdp_cec_write(cec, TX_MSG_CMD, CEC_TX_STOP); ++ cec_transmit_done(cec->adap, ++ CEC_TX_STATUS_MAX_RETRIES | ++ CEC_TX_STATUS_NACK, 0, 1, 0, 0); ++ break; ++ case CEC_STS_BUSY: ++ default: ++ break; ++ } ++ ++ /* Check RX State */ ++ sts = mhdp_cec_read(cec, RX_MSG_STATUS); ++ num_rx_msgs = mhdp_cec_read(cec, NUM_OF_MSG_RX_BUF); ++ switch (sts) { ++ case CEC_STS_SUCCESS: ++ if (num_rx_msgs == 0xf) ++ num_rx_msgs = CEC_MAX_RX_MSGS; ++ ++ if (num_rx_msgs > CEC_MAX_RX_MSGS) { ++ dev_err(cec->dev, "Error rx msg num %d\n", ++ num_rx_msgs); ++ mhdp_cec_clear_rx_buffer(cec); ++ break; ++ } ++ ++ /* Rx FIFO Depth 2 RX MSG */ ++ for (i = 0; i < num_rx_msgs; i++) { ++ mhdp_cec_read_message(cec); ++ cec->msg.rx_status = CEC_RX_STATUS_OK; ++ cec_received_msg(cec->adap, &cec->msg); ++ } ++ break; ++ default: ++ break; ++ } ++ ++ if (!kthread_should_stop()) ++ schedule_timeout_idle(20); ++ } ++ ++ return 0; ++} ++ ++static int mhdp_cec_adap_enable(struct cec_adapter *adap, bool enable) ++{ ++ struct cdns_mhdp_cec *cec = cec_get_drvdata(adap); ++ ++ if (enable) { ++ mhdp_cec_write(cec, DB_L_TIMER, 0x10); ++ mhdp_cec_set_divider(cec); ++ } else ++ mhdp_cec_set_divider(cec); ++ ++ return 0; ++} ++ ++static int mhdp_cec_adap_log_addr(struct cec_adapter *adap, u8 addr) ++{ ++ struct cdns_mhdp_cec *cec = cec_get_drvdata(adap); ++ ++ return mhdp_cec_set_logical_addr(cec, addr); ++} ++ ++static int mhdp_cec_adap_transmit(struct cec_adapter *adap, u8 attempts, ++ u32 signal_free_time, struct cec_msg *msg) ++{ ++ struct cdns_mhdp_cec *cec = cec_get_drvdata(adap); ++ ++ mhdp_cec_write_message(cec, msg); ++ ++ return 0; ++} ++ ++static const struct cec_adap_ops cdns_mhdp_cec_adap_ops = { ++ .adap_enable = mhdp_cec_adap_enable, ++ .adap_log_addr = mhdp_cec_adap_log_addr, ++ .adap_transmit = mhdp_cec_adap_transmit, ++}; ++ ++int cdns_mhdp_register_cec_driver(struct device *dev) ++{ ++ struct cdns_mhdp_device *mhdp = dev_get_drvdata(dev); ++ struct cdns_mhdp_cec *cec = &mhdp->hdmi.cec; ++ int ret; ++ ++ cec->adap = cec_allocate_adapter(&cdns_mhdp_cec_adap_ops, cec, ++ CEC_NAME, ++ CEC_CAP_PHYS_ADDR | CEC_CAP_LOG_ADDRS | ++ CEC_CAP_TRANSMIT | CEC_CAP_PASSTHROUGH ++ | CEC_CAP_RC, CEC_MAX_LOG_ADDRS); ++ ret = PTR_ERR_OR_ZERO(cec->adap); ++ if (ret) ++ return ret; ++ ret = cec_register_adapter(cec->adap, dev); ++ if (ret) { ++ cec_delete_adapter(cec->adap); ++ return ret; ++ } ++ ++ cec->dev = dev; ++ ++ cec->cec_worker = kthread_create(mhdp_cec_poll_worker, cec, "cdns-mhdp-cec"); ++ if (IS_ERR(cec->cec_worker)) ++ dev_err(cec->dev, "failed create hdp cec thread\n"); ++ ++ wake_up_process(cec->cec_worker); ++ ++ dev_dbg(dev, "CEC successfuly probed\n"); ++ return 0; ++} ++ ++int cdns_mhdp_unregister_cec_driver(struct device *dev) ++{ ++ struct cdns_mhdp_device *mhdp = dev_get_drvdata(dev); ++ struct cdns_mhdp_cec *cec = &mhdp->hdmi.cec; ++ ++ if (cec->cec_worker) { ++ kthread_stop(cec->cec_worker); ++ cec->cec_worker = NULL; ++ } ++ cec_unregister_adapter(cec->adap); ++ return 0; ++} ++ ++MODULE_AUTHOR("Sandor.Yu@NXP.com"); ++MODULE_LICENSE("GPL"); ++MODULE_DESCRIPTION("NXP CDNS MHDP HDMI CEC driver"); +diff --git a/drivers/gpu/drm/bridge/cadence/cdns-mhdp-common.c b/drivers/gpu/drm/bridge/cadence/cdns-mhdp-common.c +new file mode 100644 +index 000000000000..14a088887bc2 +--- /dev/null ++++ b/drivers/gpu/drm/bridge/cadence/cdns-mhdp-common.c +@@ -0,0 +1,1060 @@ ++// SPDX-License-Identifier: GPL-2.0 ++/* ++ * Copyright (C) Fuzhou Rockchip Electronics Co.Ltd ++ * Author: Chris Zhong ++ * ++ * This software is licensed under the terms of the GNU General Public ++ * License version 2, as published by the Free Software Foundation, and ++ * may be copied, distributed, and modified under those terms. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ */ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#include ++ ++#include ++#include ++#include ++#include ++ ++#define CDNS_DP_SPDIF_CLK 200000000 ++#define FW_ALIVE_TIMEOUT_US 1000000 ++#define MAILBOX_RETRY_US 1000 ++#define MAILBOX_TIMEOUT_US 5000000 ++#define LINK_TRAINING_RETRY_MS 20 ++#define LINK_TRAINING_TIMEOUT_MS 500 ++ ++#define mhdp_readx_poll_timeout(op, addr, offset, val, cond, sleep_us, timeout_us) \ ++({ \ ++ u64 __timeout_us = (timeout_us); \ ++ unsigned long __sleep_us = (sleep_us); \ ++ ktime_t __timeout = ktime_add_us(ktime_get(), __timeout_us); \ ++ might_sleep_if((__sleep_us) != 0); \ ++ for (;;) { \ ++ (val) = op(addr, offset); \ ++ if (cond) \ ++ break; \ ++ if (__timeout_us && \ ++ ktime_compare(ktime_get(), __timeout) > 0) { \ ++ (val) = op(addr, offset); \ ++ break; \ ++ } \ ++ if (__sleep_us) \ ++ usleep_range((__sleep_us >> 2) + 1, __sleep_us); \ ++ } \ ++ (cond) ? 0 : -ETIMEDOUT; \ ++}) ++ ++/*static inline u32 get_unaligned_be24(const void *p) ++{ ++ const u8 *_p = p; ++ ++ return _p[0] << 16 | _p[1] << 8 | _p[2]; ++} ++ ++static inline void put_unaligned_be24(u32 val, void *p) ++{ ++ u8 *_p = p; ++ ++ _p[0] = val >> 16; ++ _p[1] = val >> 8; ++ _p[2] = val; ++}*/ ++ ++u32 cdns_mhdp_bus_read(struct cdns_mhdp_device *mhdp, u32 offset) ++{ ++ u32 val; ++ ++ mutex_lock(&mhdp->iolock); ++ ++ if (mhdp->bus_type == BUS_TYPE_LOW4K_SAPB) { ++ /* Remap address to low 4K SAPB bus */ ++ writel(offset >> 12, mhdp->regs_sec + 0xc); ++ val = readl((offset & 0xfff) + mhdp->regs_base); ++ } else if (mhdp->bus_type == BUS_TYPE_LOW4K_APB) { ++ /* Remap address to low 4K memory */ ++ writel(offset >> 12, mhdp->regs_sec + 8); ++ val = readl((offset & 0xfff) + mhdp->regs_base); ++ } else if (mhdp->bus_type == BUS_TYPE_NORMAL_SAPB) ++ val = readl(mhdp->regs_sec + offset); ++ else ++ val = readl(mhdp->regs_base + offset); ++ ++ mutex_unlock(&mhdp->iolock); ++ ++ return val; ++} ++EXPORT_SYMBOL(cdns_mhdp_bus_read); ++ ++void cdns_mhdp_bus_write(u32 val, struct cdns_mhdp_device *mhdp, u32 offset) ++{ ++ mutex_lock(&mhdp->iolock); ++ ++ if (mhdp->bus_type == BUS_TYPE_LOW4K_SAPB) { ++ /* Remap address to low 4K SAPB bus */ ++ writel(offset >> 12, mhdp->regs_sec + 0xc); ++ writel(val, (offset & 0xfff) + mhdp->regs_base); ++ } else if (mhdp->bus_type == BUS_TYPE_LOW4K_APB) { ++ /* Remap address to low 4K memory */ ++ writel(offset >> 12, mhdp->regs_sec + 8); ++ writel(val, (offset & 0xfff) + mhdp->regs_base); ++ } else if (mhdp->bus_type == BUS_TYPE_NORMAL_SAPB) ++ writel(val, mhdp->regs_sec + offset); ++ else ++ writel(val, mhdp->regs_base + offset); ++ ++ mutex_unlock(&mhdp->iolock); ++} ++EXPORT_SYMBOL(cdns_mhdp_bus_write); ++ ++u32 cdns_mhdp_get_fw_clk(struct cdns_mhdp_device *mhdp) ++{ ++ return cdns_mhdp_bus_read(mhdp, SW_CLK_H); ++} ++EXPORT_SYMBOL(cdns_mhdp_get_fw_clk); ++ ++void cdns_mhdp_set_fw_clk(struct cdns_mhdp_device *mhdp, unsigned long clk) ++{ ++ cdns_mhdp_bus_write(clk / 1000000, mhdp, SW_CLK_H); ++} ++EXPORT_SYMBOL(cdns_mhdp_set_fw_clk); ++ ++void cdns_mhdp_clock_reset(struct cdns_mhdp_device *mhdp) ++{ ++ u32 val; ++ printk(KERN_ALERT "DEBUG: %s %d \n",__FUNCTION__,__LINE__); ++ ++ val = DPTX_FRMR_DATA_CLK_RSTN_EN | ++ DPTX_FRMR_DATA_CLK_EN | ++ DPTX_PHY_DATA_RSTN_EN | ++ DPTX_PHY_DATA_CLK_EN | ++ DPTX_PHY_CHAR_RSTN_EN | ++ DPTX_PHY_CHAR_CLK_EN | ++ SOURCE_AUX_SYS_CLK_RSTN_EN | ++ SOURCE_AUX_SYS_CLK_EN | ++ DPTX_SYS_CLK_RSTN_EN | ++ DPTX_SYS_CLK_EN | ++ CFG_DPTX_VIF_CLK_RSTN_EN | ++ CFG_DPTX_VIF_CLK_EN; ++ cdns_mhdp_bus_write(val, mhdp, SOURCE_DPTX_CAR); ++ ++ val = SOURCE_PHY_RSTN_EN | SOURCE_PHY_CLK_EN; ++ cdns_mhdp_bus_write(val, mhdp, SOURCE_PHY_CAR); ++ ++ val = SOURCE_PKT_SYS_RSTN_EN | ++ SOURCE_PKT_SYS_CLK_EN | ++ SOURCE_PKT_DATA_RSTN_EN | ++ SOURCE_PKT_DATA_CLK_EN; ++ cdns_mhdp_bus_write(val, mhdp, SOURCE_PKT_CAR); ++ ++ val = SPDIF_CDR_CLK_RSTN_EN | ++ SPDIF_CDR_CLK_EN | ++ SOURCE_AIF_SYS_RSTN_EN | ++ SOURCE_AIF_SYS_CLK_EN | ++ SOURCE_AIF_CLK_RSTN_EN | ++ SOURCE_AIF_CLK_EN; ++ cdns_mhdp_bus_write(val, mhdp, SOURCE_AIF_CAR); ++ ++ val = SOURCE_CIPHER_SYSTEM_CLK_RSTN_EN | ++ SOURCE_CIPHER_SYS_CLK_EN | ++ SOURCE_CIPHER_CHAR_CLK_RSTN_EN | ++ SOURCE_CIPHER_CHAR_CLK_EN; ++ cdns_mhdp_bus_write(val, mhdp, SOURCE_CIPHER_CAR); ++ ++ val = SOURCE_CRYPTO_SYS_CLK_RSTN_EN | ++ SOURCE_CRYPTO_SYS_CLK_EN; ++ cdns_mhdp_bus_write(val, mhdp, SOURCE_CRYPTO_CAR); ++ ++ /* enable Mailbox and PIF interrupt */ ++ cdns_mhdp_bus_write(0, mhdp, APB_INT_MASK); ++} ++EXPORT_SYMBOL(cdns_mhdp_clock_reset); ++ ++int cdns_mhdp_mailbox_read(struct cdns_mhdp_device *mhdp) ++{ ++ int val, ret; ++ ++ ret = mhdp_readx_poll_timeout(cdns_mhdp_bus_read, mhdp, MAILBOX_EMPTY_ADDR, ++ val, !val, MAILBOX_RETRY_US, ++ MAILBOX_TIMEOUT_US); ++ if (ret < 0) ++ return ret; ++ ++ return cdns_mhdp_bus_read(mhdp, MAILBOX0_RD_DATA) & 0xff; ++} ++EXPORT_SYMBOL(cdns_mhdp_mailbox_read); ++ ++static int cdp_dp_mailbox_write(struct cdns_mhdp_device *mhdp, u8 val) ++{ ++ int ret, full; ++ ++ ret = mhdp_readx_poll_timeout(cdns_mhdp_bus_read, mhdp, MAILBOX_FULL_ADDR, ++ full, !full, MAILBOX_RETRY_US, ++ MAILBOX_TIMEOUT_US); ++ if (ret < 0) ++ return ret; ++ ++ cdns_mhdp_bus_write(val, mhdp, MAILBOX0_WR_DATA); ++ ++ return 0; ++} ++ ++int cdns_mhdp_mailbox_validate_receive(struct cdns_mhdp_device *mhdp, ++ u8 module_id, u8 opcode, ++ u16 req_size) ++{ ++ u32 mbox_size, i; ++ u8 header[4]; ++ int ret; ++ ++ /* read the header of the message */ ++ for (i = 0; i < 4; i++) { ++ ret = cdns_mhdp_mailbox_read(mhdp); ++ if (ret < 0) ++ return ret; ++ ++ header[i] = ret; ++ } ++ ++ mbox_size = get_unaligned_be16(header + 2); ++ ++ if (opcode != header[0] || module_id != header[1] || ++ req_size != mbox_size) { ++ /* ++ * If the message in mailbox is not what we want, we need to ++ * clear the mailbox by reading its contents. ++ */ ++ for (i = 0; i < mbox_size; i++) ++ if (cdns_mhdp_mailbox_read(mhdp) < 0) ++ break; ++ ++ return -EINVAL; ++ } ++ ++ return 0; ++} ++EXPORT_SYMBOL(cdns_mhdp_mailbox_validate_receive); ++ ++int cdns_mhdp_mailbox_read_receive(struct cdns_mhdp_device *mhdp, ++ u8 *buff, u16 buff_size) ++{ ++ u32 i; ++ int ret; ++ ++ for (i = 0; i < buff_size; i++) { ++ ret = cdns_mhdp_mailbox_read(mhdp); ++ if (ret < 0) ++ return ret; ++ ++ buff[i] = ret; ++ } ++ ++ return 0; ++} ++EXPORT_SYMBOL(cdns_mhdp_mailbox_read_receive); ++ ++int cdns_mhdp_mailbox_send(struct cdns_mhdp_device *mhdp, u8 module_id, ++ u8 opcode, u16 size, u8 *message) ++{ ++ u8 header[4]; ++ int ret, i; ++ ++ header[0] = opcode; ++ header[1] = module_id; ++ put_unaligned_be16(size, header + 2); ++ ++ for (i = 0; i < 4; i++) { ++ ret = cdp_dp_mailbox_write(mhdp, header[i]); ++ if (ret) ++ return ret; ++ } ++ ++ for (i = 0; i < size; i++) { ++ ret = cdp_dp_mailbox_write(mhdp, message[i]); ++ if (ret) ++ return ret; ++ } ++ ++ return 0; ++} ++EXPORT_SYMBOL(cdns_mhdp_mailbox_send); ++ ++int cdns_mhdp_reg_read(struct cdns_mhdp_device *mhdp, u32 addr) ++{ ++ u8 msg[4], resp[8]; ++ u32 val; ++ int ret; ++ ++ if (addr == 0) { ++ ret = -EINVAL; ++ goto err_reg_read; ++ } ++ ++ put_unaligned_be32(addr, msg); ++ ++ ret = cdns_mhdp_mailbox_send(mhdp, MB_MODULE_ID_GENERAL, ++ GENERAL_READ_REGISTER, ++ sizeof(msg), msg); ++ if (ret) ++ goto err_reg_read; ++ ++ ret = cdns_mhdp_mailbox_validate_receive(mhdp, MB_MODULE_ID_GENERAL, ++ GENERAL_READ_REGISTER, ++ sizeof(resp)); ++ if (ret) ++ goto err_reg_read; ++ ++ ret = cdns_mhdp_mailbox_read_receive(mhdp, resp, sizeof(resp)); ++ if (ret) ++ goto err_reg_read; ++ ++ /* Returned address value should be the same as requested */ ++ if (memcmp(msg, resp, sizeof(msg))) { ++ ret = -EINVAL; ++ goto err_reg_read; ++ } ++ ++ val = get_unaligned_be32(resp + 4); ++ ++ return val; ++err_reg_read: ++ DRM_DEV_ERROR(mhdp->dev, "Failed to read register.\n"); ++ ++ return ret; ++} ++EXPORT_SYMBOL(cdns_mhdp_reg_read); ++ ++int cdns_mhdp_reg_write(struct cdns_mhdp_device *mhdp, u32 addr, u32 val) ++{ ++ u8 msg[8]; ++ ++ put_unaligned_be32(addr, msg); ++ put_unaligned_be32(val, msg + 4); ++ ++ return cdns_mhdp_mailbox_send(mhdp, MB_MODULE_ID_GENERAL, ++ GENERAL_WRITE_REGISTER, sizeof(msg), msg); ++} ++EXPORT_SYMBOL(cdns_mhdp_reg_write); ++ ++int cdns_mhdp_reg_write_bit(struct cdns_mhdp_device *mhdp, u16 addr, ++ u8 start_bit, u8 bits_no, u32 val) ++{ ++ u8 field[8]; ++ ++ put_unaligned_be16(addr, field); ++ field[2] = start_bit; ++ field[3] = bits_no; ++ put_unaligned_be32(val, field + 4); ++ ++ return cdns_mhdp_mailbox_send(mhdp, MB_MODULE_ID_DP_TX, ++ DPTX_WRITE_FIELD, sizeof(field), field); ++} ++EXPORT_SYMBOL(cdns_mhdp_reg_write_bit); ++ ++int cdns_mhdp_dpcd_read(struct cdns_mhdp_device *mhdp, ++ u32 addr, u8 *data, u16 len) ++{ ++ u8 msg[5], reg[5]; ++ int ret; ++ ++ put_unaligned_be16(len, msg); ++ put_unaligned_be24(addr, msg + 2); ++ ++ ret = cdns_mhdp_mailbox_send(mhdp, MB_MODULE_ID_DP_TX, ++ DPTX_READ_DPCD, sizeof(msg), msg); ++ if (ret) ++ goto err_dpcd_read; ++ ++ ret = cdns_mhdp_mailbox_validate_receive(mhdp, MB_MODULE_ID_DP_TX, ++ DPTX_READ_DPCD, ++ sizeof(reg) + len); ++ if (ret) ++ goto err_dpcd_read; ++ ++ ret = cdns_mhdp_mailbox_read_receive(mhdp, reg, sizeof(reg)); ++ if (ret) ++ goto err_dpcd_read; ++ ++ ret = cdns_mhdp_mailbox_read_receive(mhdp, data, len); ++ ++err_dpcd_read: ++ return ret; ++} ++EXPORT_SYMBOL(cdns_mhdp_dpcd_read); ++ ++int cdns_mhdp_dpcd_write(struct cdns_mhdp_device *mhdp, u32 addr, u8 value) ++{ ++ u8 msg[6], reg[5]; ++ int ret; ++ ++ put_unaligned_be16(1, msg); ++ put_unaligned_be24(addr, msg + 2); ++ msg[5] = value; ++ ++ ret = cdns_mhdp_mailbox_send(mhdp, MB_MODULE_ID_DP_TX, ++ DPTX_WRITE_DPCD, sizeof(msg), msg); ++ if (ret) ++ goto err_dpcd_write; ++ ++ ret = cdns_mhdp_mailbox_validate_receive(mhdp, MB_MODULE_ID_DP_TX, ++ DPTX_WRITE_DPCD, sizeof(reg)); ++ if (ret) ++ goto err_dpcd_write; ++ ++ ret = cdns_mhdp_mailbox_read_receive(mhdp, reg, sizeof(reg)); ++ if (ret) ++ goto err_dpcd_write; ++ ++ if (addr != get_unaligned_be24(reg + 2)) ++ ret = -EINVAL; ++ ++err_dpcd_write: ++ if (ret) ++ DRM_DEV_ERROR(mhdp->dev, "dpcd write failed: %d\n", ret); ++ return ret; ++} ++EXPORT_SYMBOL(cdns_mhdp_dpcd_write); ++ ++int cdns_mhdp_load_firmware(struct cdns_mhdp_device *mhdp, const u32 *i_mem, ++ u32 i_size, const u32 *d_mem, u32 d_size) ++{ ++ u32 reg; ++ int i, ret; ++ ++ /* reset ucpu before load firmware*/ ++ cdns_mhdp_bus_write(APB_IRAM_PATH | APB_DRAM_PATH | APB_XT_RESET, ++ mhdp, APB_CTRL); ++ ++ for (i = 0; i < i_size; i += 4) ++ cdns_mhdp_bus_write(*i_mem++, mhdp, ADDR_IMEM + i); ++ ++ for (i = 0; i < d_size; i += 4) ++ cdns_mhdp_bus_write(*d_mem++, mhdp, ADDR_DMEM + i); ++ ++ /* un-reset ucpu */ ++ cdns_mhdp_bus_write(0, mhdp, APB_CTRL); ++ ++ /* check the keep alive register to make sure fw working */ ++ ret = mhdp_readx_poll_timeout(cdns_mhdp_bus_read, mhdp, KEEP_ALIVE, ++ reg, reg, 2000, FW_ALIVE_TIMEOUT_US); ++ if (ret < 0) { ++ DRM_DEV_ERROR(mhdp->dev, "failed to loaded the FW reg = %x\n", ++ reg); ++ return -EINVAL; ++ } ++ ++ reg = cdns_mhdp_bus_read(mhdp, VER_L) & 0xff; ++ mhdp->fw_version = reg; ++ reg = cdns_mhdp_bus_read(mhdp, VER_H) & 0xff; ++ mhdp->fw_version |= reg << 8; ++ reg = cdns_mhdp_bus_read(mhdp, VER_LIB_L_ADDR) & 0xff; ++ mhdp->fw_version |= reg << 16; ++ reg = cdns_mhdp_bus_read(mhdp, VER_LIB_H_ADDR) & 0xff; ++ mhdp->fw_version |= reg << 24; ++ ++ DRM_DEV_DEBUG(mhdp->dev, "firmware version: %x\n", mhdp->fw_version); ++ ++ return 0; ++} ++EXPORT_SYMBOL(cdns_mhdp_load_firmware); ++ ++int cdns_mhdp_set_firmware_active(struct cdns_mhdp_device *mhdp, bool enable) ++{ ++ u8 msg[5]; ++ int ret, i; ++ ++ msg[0] = GENERAL_MAIN_CONTROL; ++ msg[1] = MB_MODULE_ID_GENERAL; ++ msg[2] = 0; ++ msg[3] = 1; ++ msg[4] = enable ? FW_ACTIVE : FW_STANDBY; ++ ++ for (i = 0; i < sizeof(msg); i++) { ++ ret = cdp_dp_mailbox_write(mhdp, msg[i]); ++ if (ret) ++ goto err_set_firmware_active; ++ } ++ ++ /* read the firmware state */ ++ for (i = 0; i < sizeof(msg); i++) { ++ ret = cdns_mhdp_mailbox_read(mhdp); ++ if (ret < 0) ++ goto err_set_firmware_active; ++ ++ msg[i] = ret; ++ } ++ ++ ret = 0; ++ ++err_set_firmware_active: ++ if (ret < 0) ++ DRM_DEV_ERROR(mhdp->dev, "set firmware active failed\n"); ++ return ret; ++} ++EXPORT_SYMBOL(cdns_mhdp_set_firmware_active); ++ ++int cdns_mhdp_set_host_cap(struct cdns_mhdp_device *mhdp, bool flip) ++{ ++ u8 msg[8]; ++ int ret; ++ ++ printk(KERN_ALERT "DEBUG: %s %d \n",__FUNCTION__,__LINE__); ++ ++ msg[0] = drm_dp_link_rate_to_bw_code(mhdp->dp.link.rate); ++ msg[1] = mhdp->dp.link.num_lanes | SCRAMBLER_EN; ++ msg[2] = VOLTAGE_LEVEL_2; ++ msg[3] = PRE_EMPHASIS_LEVEL_3; ++ msg[4] = PTS1 | PTS2 | PTS3 | PTS4; ++ msg[5] = FAST_LT_NOT_SUPPORT; ++ msg[6] = flip ? LANE_MAPPING_FLIPPED : LANE_MAPPING_NORMAL; ++ msg[7] = ENHANCED; ++ ++ ret = cdns_mhdp_mailbox_send(mhdp, MB_MODULE_ID_DP_TX, ++ DPTX_SET_HOST_CAPABILITIES, ++ sizeof(msg), msg); ++ if (ret) ++ goto err_set_host_cap; ++ ++/* TODO Sandor */ ++// ret = cdns_mhdp_reg_write(mhdp, DP_AUX_SWAP_INVERSION_CONTROL, ++// AUX_HOST_INVERT); ++ ++err_set_host_cap: ++ if (ret) ++ DRM_DEV_ERROR(mhdp->dev, "set host cap failed: %d\n", ret); ++ return ret; ++} ++EXPORT_SYMBOL(cdns_mhdp_set_host_cap); ++ ++int cdns_mhdp_event_config(struct cdns_mhdp_device *mhdp) ++{ ++ u8 msg[5]; ++ int ret; ++ ++ memset(msg, 0, sizeof(msg)); ++ ++ msg[0] = MHDP_EVENT_ENABLE_HPD | MHDP_EVENT_ENABLE_TRAINING; ++ ++ ret = cdns_mhdp_mailbox_send(mhdp, MB_MODULE_ID_DP_TX, ++ DPTX_ENABLE_EVENT, sizeof(msg), msg); ++ if (ret) ++ DRM_DEV_ERROR(mhdp->dev, "set event config failed: %d\n", ret); ++ ++ return ret; ++} ++EXPORT_SYMBOL(cdns_mhdp_event_config); ++ ++u32 cdns_mhdp_get_event(struct cdns_mhdp_device *mhdp) ++{ ++ return cdns_mhdp_bus_read(mhdp, SW_EVENTS0); ++} ++EXPORT_SYMBOL(cdns_mhdp_get_event); ++ ++int cdns_mhdp_get_hpd_status(struct cdns_mhdp_device *mhdp) ++{ ++ u8 status; ++ int ret; ++ ++ ret = cdns_mhdp_mailbox_send(mhdp, MB_MODULE_ID_DP_TX, ++ DPTX_HPD_STATE, 0, NULL); ++ if (ret) ++ goto err_get_hpd; ++ ++ ret = cdns_mhdp_mailbox_validate_receive(mhdp, MB_MODULE_ID_DP_TX, ++ DPTX_HPD_STATE, ++ sizeof(status)); ++ if (ret) ++ goto err_get_hpd; ++ ++ ret = cdns_mhdp_mailbox_read_receive(mhdp, &status, sizeof(status)); ++ if (ret) ++ goto err_get_hpd; ++ ++ return status; ++ ++err_get_hpd: ++ DRM_DEV_ERROR(mhdp->dev, "get hpd status failed: %d\n", ret); ++ return ret; ++} ++EXPORT_SYMBOL(cdns_mhdp_get_hpd_status); ++ ++int cdns_mhdp_get_edid_block(void *data, u8 *edid, ++ unsigned int block, size_t length) ++{ ++ struct cdns_mhdp_device *mhdp = data; ++ u8 msg[2], reg[2], i; ++ int ret; ++ ++ for (i = 0; i < 4; i++) { ++ msg[0] = block / 2; ++ msg[1] = block % 2; ++ ++ ret = cdns_mhdp_mailbox_send(mhdp, MB_MODULE_ID_DP_TX, ++ DPTX_GET_EDID, sizeof(msg), msg); ++ if (ret) ++ continue; ++ ++ ret = cdns_mhdp_mailbox_validate_receive(mhdp, ++ MB_MODULE_ID_DP_TX, ++ DPTX_GET_EDID, ++ sizeof(reg) + length); ++ if (ret) ++ continue; ++ ++ ret = cdns_mhdp_mailbox_read_receive(mhdp, reg, sizeof(reg)); ++ if (ret) ++ continue; ++ ++ ret = cdns_mhdp_mailbox_read_receive(mhdp, edid, length); ++ if (ret) ++ continue; ++ ++ if (reg[0] == length && reg[1] == block / 2) ++ break; ++ } ++ ++ if (ret) ++ DRM_DEV_ERROR(mhdp->dev, "get block[%d] edid failed: %d\n", ++ block, ret); ++ ++ return ret; ++} ++EXPORT_SYMBOL(cdns_mhdp_get_edid_block); ++ ++static int cdns_mhdp_training_start(struct cdns_mhdp_device *mhdp) ++{ ++ unsigned long timeout; ++ u8 msg, event[2]; ++ int ret; ++ ++ msg = LINK_TRAINING_RUN; ++ ++ /* start training */ ++ ret = cdns_mhdp_mailbox_send(mhdp, MB_MODULE_ID_DP_TX, ++ DPTX_TRAINING_CONTROL, sizeof(msg), &msg); ++ if (ret) ++ goto err_training_start; ++ ++ timeout = jiffies + msecs_to_jiffies(LINK_TRAINING_TIMEOUT_MS); ++ while (time_before(jiffies, timeout)) { ++ msleep(LINK_TRAINING_RETRY_MS); ++ ret = cdns_mhdp_mailbox_send(mhdp, MB_MODULE_ID_DP_TX, ++ DPTX_READ_EVENT, 0, NULL); ++ if (ret) ++ goto err_training_start; ++ ++ ret = cdns_mhdp_mailbox_validate_receive(mhdp, ++ MB_MODULE_ID_DP_TX, ++ DPTX_READ_EVENT, ++ sizeof(event)); ++ if (ret) ++ goto err_training_start; ++ ++ ret = cdns_mhdp_mailbox_read_receive(mhdp, event, ++ sizeof(event)); ++ if (ret) ++ goto err_training_start; ++ ++ if (event[1] & EQ_PHASE_FINISHED) ++ return 0; ++ } ++ ++ ret = -ETIMEDOUT; ++ ++err_training_start: ++ DRM_DEV_ERROR(mhdp->dev, "training failed: %d\n", ret); ++ return ret; ++} ++ ++static int cdns_mhdp_get_training_status(struct cdns_mhdp_device *mhdp) ++{ ++ u8 status[10]; ++ int ret; ++ ++ ret = cdns_mhdp_mailbox_send(mhdp, MB_MODULE_ID_DP_TX, ++ DPTX_READ_LINK_STAT, 0, NULL); ++ if (ret) ++ goto err_get_training_status; ++ ++ ret = cdns_mhdp_mailbox_validate_receive(mhdp, MB_MODULE_ID_DP_TX, ++ DPTX_READ_LINK_STAT, ++ sizeof(status)); ++ if (ret) ++ goto err_get_training_status; ++ ++ ret = cdns_mhdp_mailbox_read_receive(mhdp, status, sizeof(status)); ++ if (ret) ++ goto err_get_training_status; ++ ++ mhdp->dp.link.rate = drm_dp_bw_code_to_link_rate(status[0]); ++ mhdp->dp.link.num_lanes = status[1]; ++ ++err_get_training_status: ++ if (ret) ++ DRM_DEV_ERROR(mhdp->dev, "get training status failed: %d\n", ++ ret); ++ return ret; ++} ++ ++int cdns_mhdp_train_link(struct cdns_mhdp_device *mhdp) ++{ ++ int ret; ++ ++ ret = cdns_mhdp_training_start(mhdp); ++ if (ret) { ++ DRM_DEV_ERROR(mhdp->dev, "Failed to start training %d\n", ++ ret); ++ return ret; ++ } ++ ++ ret = cdns_mhdp_get_training_status(mhdp); ++ if (ret) { ++ DRM_DEV_ERROR(mhdp->dev, "Failed to get training stat %d\n", ++ ret); ++ return ret; ++ } ++ ++ DRM_DEV_DEBUG_KMS(mhdp->dev, "rate:0x%x, lanes:%d\n", mhdp->dp.link.rate, ++ mhdp->dp.link.num_lanes); ++ return ret; ++} ++EXPORT_SYMBOL(cdns_mhdp_train_link); ++ ++int cdns_mhdp_set_video_status(struct cdns_mhdp_device *mhdp, int active) ++{ ++ u8 msg; ++ int ret; ++ ++ msg = !!active; ++ ++ ret = cdns_mhdp_mailbox_send(mhdp, MB_MODULE_ID_DP_TX, ++ DPTX_SET_VIDEO, sizeof(msg), &msg); ++ if (ret) ++ DRM_DEV_ERROR(mhdp->dev, "set video status failed: %d\n", ret); ++ ++ return ret; ++} ++EXPORT_SYMBOL(cdns_mhdp_set_video_status); ++ ++static int cdns_mhdp_get_msa_misc(struct video_info *video, ++ struct drm_display_mode *mode) ++{ ++ u32 msa_misc; ++ u8 val[2] = {0}; ++ ++ switch (video->color_fmt) { ++ case PXL_RGB: ++ case Y_ONLY: ++ val[0] = 0; ++ break; ++ /* set YUV default color space conversion to BT601 */ ++ case YCBCR_4_4_4: ++ val[0] = 6 + BT_601 * 8; ++ break; ++ case YCBCR_4_2_2: ++ val[0] = 5 + BT_601 * 8; ++ break; ++ case YCBCR_4_2_0: ++ val[0] = 5; ++ break; ++ }; ++ ++ switch (video->color_depth) { ++ case 6: ++ val[1] = 0; ++ break; ++ case 8: ++ val[1] = 1; ++ break; ++ case 10: ++ val[1] = 2; ++ break; ++ case 12: ++ val[1] = 3; ++ break; ++ case 16: ++ val[1] = 4; ++ break; ++ }; ++ ++ msa_misc = 2 * val[0] + 32 * val[1] + ++ ((video->color_fmt == Y_ONLY) ? (1 << 14) : 0); ++ ++ return msa_misc; ++} ++ ++int cdns_mhdp_config_video(struct cdns_mhdp_device *mhdp) ++{ ++ struct video_info *video = &mhdp->video_info; ++ struct drm_display_mode *mode = &mhdp->mode; ++ u64 symbol; ++ u32 val, link_rate, rem; ++ u8 bit_per_pix, tu_size_reg = TU_SIZE; ++ int ret; ++ ++ bit_per_pix = (video->color_fmt == YCBCR_4_2_2) ? ++ (video->color_depth * 2) : (video->color_depth * 3); ++ ++ link_rate = mhdp->dp.link.rate / 1000; ++ ++ ret = cdns_mhdp_reg_write(mhdp, BND_HSYNC2VSYNC, VIF_BYPASS_INTERLACE); ++ if (ret) ++ goto err_config_video; ++ ++ ret = cdns_mhdp_reg_write(mhdp, HSYNC2VSYNC_POL_CTRL, 0); ++ if (ret) ++ goto err_config_video; ++ ++ /* ++ * get a best tu_size and valid symbol: ++ * 1. chose Lclk freq(162Mhz, 270Mhz, 540Mhz), set TU to 32 ++ * 2. calculate VS(valid symbol) = TU * Pclk * Bpp / (Lclk * Lanes) ++ * 3. if VS > *.85 or VS < *.1 or VS < 2 or TU < VS + 4, then set ++ * TU += 2 and repeat 2nd step. ++ */ ++ do { ++ tu_size_reg += 2; ++ symbol = tu_size_reg * mode->clock * bit_per_pix; ++ do_div(symbol, mhdp->dp.link.num_lanes * link_rate * 8); ++ rem = do_div(symbol, 1000); ++ if (tu_size_reg > 64) { ++ ret = -EINVAL; ++ DRM_DEV_ERROR(mhdp->dev, ++ "tu error, clk:%d, lanes:%d, rate:%d\n", ++ mode->clock, mhdp->dp.link.num_lanes, ++ link_rate); ++ goto err_config_video; ++ } ++ } while ((symbol <= 1) || (tu_size_reg - symbol < 4) || ++ (rem > 850) || (rem < 100)); ++ ++ val = symbol + (tu_size_reg << 8); ++ val |= TU_CNT_RST_EN; ++ ret = cdns_mhdp_reg_write(mhdp, DP_FRAMER_TU, val); ++ if (ret) ++ goto err_config_video; ++ ++ /* set the FIFO Buffer size */ ++ val = div_u64(mode->clock * (symbol + 1), 1000) + link_rate; ++ val /= (mhdp->dp.link.num_lanes * link_rate); ++ val = div_u64(8 * (symbol + 1), bit_per_pix) - val; ++ val += 2; ++ ret = cdns_mhdp_reg_write(mhdp, DP_VC_TABLE(15), val); ++ ++ switch (video->color_depth) { ++ case 6: ++ val = BCS_6; ++ break; ++ case 8: ++ val = BCS_8; ++ break; ++ case 10: ++ val = BCS_10; ++ break; ++ case 12: ++ val = BCS_12; ++ break; ++ case 16: ++ val = BCS_16; ++ break; ++ }; ++ ++ val += video->color_fmt << 8; ++ ret = cdns_mhdp_reg_write(mhdp, DP_FRAMER_PXL_REPR, val); ++ if (ret) ++ goto err_config_video; ++ ++ val = video->h_sync_polarity ? DP_FRAMER_SP_HSP : 0; ++ val |= video->v_sync_polarity ? DP_FRAMER_SP_VSP : 0; ++ ret = cdns_mhdp_reg_write(mhdp, DP_FRAMER_SP, val); ++ if (ret) ++ goto err_config_video; ++ ++ val = (mode->hsync_start - mode->hdisplay) << 16; ++ val |= mode->htotal - mode->hsync_end; ++ ret = cdns_mhdp_reg_write(mhdp, DP_FRONT_BACK_PORCH, val); ++ if (ret) ++ goto err_config_video; ++ ++ val = mode->hdisplay * bit_per_pix / 8; ++ ret = cdns_mhdp_reg_write(mhdp, DP_BYTE_COUNT, val); ++ if (ret) ++ goto err_config_video; ++ ++ val = mode->htotal | ((mode->htotal - mode->hsync_start) << 16); ++ ret = cdns_mhdp_reg_write(mhdp, MSA_HORIZONTAL_0, val); ++ if (ret) ++ goto err_config_video; ++ ++ val = mode->hsync_end - mode->hsync_start; ++ val |= (mode->hdisplay << 16) | (video->h_sync_polarity << 15); ++ ret = cdns_mhdp_reg_write(mhdp, MSA_HORIZONTAL_1, val); ++ if (ret) ++ goto err_config_video; ++ ++ val = mode->vtotal; ++ val |= (mode->vtotal - mode->vsync_start) << 16; ++ ret = cdns_mhdp_reg_write(mhdp, MSA_VERTICAL_0, val); ++ if (ret) ++ goto err_config_video; ++ ++ val = mode->vsync_end - mode->vsync_start; ++ val |= (mode->vdisplay << 16) | (video->v_sync_polarity << 15); ++ ret = cdns_mhdp_reg_write(mhdp, MSA_VERTICAL_1, val); ++ if (ret) ++ goto err_config_video; ++ ++ val = cdns_mhdp_get_msa_misc(video, mode); ++ ret = cdns_mhdp_reg_write(mhdp, MSA_MISC, val); ++ if (ret) ++ goto err_config_video; ++ ++ ret = cdns_mhdp_reg_write(mhdp, STREAM_CONFIG, 1); ++ if (ret) ++ goto err_config_video; ++ ++ val = mode->hsync_end - mode->hsync_start; ++ val |= mode->hdisplay << 16; ++ ret = cdns_mhdp_reg_write(mhdp, DP_HORIZONTAL, val); ++ if (ret) ++ goto err_config_video; ++ ++ val = mode->vdisplay; ++ val |= (mode->vtotal - mode->vsync_start) << 16; ++ ret = cdns_mhdp_reg_write(mhdp, DP_VERTICAL_0, val); ++ if (ret) ++ goto err_config_video; ++ ++ val = mode->vtotal; ++ ret = cdns_mhdp_reg_write(mhdp, DP_VERTICAL_1, val); ++ if (ret) ++ goto err_config_video; ++ ++ ret = cdns_mhdp_reg_write_bit(mhdp, DP_VB_ID, 2, 1, 0); ++ ++err_config_video: ++ if (ret) ++ DRM_DEV_ERROR(mhdp->dev, "config video failed: %d\n", ret); ++ return ret; ++} ++EXPORT_SYMBOL(cdns_mhdp_config_video); ++ ++int cdns_mhdp_adjust_lt(struct cdns_mhdp_device *mhdp, ++ u8 nlanes, u16 udelay, u8 *lanes_data, u8 *dpcd) ++{ ++ u8 payload[7]; ++ u8 hdr[5]; /* For DPCD read response header */ ++ u32 addr; ++ u8 const nregs = 6; /* Registers 0x202-0x207 */ ++ int ret; ++ ++ if (nlanes != 4 && nlanes != 2 && nlanes != 1) { ++ DRM_DEV_ERROR(mhdp->dev, "invalid number of lanes: %d\n", ++ nlanes); ++ ret = -EINVAL; ++ goto err_adjust_lt; ++ } ++ ++ payload[0] = nlanes; ++ put_unaligned_be16(udelay, payload + 1); ++ memcpy(payload + 3, lanes_data, nlanes); ++ ++ ret = cdns_mhdp_mailbox_send(mhdp, MB_MODULE_ID_DP_TX, ++ DPTX_ADJUST_LT, ++ sizeof(payload), payload); ++ if (ret) ++ goto err_adjust_lt; ++ ++ /* Yes, read the DPCD read command response */ ++ ret = cdns_mhdp_mailbox_validate_receive(mhdp, MB_MODULE_ID_DP_TX, ++ DPTX_READ_DPCD, ++ sizeof(hdr) + nregs); ++ if (ret) ++ goto err_adjust_lt; ++ ++ ret = cdns_mhdp_mailbox_read_receive(mhdp, hdr, sizeof(hdr)); ++ if (ret) ++ goto err_adjust_lt; ++ ++ addr = get_unaligned_be24(hdr + 2); ++ if (addr != DP_LANE0_1_STATUS) ++ goto err_adjust_lt; ++ ++ ret = cdns_mhdp_mailbox_read_receive(mhdp, dpcd, nregs); ++ ++err_adjust_lt: ++ if (ret) ++ DRM_DEV_ERROR(mhdp->dev, "Failed to adjust Link Training.\n"); ++ ++ return ret; ++} ++EXPORT_SYMBOL(cdns_mhdp_adjust_lt); ++ ++int cdns_phy_reg_write(struct cdns_mhdp_device *mhdp, u32 addr, u32 val) ++{ ++ return cdns_mhdp_reg_write(mhdp, ADDR_PHY_AFE + (addr << 2), val); ++} ++EXPORT_SYMBOL(cdns_phy_reg_write); ++ ++u32 cdns_phy_reg_read(struct cdns_mhdp_device *mhdp, u32 addr) ++{ ++ return cdns_mhdp_reg_read(mhdp, ADDR_PHY_AFE + (addr << 2)); ++} ++EXPORT_SYMBOL(cdns_phy_reg_read); ++ ++int cdns_mhdp_read_hpd(struct cdns_mhdp_device *mhdp) ++{ ++ u8 status; ++ int ret; ++ ++ ret = cdns_mhdp_mailbox_send(mhdp, MB_MODULE_ID_GENERAL, GENERAL_GET_HPD_STATE, ++ 0, NULL); ++ if (ret) ++ goto err_get_hpd; ++ ++ ret = cdns_mhdp_mailbox_validate_receive(mhdp, MB_MODULE_ID_GENERAL, ++ GENERAL_GET_HPD_STATE, sizeof(status)); ++ if (ret) ++ goto err_get_hpd; ++ ++ ret = cdns_mhdp_mailbox_read_receive(mhdp, &status, sizeof(status)); ++ if (ret) ++ goto err_get_hpd; ++ ++ return status; ++ ++err_get_hpd: ++ DRM_ERROR("read hpd failed: %d\n", ret); ++ return ret; ++} ++EXPORT_SYMBOL(cdns_mhdp_read_hpd); ++ ++bool cdns_mhdp_check_alive(struct cdns_mhdp_device *mhdp) ++{ ++ u32 alive, newalive; ++ u8 retries_left = 50; ++ ++ alive = cdns_mhdp_bus_read(mhdp, KEEP_ALIVE); ++ ++ while (retries_left--) { ++ udelay(2); ++ ++ newalive = cdns_mhdp_bus_read(mhdp, KEEP_ALIVE); ++ if (alive == newalive) ++ continue; ++ return true; ++ } ++ return false; ++} ++EXPORT_SYMBOL(cdns_mhdp_check_alive); +diff --git a/drivers/gpu/drm/bridge/cadence/cdns-mhdp-hdmi.c b/drivers/gpu/drm/bridge/cadence/cdns-mhdp-hdmi.c +new file mode 100644 +index 000000000000..9773202e0651 +--- /dev/null ++++ b/drivers/gpu/drm/bridge/cadence/cdns-mhdp-hdmi.c +@@ -0,0 +1,357 @@ ++/* ++ * Copyright (C) 2019 NXP Semiconductor, Inc. ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License as published by ++ * the Free Software Foundation; either version 2 of the License, or ++ * (at your option) any later version. ++ */ ++ ++#include ++#include ++#include ++ ++void cdns_mhdp_infoframe_set(struct cdns_mhdp_device *mhdp, ++ u8 entry_id, u8 packet_len, u8 *packet, u8 packet_type) ++{ ++ u32 *packet32, len32; ++ u32 val, i; ++ ++ printk(KERN_ALERT "DEBUG: %s %d \n",__FUNCTION__,__LINE__); ++ ++ /* invalidate entry */ ++ val = F_ACTIVE_IDLE_TYPE(1) | F_PKT_ALLOC_ADDRESS(entry_id); ++ cdns_mhdp_bus_write(val, mhdp, SOURCE_PIF_PKT_ALLOC_REG); ++ cdns_mhdp_bus_write(F_PKT_ALLOC_WR_EN(1), mhdp, SOURCE_PIF_PKT_ALLOC_WR_EN); ++ ++ /* flush fifo 1 */ ++ cdns_mhdp_bus_write(F_FIFO1_FLUSH(1), mhdp, SOURCE_PIF_FIFO1_FLUSH); ++ ++ /* write packet into memory */ ++ packet32 = (u32 *)packet; ++ len32 = packet_len / 4; ++ for (i = 0; i < len32; i++) ++ cdns_mhdp_bus_write(F_DATA_WR(packet32[i]), mhdp, SOURCE_PIF_DATA_WR); ++ ++ /* write entry id */ ++ cdns_mhdp_bus_write(F_WR_ADDR(entry_id), mhdp, SOURCE_PIF_WR_ADDR); ++ ++ /* write request */ ++ cdns_mhdp_bus_write(F_HOST_WR(1), mhdp, SOURCE_PIF_WR_REQ); ++ ++ /* update entry */ ++ val = F_ACTIVE_IDLE_TYPE(1) | F_TYPE_VALID(1) | ++ F_PACKET_TYPE(packet_type) | F_PKT_ALLOC_ADDRESS(entry_id); ++ cdns_mhdp_bus_write(val, mhdp, SOURCE_PIF_PKT_ALLOC_REG); ++ ++ cdns_mhdp_bus_write(F_PKT_ALLOC_WR_EN(1), mhdp, SOURCE_PIF_PKT_ALLOC_WR_EN); ++} ++ ++int cdns_hdmi_get_edid_block(void *data, u8 *edid, ++ u32 block, size_t length) ++{ ++ struct cdns_mhdp_device *mhdp = data; ++ u8 msg[2], reg[5], i; ++ int ret; ++ ++ for (i = 0; i < 4; i++) { ++ msg[0] = block / 2; ++ msg[1] = block % 2; ++ ++ ret = cdns_mhdp_mailbox_send(mhdp, MB_MODULE_ID_HDMI_TX, HDMI_TX_EDID, ++ sizeof(msg), msg); ++ if (ret) ++ continue; ++ ++ ret = cdns_mhdp_mailbox_validate_receive(mhdp, MB_MODULE_ID_HDMI_TX, ++ HDMI_TX_EDID, sizeof(reg) + length); ++ if (ret) ++ continue; ++ ++ ret = cdns_mhdp_mailbox_read_receive(mhdp, reg, sizeof(reg)); ++ if (ret) ++ continue; ++ ++ ret = cdns_mhdp_mailbox_read_receive(mhdp, edid, length); ++ if (ret) ++ continue; ++ ++ if ((reg[3] << 8 | reg[4]) == length) ++ break; ++ } ++ ++ if (ret) ++ printk(KERN_ALERT "cdns-mhdp-hdmi: get block[%d] edid failed: %d\n", block, ret); ++ //DRM_ERROR("get block[%d] edid failed: %d\n", block, ret); ++ return ret; ++} ++ ++int cdns_hdmi_scdc_read(struct cdns_mhdp_device *mhdp, u8 addr, u8 *data) ++{ ++ u8 msg[4], reg[6]; ++ int ret; ++ ++ msg[0] = 0x54; ++ msg[1] = addr; ++ msg[2] = 0; ++ msg[3] = 1; ++ ret = cdns_mhdp_mailbox_send(mhdp, MB_MODULE_ID_HDMI_TX, HDMI_TX_READ, ++ sizeof(msg), msg); ++ if (ret) ++ goto err_scdc_read; ++ ++ ret = cdns_mhdp_mailbox_validate_receive(mhdp, MB_MODULE_ID_HDMI_TX, ++ HDMI_TX_READ, sizeof(reg)); ++ if (ret) ++ goto err_scdc_read; ++ ++ ret = cdns_mhdp_mailbox_read_receive(mhdp, reg, sizeof(reg)); ++ if (ret) ++ goto err_scdc_read; ++ ++ *data = reg[5]; ++ ++err_scdc_read: ++ if (ret) ++ printk(KERN_ALERT "cdns-mhdp-hdmi: scdc read failed: %d\n", ret); ++ //DRM_ERROR("scdc read failed: %d\n", ret); ++ return ret; ++} ++ ++int cdns_hdmi_scdc_write(struct cdns_mhdp_device *mhdp, u8 addr, u8 value) ++{ ++ u8 msg[5], reg[5]; ++ int ret; ++ ++ msg[0] = 0x54; ++ msg[1] = addr; ++ msg[2] = 0; ++ msg[3] = 1; ++ msg[4] = value; ++ ret = cdns_mhdp_mailbox_send(mhdp, MB_MODULE_ID_HDMI_TX, HDMI_TX_WRITE, ++ sizeof(msg), msg); ++ if (ret) ++ goto err_scdc_write; ++ ++ ret = cdns_mhdp_mailbox_validate_receive(mhdp, MB_MODULE_ID_HDMI_TX, ++ HDMI_TX_WRITE, sizeof(reg)); ++ if (ret) ++ goto err_scdc_write; ++ ++ ret = cdns_mhdp_mailbox_read_receive(mhdp, reg, sizeof(reg)); ++ if (ret) ++ goto err_scdc_write; ++ ++ if (reg[0] != 0) ++ ret = -EINVAL; ++ ++err_scdc_write: ++ if (ret) ++ printk(KERN_ALERT "cdns-mhdp-hdmi: scdc write failed: %d\n", ret); ++ //DRM_ERROR("scdc write failed: %d\n", ret); ++ return ret; ++} ++ ++int cdns_hdmi_ctrl_init(struct cdns_mhdp_device *mhdp, ++ int protocol, ++ u32 char_rate) ++{ ++ u32 reg0; ++ u32 reg1; ++ u32 val; ++ int ret; ++ ++ printk(KERN_ALERT "DEBUG: %s %d proto: %d char_rate: %ul \n",__FUNCTION__,__LINE__,protocol,char_rate); ++ ++ /* Set PHY to HDMI data */ ++ ret = cdns_mhdp_reg_write(mhdp, PHY_DATA_SEL, F_SOURCE_PHY_MHDP_SEL(1)); ++ if (ret < 0) ++ return ret; ++ ++ printk(KERN_ALERT "DEBUG: %s %d \n",__FUNCTION__,__LINE__); ++ ++ ret = cdns_mhdp_reg_write(mhdp, HDTX_HPD, ++ F_HPD_VALID_WIDTH(4) | F_HPD_GLITCH_WIDTH(0)); ++ if (ret < 0) ++ return ret; ++ ++ printk(KERN_ALERT "DEBUG: %s %d \n",__FUNCTION__,__LINE__); ++ ++ /* open CARS */ ++ ret = cdns_mhdp_reg_write(mhdp, SOURCE_PHY_CAR, 0xF); ++ if (ret < 0) ++ return ret; ++ ret = cdns_mhdp_reg_write(mhdp, SOURCE_HDTX_CAR, 0xFF); ++ if (ret < 0) ++ return ret; ++ ret = cdns_mhdp_reg_write(mhdp, SOURCE_PKT_CAR, 0xF); ++ if (ret < 0) ++ return ret; ++ ret = cdns_mhdp_reg_write(mhdp, SOURCE_AIF_CAR, 0xF); ++ if (ret < 0) ++ return ret; ++ ret = cdns_mhdp_reg_write(mhdp, SOURCE_CIPHER_CAR, 0xF); ++ if (ret < 0) ++ return ret; ++ ret = cdns_mhdp_reg_write(mhdp, SOURCE_CRYPTO_CAR, 0xF); ++ if (ret < 0) ++ return ret; ++ ret = cdns_mhdp_reg_write(mhdp, SOURCE_CEC_CAR, 3); ++ if (ret < 0) ++ return ret; ++ ++ printk(KERN_ALERT "DEBUG: %s %d \n",__FUNCTION__,__LINE__); ++ ++ reg0 = reg1 = 0x7c1f; ++ if (protocol == MODE_HDMI_2_0 && char_rate >= 340000) { ++ reg0 = 0; ++ reg1 = 0xFFFFF; ++ } ++ ret = cdns_mhdp_reg_write(mhdp, HDTX_CLOCK_REG_0, reg0); ++ if (ret < 0) ++ return ret; ++ ret = cdns_mhdp_reg_write(mhdp, HDTX_CLOCK_REG_1, reg1); ++ if (ret < 0) ++ return ret; ++ ++ printk(KERN_ALERT "DEBUG: %s %d \n",__FUNCTION__,__LINE__); ++ ++ /* set hdmi mode and preemble mode data enable */ ++ val = F_HDMI_MODE(protocol) | F_HDMI2_PREAMBLE_EN(1) | F_DATA_EN(1) | ++ F_HDMI2_CTRL_IL_MODE(1) | F_BCH_EN(1) | F_PIC_3D(0XF); ++ ret = cdns_mhdp_reg_write(mhdp, HDTX_CONTROLLER, val); ++ ++ printk(KERN_ALERT "DEBUG: %s %d \n",__FUNCTION__,__LINE__); ++ ++ return ret; ++} ++ ++int cdns_hdmi_mode_config(struct cdns_mhdp_device *mhdp, ++ struct drm_display_mode *mode, ++ struct video_info *video_info) ++{ ++ int ret; ++ u32 val; ++ u32 vsync_lines = mode->vsync_end - mode->vsync_start; ++ u32 eof_lines = mode->vsync_start - mode->vdisplay; ++ u32 sof_lines = mode->vtotal - mode->vsync_end; ++ u32 hblank = mode->htotal - mode->hdisplay; ++ u32 hactive = mode->hdisplay; ++ u32 vblank = mode->vtotal - mode->vdisplay; ++ u32 vactive = mode->vdisplay; ++ u32 hfront = mode->hsync_start - mode->hdisplay; ++ u32 hback = mode->htotal - mode->hsync_end; ++ u32 vfront = eof_lines; ++ u32 hsync = hblank - hfront - hback; ++ u32 vsync = vsync_lines; ++ u32 vback = sof_lines; ++ u32 v_h_polarity = ((mode->flags & DRM_MODE_FLAG_NHSYNC) ? 0 : 1) + ++ ((mode->flags & DRM_MODE_FLAG_NVSYNC) ? 0 : 2); ++ ++ printk(KERN_ALERT "DEBUG: %s %d \n",__FUNCTION__,__LINE__); ++ ++ ret = cdns_mhdp_reg_write(mhdp, SCHEDULER_H_SIZE, (hactive << 16) + hblank); ++ if (ret < 0) ++ return ret; ++ ++ ret = cdns_mhdp_reg_write(mhdp, SCHEDULER_V_SIZE, (vactive << 16) + vblank); ++ if (ret < 0) ++ return ret; ++ ++ ret = cdns_mhdp_reg_write(mhdp, HDTX_SIGNAL_FRONT_WIDTH, (vfront << 16) + hfront); ++ if (ret < 0) ++ return ret; ++ ++ ret = cdns_mhdp_reg_write(mhdp, HDTX_SIGNAL_SYNC_WIDTH, (vsync << 16) + hsync); ++ if (ret < 0) ++ return ret; ++ ++ ret = cdns_mhdp_reg_write(mhdp, HDTX_SIGNAL_BACK_WIDTH, (vback << 16) + hback); ++ if (ret < 0) ++ return ret; ++ ++ ret = cdns_mhdp_reg_write(mhdp, HSYNC2VSYNC_POL_CTRL, v_h_polarity); ++ if (ret < 0) ++ return ret; ++ ++ printk(KERN_ALERT "DEBUG: %s %d mode: %d x %d h: %d %d %d v: %d %d %d pol: %d\n",__FUNCTION__,__LINE__,hactive,vactive,hfront,hsync,hback,vfront, ++ vsync,vback,v_h_polarity); ++ ++ /* Reset Data Enable */ ++ val = cdns_mhdp_reg_read(mhdp, HDTX_CONTROLLER); ++ val &= ~F_DATA_EN(1); ++ ret = cdns_mhdp_reg_write(mhdp, HDTX_CONTROLLER, val); ++ if (ret < 0) ++ return ret; ++ printk(KERN_ALERT "DEBUG: %s %d \n",__FUNCTION__,__LINE__); ++ ++ /* Set bpc */ ++ val &= ~F_VIF_DATA_WIDTH(3); ++ switch (video_info->color_depth) { ++ case 10: ++ val |= F_VIF_DATA_WIDTH(1); ++ break; ++ case 12: ++ val |= F_VIF_DATA_WIDTH(2); ++ break; ++ case 16: ++ val |= F_VIF_DATA_WIDTH(3); ++ break; ++ case 8: ++ default: ++ val |= F_VIF_DATA_WIDTH(0); ++ break; ++ } ++ printk(KERN_ALERT "DEBUG: %s %d BPC: %d\n",__FUNCTION__,__LINE__,video_info->color_depth); ++ ++ /* select color encoding */ ++ val &= ~F_HDMI_ENCODING(3); ++ switch (video_info->color_fmt) { ++ case YCBCR_4_4_4: ++ val |= F_HDMI_ENCODING(2); ++ break; ++ case YCBCR_4_2_2: ++ val |= F_HDMI_ENCODING(1); ++ break; ++ case YCBCR_4_2_0: ++ val |= F_HDMI_ENCODING(3); ++ break; ++ case PXL_RGB: ++ default: ++ val |= F_HDMI_ENCODING(0); ++ break; ++ } ++ printk(KERN_ALERT "DEBUG: %s %d color: %d\n",__FUNCTION__,__LINE__,video_info->color_fmt); ++ ++ ret = cdns_mhdp_reg_write(mhdp, HDTX_CONTROLLER, val); ++ if (ret < 0) ++ return ret; ++ ++ /* set data enable */ ++ val |= F_DATA_EN(1); ++ ret = cdns_mhdp_reg_write(mhdp, HDTX_CONTROLLER, val); ++ ++ printk(KERN_ALERT "DEBUG: %s %d \n",__FUNCTION__,__LINE__); ++ ++ return ret; ++} ++ ++int cdns_hdmi_disable_gcp(struct cdns_mhdp_device *mhdp) ++{ ++ u32 val; ++ ++ val = cdns_mhdp_reg_read(mhdp, HDTX_CONTROLLER); ++ val &= ~F_GCP_EN(1); ++ ++ return cdns_mhdp_reg_write(mhdp, HDTX_CONTROLLER, val); ++} ++ ++int cdns_hdmi_enable_gcp(struct cdns_mhdp_device *mhdp) ++{ ++ u32 val; ++ ++ val = cdns_mhdp_reg_read(mhdp, HDTX_CONTROLLER); ++ val |= F_GCP_EN(1); ++ ++ return cdns_mhdp_reg_write(mhdp, HDTX_CONTROLLER, val); ++} +diff --git a/drivers/gpu/drm/bridge/cadence/cdns-mhdp.h b/drivers/gpu/drm/bridge/cadence/cdns-mhdp.h +new file mode 100644 +index 000000000000..399c3f6f86ad +--- /dev/null ++++ b/drivers/gpu/drm/bridge/cadence/cdns-mhdp.h +@@ -0,0 +1,209 @@ ++/* SPDX-License-Identifier: GPL-2.0 */ ++/* ++ * Cadence MHDP DP MST bridge driver. ++ * ++ * Copyright: 2018 Cadence Design Systems, Inc. ++ * ++ * Author: Quentin Schulz ++ */ ++ ++ ++#ifndef CDNS_MHDP_H ++#define CDNS_MHDP_H ++ ++#include ++ ++#define CDNS_APB_CFG 0x00000 ++#define CDNS_APB_CTRL (CDNS_APB_CFG + 0x00) ++#define CDNS_MAILBOX_FULL (CDNS_APB_CFG + 0x08) ++#define CDNS_MAILBOX_EMPTY (CDNS_APB_CFG + 0x0c) ++#define CDNS_MAILBOX_TX_DATA (CDNS_APB_CFG + 0x10) ++#define CDNS_MAILBOX_RX_DATA (CDNS_APB_CFG + 0x14) ++#define CDNS_KEEP_ALIVE (CDNS_APB_CFG + 0x18) ++#define CDNS_KEEP_ALIVE_MASK GENMASK(7, 0) ++ ++#define CDNS_MB_INT_MASK (CDNS_APB_CFG + 0x34) ++ ++#define CDNS_SW_CLK_L (CDNS_APB_CFG + 0x3c) ++#define CDNS_SW_CLK_H (CDNS_APB_CFG + 0x40) ++#define CDNS_SW_EVENT0 (CDNS_APB_CFG + 0x44) ++#define CDNS_DPTX_HPD BIT(0) ++ ++#define CDNS_SW_EVENT1 (CDNS_APB_CFG + 0x48) ++#define CDNS_SW_EVENT2 (CDNS_APB_CFG + 0x4c) ++#define CDNS_SW_EVENT3 (CDNS_APB_CFG + 0x50) ++ ++#define CDNS_APB_INT_MASK (CDNS_APB_CFG + 0x6C) ++#define CDNS_APB_INT_MASK_MAILBOX_INT BIT(0) ++#define CDNS_APB_INT_MASK_SW_EVENT_INT BIT(1) ++ ++#define CDNS_DPTX_CAR (CDNS_APB_CFG + 0x904) ++#define CDNS_VIF_CLK_EN BIT(0) ++#define CDNS_VIF_CLK_RSTN BIT(1) ++ ++#define CDNS_SOURCE_VIDEO_IF(s) (0x00b00 + (s * 0x20)) ++#define CDNS_BND_HSYNC2VSYNC(s) (CDNS_SOURCE_VIDEO_IF(s) + \ ++ 0x00) ++#define CDNS_IP_DTCT_WIN GENMASK(11, 0) ++#define CDNS_IP_DET_INTERLACE_FORMAT BIT(12) ++#define CDNS_IP_BYPASS_V_INTERFACE BIT(13) ++ ++#define CDNS_HSYNC2VSYNC_POL_CTRL(s) (CDNS_SOURCE_VIDEO_IF(s) + \ ++ 0x10) ++#define CDNS_H2V_HSYNC_POL_ACTIVE_LOW BIT(1) ++#define CDNS_H2V_VSYNC_POL_ACTIVE_LOW BIT(2) ++ ++#define CDNS_DPTX_PHY_CONFIG 0x02000 ++#define CDNS_PHY_TRAINING_EN BIT(0) ++#define CDNS_PHY_TRAINING_TYPE(x) (((x) & GENMASK(3, 0)) << 1) ++#define CDNS_PHY_SCRAMBLER_BYPASS BIT(5) ++#define CDNS_PHY_ENCODER_BYPASS BIT(6) ++#define CDNS_PHY_SKEW_BYPASS BIT(7) ++#define CDNS_PHY_TRAINING_AUTO BIT(8) ++#define CDNS_PHY_LANE0_SKEW(x) (((x) & GENMASK(2, 0)) << 9) ++#define CDNS_PHY_LANE1_SKEW(x) (((x) & GENMASK(2, 0)) << 12) ++#define CDNS_PHY_LANE2_SKEW(x) (((x) & GENMASK(2, 0)) << 15) ++#define CDNS_PHY_LANE3_SKEW(x) (((x) & GENMASK(2, 0)) << 18) ++#define CDNS_PHY_COMMON_CONFIG (CDNS_PHY_LANE1_SKEW(1) | \ ++ CDNS_PHY_LANE2_SKEW(2) | \ ++ CDNS_PHY_LANE3_SKEW(3)) ++#define CDNS_PHY_10BIT_EN BIT(21) ++ ++#define CDNS_DPTX_FRAMER 0x02200 ++#define CDNS_DP_FRAMER_GLOBAL_CONFIG (CDNS_DPTX_FRAMER + 0x00) ++#define CDNS_DP_NUM_LANES(x) (x - 1) ++#define CDNS_DP_MST_EN BIT(2) ++#define CDNS_DP_FRAMER_EN BIT(3) ++#define CDNS_DP_RATE_GOVERNOR_EN BIT(4) ++#define CDNS_DP_NO_VIDEO_MODE BIT(5) ++#define CDNS_DP_DISABLE_PHY_RST BIT(6) ++#define CDNS_DP_WR_FAILING_EDGE_VSYNC BIT(7) ++ ++#define CDNS_DP_SW_RESET (CDNS_DPTX_FRAMER + 0x04) ++#define CDNS_DP_FRAMER_TU (CDNS_DPTX_FRAMER + 0x08) ++#define CDNS_DP_FRAMER_TU_SIZE(x) (((x) & GENMASK(6, 0)) << 8) ++#define CDNS_DP_FRAMER_TU_VS(x) ((x) & GENMASK(5, 0)) ++#define CDNS_DP_FRAMER_TU_CNT_RST_EN BIT(15) ++ ++#define CDNS_DPTX_STREAM(s) (0x03000 + s * 0x80) ++#define CDNS_DP_MSA_HORIZONTAL_0(s) (CDNS_DPTX_STREAM(s) + 0x00) ++#define CDNS_DP_MSAH0_H_TOTAL(x) (x) ++#define CDNS_DP_MSAH0_HSYNC_START(x) ((x) << 16) ++ ++#define CDNS_DP_MSA_HORIZONTAL_1(s) (CDNS_DPTX_STREAM(s) + 0x04) ++#define CDNS_DP_MSAH1_HSYNC_WIDTH(x) (x) ++#define CDNS_DP_MSAH1_HSYNC_POL_LOW BIT(15) ++#define CDNS_DP_MSAH1_HDISP_WIDTH(x) ((x) << 16) ++ ++#define CDNS_DP_MSA_VERTICAL_0(s) (CDNS_DPTX_STREAM(s) + 0x08) ++#define CDNS_DP_MSAV0_V_TOTAL(x) (x) ++#define CDNS_DP_MSAV0_VSYNC_START(x) ((x) << 16) ++ ++#define CDNS_DP_MSA_VERTICAL_1(s) (CDNS_DPTX_STREAM(s) + 0x0c) ++#define CDNS_DP_MSAV1_VSYNC_WIDTH(x) (x) ++#define CDNS_DP_MSAV1_VSYNC_POL_LOW BIT(15) ++#define CDNS_DP_MSAV1_VDISP_WIDTH(x) ((x) << 16) ++ ++#define CDNS_DP_MSA_MISC(s) (CDNS_DPTX_STREAM(s) + 0x10) ++#define CDNS_DP_STREAM_CONFIGs(s) (CDNS_DPTX_STREAM(s) + 0x14) ++#define CDNS_DP_STREAM_CONFIG_2(s) (CDNS_DPTX_STREAM(s) + 0x2c) ++#define CDNS_DP_SC2_TU_VS_DIFF(x) ((x) << 8) ++ ++#define CDNS_DP_HORIZONTAL(s) (CDNS_DPTX_STREAM(s) + 0x30) ++#define CDNS_DP_H_HSYNC_WIDTH(x) (x) ++#define CDNS_DP_H_H_TOTAL(x) ((x) << 16) ++ ++#define CDNS_DP_VERTICAL_0(s) (CDNS_DPTX_STREAM(s) + 0x34) ++#define CDNS_DP_V0_VHEIGHT(x) (x) ++#define CDNS_DP_V0_VSTART(x) ((x) << 16) ++ ++#define CDNS_DP_VERTICAL_1(s) (CDNS_DPTX_STREAM(s) + 0x38) ++#define CDNS_DP_V1_VTOTAL(x) (x) ++#define CDNS_DP_V1_VTOTAL_EVEN BIT(16) ++ ++#define CDNS_DP_FRAMER_PXL_REPR(s) (CDNS_DPTX_STREAM(s) + 0x4c) ++#define CDNS_DP_FRAMER_6_BPC BIT(0) ++#define CDNS_DP_FRAMER_8_BPC BIT(1) ++#define CDNS_DP_FRAMER_10_BPC BIT(2) ++#define CDNS_DP_FRAMER_12_BPC BIT(3) ++#define CDNS_DP_FRAMER_16_BPC BIT(4) ++#define CDNS_DP_FRAMER_PXL_FORMAT 0x8 ++#define CDNS_DP_FRAMER_RGB BIT(0) ++#define CDNS_DP_FRAMER_YCBCR444 BIT(1) ++#define CDNS_DP_FRAMER_YCBCR422 BIT(2) ++#define CDNS_DP_FRAMER_YCBCR420 BIT(3) ++#define CDNS_DP_FRAMER_Y_ONLY BIT(4) ++ ++#define CDNS_DP_FRAMER_SP(s) (CDNS_DPTX_STREAM(s) + 0x10) ++#define CDNS_DP_FRAMER_VSYNC_POL_LOW BIT(0) ++#define CDNS_DP_FRAMER_HSYNC_POL_LOW BIT(1) ++#define CDNS_DP_FRAMER_INTERLACE BIT(2) ++ ++#define CDNS_DP_LINE_THRESH(s) (CDNS_DPTX_STREAM(s) + 0x64) ++#define CDNS_DP_ACTIVE_LINE_THRESH(x) (x) ++ ++#define CDNS_DP_VB_ID(s) (CDNS_DPTX_STREAM(s) + 0x68) ++#define CDNS_DP_VB_ID_INTERLACED BIT(2) ++#define CDNS_DP_VB_ID_COMPRESSED BIT(6) ++ ++#define CDNS_DP_FRONT_BACK_PORCH(s) (CDNS_DPTX_STREAM(s) + 0x78) ++#define CDNS_DP_BACK_PORCH(x) (x) ++#define CDNS_DP_FRONT_PORCH(x) ((x) << 16) ++ ++#define CDNS_DP_BYTE_COUNT(s) (CDNS_DPTX_STREAM(s) + 0x7c) ++#define CDNS_DP_BYTE_COUNT_BYTES_IN_CHUNK_SHIFT 16 ++ ++#define CDNS_DP_MST_STREAM_CONFIG(s) (CDNS_DPTX_STREAM(s) + 0x14) ++#define CDNS_DP_MST_STRM_CFG_STREAM_EN BIT(0) ++#define CDNS_DP_MST_STRM_CFG_NO_VIDEO BIT(1) ++ ++#define CDNS_DP_MST_SLOT_ALLOCATE(s) (CDNS_DPTX_STREAM(s) + 0x44) ++#define CDNS_DP_S_ALLOC_START_SLOT(x) (x) ++#define CDNS_DP_S_ALLOC_END_SLOT(x) ((x) << 8) ++ ++#define CDNS_DP_RATE_GOVERNING(s) (CDNS_DPTX_STREAM(s) + 0x48) ++#define CDNS_DP_RG_TARG_AV_SLOTS_Y(x) (x) ++#define CDNS_DP_RG_TARG_AV_SLOTS_X(x) (x << 4) ++#define CDNS_DP_RG_ENABLE BIT(10) ++ ++#define CDNS_DP_MTPH_CONTROL 0x2264 ++#define CDNS_DP_MTPH_ECF_EN BIT(0) ++#define CDNS_DP_MTPH_ACT_EN BIT(1) ++#define CDNS_DP_MTPH_LVP_EN BIT(2) ++ ++#define CDNS_DP_MTPH_STATUS 0x226C ++#define CDNS_DP_MTPH_ACT_STATUS BIT(0) ++ ++ ++#define CDNS_DPTX_GLOBAL 0x02300 ++#define CDNS_DP_LANE_EN (CDNS_DPTX_GLOBAL + 0x00) ++#define CDNS_DP_LANE_EN_LANES(x) GENMASK(x - 1, 0) ++#define CDNS_DP_ENHNCD (CDNS_DPTX_GLOBAL + 0x04) ++ ++ ++#define to_mhdp_connector(x) container_of(x, struct cdns_mhdp_connector, base) ++#define to_mhdp_bridge(x) container_of(x, struct cdns_mhdp_bridge, base) ++#define mgr_to_mhdp(x) container_of(x, struct cdns_mhdp_device, mst_mgr) ++ ++#define CDNS_MHDP_MAX_STREAMS 4 ++ ++enum pixel_format { ++ PIXEL_FORMAT_RGB = 1, ++ PIXEL_FORMAT_YCBCR_444 = 2, ++ PIXEL_FORMAT_YCBCR_422 = 4, ++ PIXEL_FORMAT_YCBCR_420 = 8, ++ PIXEL_FORMAT_Y_ONLY = 16, ++}; ++ ++ ++int cdns_mhdp_mst_init(struct cdns_mhdp_device *mhdp); ++void cdns_mhdp_mst_deinit(struct cdns_mhdp_device *mhdp); ++bool cdns_mhdp_mst_probe(struct cdns_mhdp_device *mhdp); ++enum pixel_format cdns_mhdp_get_pxlfmt(u32 color_formats); ++u32 cdns_mhdp_get_bpp(u32 bpc, u32 color_formats); ++void cdns_mhdp_configure_video(struct drm_bridge *bridge); ++void cdns_mhdp_mst_enable(struct drm_bridge *bridge); ++void cdns_mhdp_mst_disable(struct drm_bridge *bridge); ++void cdns_mhdp_enable(struct drm_bridge *bridge); ++ ++#endif +diff --git a/drivers/gpu/drm/imx/Kconfig b/drivers/gpu/drm/imx/Kconfig +index 6231048aa5aa..74592ac2889b 100644 +--- a/drivers/gpu/drm/imx/Kconfig ++++ b/drivers/gpu/drm/imx/Kconfig +@@ -40,4 +40,13 @@ config DRM_IMX_HDMI + help + Choose this if you want to use HDMI on i.MX6. + ++config DRM_IMX_CDNS_MHDP ++ tristate "NXP i.MX MX8 DRM HDMI/DP" ++ select DRM_CDNS_MHDP ++ select DRM_CDNS_DP ++ select DRM_CDNS_HDMI ++ select DRM_CDNS_AUDIO ++ help ++ Choose this if you want to use HDMI on i.MX8. ++ + source "drivers/gpu/drm/imx/dcss/Kconfig" +diff --git a/drivers/gpu/drm/imx/Makefile b/drivers/gpu/drm/imx/Makefile +index b644deffe948..b43e3250b416 100644 +--- a/drivers/gpu/drm/imx/Makefile ++++ b/drivers/gpu/drm/imx/Makefile +@@ -10,3 +10,7 @@ obj-$(CONFIG_DRM_IMX_LDB) += imx-ldb.o + + obj-$(CONFIG_DRM_IMX_HDMI) += dw_hdmi-imx.o + obj-$(CONFIG_DRM_IMX_DCSS) += dcss/ ++ ++cdns_mhdp_imx-objs := cdn-mhdp-imxdrv.o cdn-mhdp-dp-phy.o cdn-mhdp-hdmi-phy.o ++obj-$(CONFIG_DRM_IMX_CDNS_MHDP) += cdns_mhdp_imx.o ++ +diff --git a/drivers/gpu/drm/imx/cdn-mhdp-dp-phy.c b/drivers/gpu/drm/imx/cdn-mhdp-dp-phy.c +new file mode 100644 +index 000000000000..60c1e6342875 +--- /dev/null ++++ b/drivers/gpu/drm/imx/cdn-mhdp-dp-phy.c +@@ -0,0 +1,529 @@ ++/* ++ * Cadence Display Port Interface (DP) PHY driver ++ * ++ * Copyright (C) 2019 NXP Semiconductor, Inc. ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License as published by ++ * the Free Software Foundation; either version 2 of the License, or ++ * (at your option) any later version. ++ * ++ */ ++#include ++#include ++#include ++#include ++#include "cdn-mhdp-phy.h" ++ ++enum dp_link_rate { ++ RATE_1_6 = 162000, ++ RATE_2_1 = 216000, ++ RATE_2_4 = 243000, ++ RATE_2_7 = 270000, ++ RATE_3_2 = 324000, ++ RATE_4_3 = 432000, ++ RATE_5_4 = 540000, ++ RATE_8_1 = 810000, ++}; ++ ++struct phy_pll_reg { ++ u16 val[7]; ++ u32 addr; ++}; ++ ++static const struct phy_pll_reg phy_pll_27m_cfg[] = { ++ /* 1.62 2.16 2.43 2.7 3.24 4.32 5.4 register address */ ++ {{ 0x010E, 0x010E, 0x010E, 0x010E, 0x010E, 0x010E, 0x010E }, CMN_PLL0_VCOCAL_INIT_TMR }, ++ {{ 0x001B, 0x001B, 0x001B, 0x001B, 0x001B, 0x001B, 0x001B }, CMN_PLL0_VCOCAL_ITER_TMR }, ++ {{ 0x30B9, 0x3087, 0x3096, 0x30B4, 0x30B9, 0x3087, 0x30B4 }, CMN_PLL0_VCOCAL_START }, ++ {{ 0x0077, 0x009F, 0x00B3, 0x00C7, 0x0077, 0x009F, 0x00C7 }, CMN_PLL0_INTDIV }, ++ {{ 0xF9DA, 0xF7CD, 0xF6C7, 0xF5C1, 0xF9DA, 0xF7CD, 0xF5C1 }, CMN_PLL0_FRACDIV }, ++ {{ 0x001E, 0x0028, 0x002D, 0x0032, 0x001E, 0x0028, 0x0032 }, CMN_PLL0_HIGH_THR }, ++ {{ 0x0020, 0x0020, 0x0020, 0x0020, 0x0020, 0x0020, 0x0020 }, CMN_PLL0_DSM_DIAG }, ++ {{ 0x0000, 0x1000, 0x1000, 0x1000, 0x0000, 0x1000, 0x1000 }, CMN_PLLSM0_USER_DEF_CTRL }, ++ {{ 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000 }, CMN_DIAG_PLL0_OVRD }, ++ {{ 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000 }, CMN_DIAG_PLL0_FBH_OVRD }, ++ {{ 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000 }, CMN_DIAG_PLL0_FBL_OVRD }, ++ {{ 0x0006, 0x0007, 0x0007, 0x0007, 0x0006, 0x0007, 0x0007 }, CMN_DIAG_PLL0_V2I_TUNE }, ++ {{ 0x0043, 0x0043, 0x0043, 0x0042, 0x0043, 0x0043, 0x0042 }, CMN_DIAG_PLL0_CP_TUNE }, ++ {{ 0x0008, 0x0008, 0x0008, 0x0008, 0x0008, 0x0008, 0x0008 }, CMN_DIAG_PLL0_LF_PROG }, ++ {{ 0x0100, 0x0001, 0x0001, 0x0001, 0x0100, 0x0001, 0x0001 }, CMN_DIAG_PLL0_PTATIS_TUNE1 }, ++ {{ 0x0007, 0x0001, 0x0001, 0x0001, 0x0007, 0x0001, 0x0001 }, CMN_DIAG_PLL0_PTATIS_TUNE2 }, ++ {{ 0x0020, 0x0020, 0x0020, 0x0020, 0x0020, 0x0020, 0x0020 }, CMN_DIAG_PLL0_TEST_MODE}, ++ {{ 0x0016, 0x0016, 0x0016, 0x0016, 0x0016, 0x0016, 0x0016 }, CMN_PSM_CLK_CTRL } ++}; ++ ++static const struct phy_pll_reg phy_pll_24m_cfg[] = { ++ /* 1.62 2.16 2.43 2.7 3.24 4.32 5.4 register address */ ++ {{ 0x00F0, 0x00F0, 0x00F0, 0x00F0, 0x00F0, 0x00F0, 0x00F0 }, CMN_PLL0_VCOCAL_INIT_TMR }, ++ {{ 0x0018, 0x0018, 0x0018, 0x0018, 0x0018, 0x0018, 0x0018 }, CMN_PLL0_VCOCAL_ITER_TMR }, ++ {{ 0x3061, 0x3092, 0x30B3, 0x30D0, 0x3061, 0x3092, 0x30D0 }, CMN_PLL0_VCOCAL_START }, ++ {{ 0x0086, 0x00B3, 0x00CA, 0x00E0, 0x0086, 0x00B3, 0x00E0 }, CMN_PLL0_INTDIV }, ++ {{ 0xF917, 0xF6C7, 0x75A1, 0xF479, 0xF917, 0xF6C7, 0xF479 }, CMN_PLL0_FRACDIV }, ++ {{ 0x0022, 0x002D, 0x0033, 0x0038, 0x0022, 0x002D, 0x0038 }, CMN_PLL0_HIGH_THR }, ++ {{ 0x0020, 0x0020, 0x0020, 0x0020, 0x0020, 0x0020, 0x0020 }, CMN_PLL0_DSM_DIAG }, ++ {{ 0x0000, 0x1000, 0x1000, 0x1000, 0x0000, 0x1000, 0x1000 }, CMN_PLLSM0_USER_DEF_CTRL }, ++ {{ 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000 }, CMN_DIAG_PLL0_OVRD }, ++ {{ 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000 }, CMN_DIAG_PLL0_FBH_OVRD }, ++ {{ 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000 }, CMN_DIAG_PLL0_FBL_OVRD }, ++ {{ 0x0006, 0x0007, 0x0007, 0x0007, 0x0006, 0x0007, 0x0007 }, CMN_DIAG_PLL0_V2I_TUNE }, ++ {{ 0x0026, 0x0029, 0x0029, 0x0029, 0x0026, 0x0029, 0x0029 }, CMN_DIAG_PLL0_CP_TUNE }, ++ {{ 0x0008, 0x0008, 0x0008, 0x0008, 0x0008, 0x0008, 0x0008 }, CMN_DIAG_PLL0_LF_PROG }, ++ {{ 0x008C, 0x008C, 0x008C, 0x008C, 0x008C, 0x008C, 0x008C }, CMN_DIAG_PLL0_PTATIS_TUNE1 }, ++ {{ 0x002E, 0x002E, 0x002E, 0x002E, 0x002E, 0x002E, 0x002E }, CMN_DIAG_PLL0_PTATIS_TUNE2 }, ++ {{ 0x0022, 0x0022, 0x0022, 0x0022, 0x0022, 0x0022, 0x0022 }, CMN_DIAG_PLL0_TEST_MODE}, ++ {{ 0x0016, 0x0016, 0x0016, 0x0016, 0x0016, 0x0016, 0x0016 }, CMN_PSM_CLK_CTRL } ++}; ++ ++static int link_rate_index(u32 rate) ++{ ++ switch (rate) { ++ case RATE_1_6: ++ return 0; ++ case RATE_2_1: ++ return 1; ++ case RATE_2_4: ++ return 2; ++ case RATE_2_7: ++ return 3; ++ case RATE_3_2: ++ return 4; ++ case RATE_4_3: ++ return 5; ++ case RATE_5_4: ++ return 6; ++ default: ++ return -1; ++ } ++} ++ ++static void dp_aux_cfg(struct cdns_mhdp_device *mhdp) ++{ ++ /* Power up Aux */ ++ cdns_phy_reg_write(mhdp, TXDA_CYA_AUXDA_CYA, 1); ++ ++ cdns_phy_reg_write(mhdp, TX_DIG_CTRL_REG_2, 36); ++ ndelay(150); ++ cdns_phy_reg_write(mhdp, TX_ANA_CTRL_REG_2, 0x0100); ++ ndelay(150); ++ cdns_phy_reg_write(mhdp, TX_ANA_CTRL_REG_2, 0x0300); ++ ndelay(150); ++ cdns_phy_reg_write(mhdp, TX_ANA_CTRL_REG_3, 0x0000); ++ ndelay(150); ++ cdns_phy_reg_write(mhdp, TX_ANA_CTRL_REG_1, 0x2008); ++ ndelay(150); ++ cdns_phy_reg_write(mhdp, TX_ANA_CTRL_REG_1, 0x2018); ++ ndelay(150); ++ cdns_phy_reg_write(mhdp, TX_ANA_CTRL_REG_1, 0xA018); ++ ndelay(150); ++ cdns_phy_reg_write(mhdp, TX_ANA_CTRL_REG_2, 0x030C); ++ ndelay(150); ++ cdns_phy_reg_write(mhdp, TX_ANA_CTRL_REG_5, 0x0000); ++ ndelay(150); ++ cdns_phy_reg_write(mhdp, TX_ANA_CTRL_REG_4, 0x1001); ++ ndelay(150); ++ cdns_phy_reg_write(mhdp, TX_ANA_CTRL_REG_1, 0xA098); ++ ndelay(150); ++ cdns_phy_reg_write(mhdp, TX_ANA_CTRL_REG_1, 0xA198); ++ ndelay(150); ++ cdns_phy_reg_write(mhdp, TX_ANA_CTRL_REG_2, 0x030d); ++ ndelay(150); ++ cdns_phy_reg_write(mhdp, TX_ANA_CTRL_REG_2, 0x030f); ++} ++ ++/* PMA common configuration for 24MHz */ ++static void dp_phy_pma_cmn_cfg_24mhz(struct cdns_mhdp_device *mhdp) ++{ ++ int k; ++ u32 num_lanes = mhdp->dp.link.num_lanes; ++ u16 val; ++ ++ val = cdns_phy_reg_read(mhdp, PHY_PMA_CMN_CTRL1); ++ val &= 0xFFF7; ++ val |= 0x0008; ++ cdns_phy_reg_write(mhdp, PHY_PMA_CMN_CTRL1, val); ++ ++ for (k = 0; k < num_lanes; k++) { ++ /* Transceiver control and diagnostic registers */ ++ cdns_phy_reg_write(mhdp, XCVR_DIAG_LANE_FCM_EN_MGN_TMR | (k << 9), 0x0090); ++ /* Transmitter receiver detect registers */ ++ cdns_phy_reg_write(mhdp, TX_RCVDET_EN_TMR | (k << 9), 0x0960); ++ cdns_phy_reg_write(mhdp, TX_RCVDET_ST_TMR | (k << 9), 0x0030); ++ } ++} ++ ++/* Valid for 24 MHz only */ ++static void dp_phy_pma_cmn_pll0_24mhz(struct cdns_mhdp_device *mhdp) ++{ ++ u32 num_lanes = mhdp->dp.link.num_lanes; ++ u32 link_rate = mhdp->dp.link.rate; ++ u16 val; ++ int index, i, k; ++ ++ /* ++ * PLL reference clock source select ++ * for single ended reference clock val |= 0x0030; ++ * for differential clock val |= 0x0000; ++ */ ++ val = cdns_phy_reg_read(mhdp, PHY_PMA_CMN_CTRL1); ++ val = val & 0xFF8F; ++ val = val | 0x0030; ++ cdns_phy_reg_write(mhdp, PHY_PMA_CMN_CTRL1, val); ++ ++ /* DP PLL data rate 0/1 clock divider value */ ++ val = cdns_phy_reg_read(mhdp, PHY_HDP_CLK_CTL); ++ val &= 0x00FF; ++ if (link_rate <= RATE_2_7) ++ val |= 0x2400; ++ else ++ val |= 0x1200; ++ cdns_phy_reg_write(mhdp, PHY_HDP_CLK_CTL, val); ++ ++ /* High speed clock 0/1 div */ ++ val = cdns_phy_reg_read(mhdp, CMN_DIAG_HSCLK_SEL); ++ val &= 0xFFCC; ++ if (link_rate <= RATE_2_7) ++ val |= 0x0011; ++ cdns_phy_reg_write(mhdp, CMN_DIAG_HSCLK_SEL, val); ++ ++ for (k = 0; k < num_lanes; k = k + 1) { ++ val = cdns_phy_reg_read(mhdp, (XCVR_DIAG_HSCLK_SEL | (k << 9))); ++ val &= 0xCFFF; ++ if (link_rate <= RATE_2_7) ++ val |= 0x1000; ++ cdns_phy_reg_write(mhdp, (XCVR_DIAG_HSCLK_SEL | (k << 9)), val); ++ } ++ ++ /* DP PHY PLL 24MHz configuration */ ++ index = link_rate_index(link_rate); ++ for (i = 0; i < ARRAY_SIZE(phy_pll_24m_cfg); i++) ++ cdns_phy_reg_write(mhdp, phy_pll_24m_cfg[i].addr, phy_pll_24m_cfg[i].val[index]); ++ ++ /* Transceiver control and diagnostic registers */ ++ for (k = 0; k < num_lanes; k = k + 1) { ++ val = cdns_phy_reg_read(mhdp, (XCVR_DIAG_PLLDRC_CTRL | (k << 9))); ++ val &= 0x8FFF; ++ if (link_rate <= RATE_2_7) ++ val |= 0x2000; ++ else ++ val |= 0x1000; ++ cdns_phy_reg_write(mhdp, (XCVR_DIAG_PLLDRC_CTRL | (k << 9)), val); ++ } ++ ++ for (k = 0; k < num_lanes; k = k + 1) { ++ cdns_phy_reg_write(mhdp, (XCVR_PSM_RCTRL | (k << 9)), 0xBEFC); ++ cdns_phy_reg_write(mhdp, (TX_PSC_A0 | (k << 9)), 0x6799); ++ cdns_phy_reg_write(mhdp, (TX_PSC_A1 | (k << 9)), 0x6798); ++ cdns_phy_reg_write(mhdp, (TX_PSC_A2 | (k << 9)), 0x0098); ++ cdns_phy_reg_write(mhdp, (TX_PSC_A3 | (k << 9)), 0x0098); ++ } ++} ++ ++/* PMA common configuration for 27MHz */ ++static void dp_phy_pma_cmn_cfg_27mhz(struct cdns_mhdp_device *mhdp) ++{ ++ u32 num_lanes = mhdp->dp.link.num_lanes; ++ u16 val; ++ int k; ++ ++ val = cdns_phy_reg_read(mhdp, PHY_PMA_CMN_CTRL1); ++ val &= 0xFFF7; ++ val |= 0x0008; ++ cdns_phy_reg_write(mhdp, PHY_PMA_CMN_CTRL1, val); ++ ++ /* Startup state machine registers */ ++ cdns_phy_reg_write(mhdp, CMN_SSM_BIAS_TMR, 0x0087); ++ cdns_phy_reg_write(mhdp, CMN_PLLSM0_PLLEN_TMR, 0x001B); ++ cdns_phy_reg_write(mhdp, CMN_PLLSM0_PLLPRE_TMR, 0x0036); ++ cdns_phy_reg_write(mhdp, CMN_PLLSM0_PLLVREF_TMR, 0x001B); ++ cdns_phy_reg_write(mhdp, CMN_PLLSM0_PLLLOCK_TMR, 0x006C); ++ ++ /* Current calibration registers */ ++ cdns_phy_reg_write(mhdp, CMN_ICAL_INIT_TMR, 0x0044); ++ cdns_phy_reg_write(mhdp, CMN_ICAL_ITER_TMR, 0x0006); ++ cdns_phy_reg_write(mhdp, CMN_ICAL_ADJ_INIT_TMR, 0x0022); ++ cdns_phy_reg_write(mhdp, CMN_ICAL_ADJ_ITER_TMR, 0x0006); ++ ++ /* Resistor calibration registers */ ++ cdns_phy_reg_write(mhdp, CMN_TXPUCAL_INIT_TMR, 0x0022); ++ cdns_phy_reg_write(mhdp, CMN_TXPUCAL_ITER_TMR, 0x0006); ++ cdns_phy_reg_write(mhdp, CMN_TXPU_ADJ_INIT_TMR, 0x0022); ++ cdns_phy_reg_write(mhdp, CMN_TXPU_ADJ_ITER_TMR, 0x0006); ++ cdns_phy_reg_write(mhdp, CMN_TXPDCAL_INIT_TMR, 0x0022); ++ cdns_phy_reg_write(mhdp, CMN_TXPDCAL_ITER_TMR, 0x0006); ++ cdns_phy_reg_write(mhdp, CMN_TXPD_ADJ_INIT_TMR, 0x0022); ++ cdns_phy_reg_write(mhdp, CMN_TXPD_ADJ_ITER_TMR, 0x0006); ++ cdns_phy_reg_write(mhdp, CMN_RXCAL_INIT_TMR, 0x0022); ++ cdns_phy_reg_write(mhdp, CMN_RXCAL_ITER_TMR, 0x0006); ++ cdns_phy_reg_write(mhdp, CMN_RX_ADJ_INIT_TMR, 0x0022); ++ cdns_phy_reg_write(mhdp, CMN_RX_ADJ_ITER_TMR, 0x0006); ++ ++ for (k = 0; k < num_lanes; k = k + 1) { ++ /* Power state machine registers */ ++ cdns_phy_reg_write(mhdp, XCVR_PSM_CAL_TMR | (k << 9), 0x016D); ++ cdns_phy_reg_write(mhdp, XCVR_PSM_A0IN_TMR | (k << 9), 0x016D); ++ /* Transceiver control and diagnostic registers */ ++ cdns_phy_reg_write(mhdp, XCVR_DIAG_LANE_FCM_EN_MGN_TMR | (k << 9), 0x00A2); ++ cdns_phy_reg_write(mhdp, TX_DIAG_BGREF_PREDRV_DELAY | (k << 9), 0x0097); ++ /* Transmitter receiver detect registers */ ++ cdns_phy_reg_write(mhdp, TX_RCVDET_EN_TMR | (k << 9), 0x0A8C); ++ cdns_phy_reg_write(mhdp, TX_RCVDET_ST_TMR | (k << 9), 0x0036); ++ } ++} ++ ++static void dp_phy_pma_cmn_pll0_27mhz(struct cdns_mhdp_device *mhdp) ++{ ++ u32 num_lanes = mhdp->dp.link.num_lanes; ++ u32 link_rate = mhdp->dp.link.rate; ++ u16 val; ++ int index, i, k; ++ ++ /* ++ * PLL reference clock source select ++ * for single ended reference clock val |= 0x0030; ++ * for differential clock val |= 0x0000; ++ */ ++ val = cdns_phy_reg_read(mhdp, PHY_PMA_CMN_CTRL1); ++ val &= 0xFF8F; ++ cdns_phy_reg_write(mhdp, PHY_PMA_CMN_CTRL1, val); ++ ++ /* for differential clock on the refclk_p and refclk_m off chip pins: ++ * CMN_DIAG_ACYA[8]=1'b1 ++ */ ++ cdns_phy_reg_write(mhdp, CMN_DIAG_ACYA, 0x0100); ++ ++ /* DP PLL data rate 0/1 clock divider value */ ++ val = cdns_phy_reg_read(mhdp, PHY_HDP_CLK_CTL); ++ val &= 0x00FF; ++ if (link_rate <= RATE_2_7) ++ val |= 0x2400; ++ else ++ val |= 0x1200; ++ cdns_phy_reg_write(mhdp, PHY_HDP_CLK_CTL, val); ++ ++ /* High speed clock 0/1 div */ ++ val = cdns_phy_reg_read(mhdp, CMN_DIAG_HSCLK_SEL); ++ val &= 0xFFCC; ++ if (link_rate <= RATE_2_7) ++ val |= 0x0011; ++ cdns_phy_reg_write(mhdp, CMN_DIAG_HSCLK_SEL, val); ++ ++ for (k = 0; k < num_lanes; k++) { ++ val = cdns_phy_reg_read(mhdp, (XCVR_DIAG_HSCLK_SEL | (k << 9))); ++ val = val & 0xCFFF; ++ if (link_rate <= RATE_2_7) ++ val |= 0x1000; ++ cdns_phy_reg_write(mhdp, (XCVR_DIAG_HSCLK_SEL | (k << 9)), val); ++ } ++ ++ /* DP PHY PLL 27MHz configuration */ ++ index = link_rate_index(link_rate); ++ for (i = 0; i < ARRAY_SIZE(phy_pll_27m_cfg); i++) ++ cdns_phy_reg_write(mhdp, phy_pll_27m_cfg[i].addr, phy_pll_27m_cfg[i].val[index]); ++ ++ /* Transceiver control and diagnostic registers */ ++ for (k = 0; k < num_lanes; k++) { ++ val = cdns_phy_reg_read(mhdp, (XCVR_DIAG_PLLDRC_CTRL | (k << 9))); ++ val = val & 0x8FFF; ++ if (link_rate <= RATE_2_7) ++ val |= 0x2000; ++ else ++ val |= 0x1000; ++ cdns_phy_reg_write(mhdp, (XCVR_DIAG_PLLDRC_CTRL | (k << 9)), val); ++ } ++ ++ for (k = 0; k < num_lanes; k = k + 1) { ++ /* Power state machine registers */ ++ cdns_phy_reg_write(mhdp, (XCVR_PSM_RCTRL | (k << 9)), 0xBEFC); ++ cdns_phy_reg_write(mhdp, (TX_PSC_A0 | (k << 9)), 0x6799); ++ cdns_phy_reg_write(mhdp, (TX_PSC_A1 | (k << 9)), 0x6798); ++ cdns_phy_reg_write(mhdp, (TX_PSC_A2 | (k << 9)), 0x0098); ++ cdns_phy_reg_write(mhdp, (TX_PSC_A3 | (k << 9)), 0x0098); ++ /* Receiver calibration power state definition register */ ++ val = cdns_phy_reg_read(mhdp, RX_PSC_CAL | (k << 9)); ++ val &= 0xFFBB; ++ cdns_phy_reg_write(mhdp, (RX_PSC_CAL | (k << 9)), val); ++ val = cdns_phy_reg_read(mhdp, RX_PSC_A0 | (k << 9)); ++ val &= 0xFFBB; ++ cdns_phy_reg_write(mhdp, (RX_PSC_A0 | (k << 9)), val); ++ } ++} ++ ++static void dp_phy_power_down(struct cdns_mhdp_device *mhdp) ++{ ++ u16 val; ++ int i; ++ ++ if (!mhdp->power_up) ++ return; ++ ++ /* Place the PHY lanes in the A3 power state. */ ++ cdns_phy_reg_write(mhdp, PHY_HDP_MODE_CTRL, 0x8); ++ /* Wait for Power State A3 Ack */ ++ for (i = 0; i < 10; i++) { ++ val = cdns_phy_reg_read(mhdp, PHY_HDP_MODE_CTRL); ++ if (val & (1 << 7)) ++ break; ++ msleep(20); ++ } ++ if (i == 10) { ++ dev_err(mhdp->dev, "Wait A3 Ack failed\n"); ++ return; ++ } ++ ++ /* Disable HDP PLL’s data rate and full rate clocks out of PMA. */ ++ val = cdns_phy_reg_read(mhdp, PHY_HDP_CLK_CTL); ++ val &= ~(1 << 2); ++ cdns_phy_reg_write(mhdp, PHY_HDP_CLK_CTL, val); ++ /* Wait for PLL clock gate ACK */ ++ for (i = 0; i < 10; i++) { ++ val = cdns_phy_reg_read(mhdp, PHY_HDP_CLK_CTL); ++ if (!(val & (1 << 3))) ++ break; ++ msleep(20); ++ } ++ if (i == 10) { ++ dev_err(mhdp->dev, "Wait PLL clock gate Ack failed\n"); ++ return; ++ } ++ ++ /* Disable HDP PLL’s for high speed clocks */ ++ val = cdns_phy_reg_read(mhdp, PHY_HDP_CLK_CTL); ++ val &= ~(1 << 0); ++ cdns_phy_reg_write(mhdp, PHY_HDP_CLK_CTL, val); ++ /* Wait for PLL disable ACK */ ++ for (i = 0; i < 10; i++) { ++ val = cdns_phy_reg_read(mhdp, PHY_HDP_CLK_CTL); ++ if (!(val & (1 << 1))) ++ break; ++ msleep(20); ++ } ++ if (i == 10) { ++ dev_err(mhdp->dev, "Wait PLL disable Ack failed\n"); ++ return; ++ } ++} ++ ++static int dp_phy_power_up(struct cdns_mhdp_device *mhdp) ++{ ++ u32 val, i; ++ ++ /* Enable HDP PLL’s for high speed clocks */ ++ val = cdns_phy_reg_read(mhdp, PHY_HDP_CLK_CTL); ++ val |= (1 << 0); ++ cdns_phy_reg_write(mhdp, PHY_HDP_CLK_CTL, val); ++ /* Wait for PLL ready ACK */ ++ for (i = 0; i < 10; i++) { ++ val = cdns_phy_reg_read(mhdp, PHY_HDP_CLK_CTL); ++ if (val & (1 << 1)) ++ break; ++ msleep(20); ++ } ++ if (i == 10) { ++ dev_err(mhdp->dev, "Wait PLL Ack failed\n"); ++ return -1; ++ } ++ ++ /* Enable HDP PLL’s data rate and full rate clocks out of PMA. */ ++ val = cdns_phy_reg_read(mhdp, PHY_HDP_CLK_CTL); ++ val |= (1 << 2); ++ cdns_phy_reg_write(mhdp, PHY_HDP_CLK_CTL, val); ++ /* Wait for PLL clock enable ACK */ ++ for (i = 0; i < 10; i++) { ++ val = cdns_phy_reg_read(mhdp, PHY_HDP_CLK_CTL); ++ if (val & (1 << 3)) ++ break; ++ msleep(20); ++ } ++ if (i == 10) { ++ dev_err(mhdp->dev, "Wait PLL clock enable ACk failed\n"); ++ return -1; ++ } ++ ++ /* Configure PHY in A2 Mode */ ++ cdns_phy_reg_write(mhdp, PHY_HDP_MODE_CTRL, 0x0004); ++ /* Wait for Power State A2 Ack */ ++ for (i = 0; i < 10; i++) { ++ val = cdns_phy_reg_read(mhdp, PHY_HDP_MODE_CTRL); ++ if (val & (1 << 6)) ++ break; ++ msleep(20); ++ } ++ if (i == 10) { ++ dev_err(mhdp->dev, "Wait A2 Ack failed\n"); ++ return -1; ++ } ++ ++ /* Configure PHY in A0 mode (PHY must be in the A0 power ++ * state in order to transmit data) ++ */ ++ cdns_phy_reg_write(mhdp, PHY_HDP_MODE_CTRL, 0x0101); ++ ++ /* Wait for Power State A0 Ack */ ++ for (i = 0; i < 10; i++) { ++ val = cdns_phy_reg_read(mhdp, PHY_HDP_MODE_CTRL); ++ if (val & (1 << 4)) ++ break; ++ msleep(20); ++ } ++ if (i == 10) { ++ dev_err(mhdp->dev, "Wait A0 Ack failed\n"); ++ return -1; ++ } ++ ++ mhdp->power_up = true; ++ ++ return 0; ++} ++ ++int cdns_dp_phy_set_imx8mq(struct cdns_mhdp_device *mhdp) ++{ ++ int ret; ++ ++ /* Disable phy clock if PHY in power up state */ ++ dp_phy_power_down(mhdp); ++ ++ dp_phy_pma_cmn_cfg_27mhz(mhdp); ++ ++ dp_phy_pma_cmn_pll0_27mhz(mhdp); ++ ++ cdns_phy_reg_write(mhdp, TX_DIAG_ACYA_0, 1); ++ cdns_phy_reg_write(mhdp, TX_DIAG_ACYA_1, 1); ++ cdns_phy_reg_write(mhdp, TX_DIAG_ACYA_2, 1); ++ cdns_phy_reg_write(mhdp, TX_DIAG_ACYA_3, 1); ++ ++ /* PHY power up */ ++ ret = dp_phy_power_up(mhdp); ++ if (ret < 0) ++ return ret; ++ ++ dp_aux_cfg(mhdp); ++ ++ return ret; ++} ++ ++int cdns_dp_phy_set_imx8qm(struct cdns_mhdp_device *mhdp) ++{ ++ int ret; ++ ++ /* Disable phy clock if PHY in power up state */ ++ dp_phy_power_down(mhdp); ++ ++ dp_phy_pma_cmn_cfg_24mhz(mhdp); ++ ++ dp_phy_pma_cmn_pll0_24mhz(mhdp); ++ ++ cdns_phy_reg_write(mhdp, TX_DIAG_ACYA_0, 1); ++ cdns_phy_reg_write(mhdp, TX_DIAG_ACYA_1, 1); ++ cdns_phy_reg_write(mhdp, TX_DIAG_ACYA_2, 1); ++ cdns_phy_reg_write(mhdp, TX_DIAG_ACYA_3, 1); ++ ++ /* PHY power up */ ++ ret = dp_phy_power_up(mhdp); ++ if (ret < 0) ++ return ret; ++ ++ dp_aux_cfg(mhdp); ++ ++ return true; ++} +diff --git a/drivers/gpu/drm/imx/cdn-mhdp-hdmi-phy.c b/drivers/gpu/drm/imx/cdn-mhdp-hdmi-phy.c +new file mode 100644 +index 000000000000..ed0909a6bbdb +--- /dev/null ++++ b/drivers/gpu/drm/imx/cdn-mhdp-hdmi-phy.c +@@ -0,0 +1,777 @@ ++/* ++ * Cadence High-Definition Multimedia Interface (HDMI) driver ++ * ++ * Copyright (C) 2019 NXP Semiconductor, Inc. ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License as published by ++ * the Free Software Foundation; either version 2 of the License, or ++ * (at your option) any later version. ++ * ++ */ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#include ++#include "cdn-mhdp-phy.h" ++ ++/* HDMI TX clock control settings */ ++struct hdmi_ctrl { ++ u32 pixel_clk_freq_min; ++ u32 pixel_clk_freq_max; ++ u32 feedback_factor; ++ u32 data_range_kbps_min; ++ u32 data_range_kbps_max; ++ u32 cmnda_pll0_ip_div; ++ u32 cmn_ref_clk_dig_div; ++ u32 ref_clk_divider_scaler; ++ u32 pll_fb_div_total; ++ u32 cmnda_pll0_fb_div_low; ++ u32 cmnda_pll0_fb_div_high; ++ u32 pixel_div_total; ++ u32 cmnda_pll0_pxdiv_low; ++ u32 cmnda_pll0_pxdiv_high; ++ u32 vco_freq_min; ++ u32 vco_freq_max; ++ u32 vco_ring_select; ++ u32 cmnda_hs_clk_0_sel; ++ u32 cmnda_hs_clk_1_sel; ++ u32 hsclk_div_at_xcvr; ++ u32 hsclk_div_tx_sub_rate; ++ u32 cmnda_pll0_hs_sym_div_sel; ++ u32 cmnda_pll0_clk_freq_min; ++ u32 cmnda_pll0_clk_freq_max; ++}; ++ ++/* HDMI TX clock control settings, pixel clock is output */ ++static const struct hdmi_ctrl imx8mq_ctrl_table[] = { ++/*Minclk Maxclk Fdbak DR_min DR_max ip_d dig DS Totl */ ++{ 27000, 27000, 1000, 270000, 270000, 0x03, 0x1, 0x1, 240, 0x0BC, 0x030, 80, 0x026, 0x026, 2160000, 2160000, 0, 2, 2, 2, 4, 0x3, 27000, 27000}, ++{ 27000, 27000, 1250, 337500, 337500, 0x03, 0x1, 0x1, 300, 0x0EC, 0x03C, 100, 0x030, 0x030, 2700000, 2700000, 0, 2, 2, 2, 4, 0x3, 33750, 33750}, ++{ 27000, 27000, 1500, 405000, 405000, 0x03, 0x1, 0x1, 360, 0x11C, 0x048, 120, 0x03A, 0x03A, 3240000, 3240000, 0, 2, 2, 2, 4, 0x3, 40500, 40500}, ++{ 27000, 27000, 2000, 540000, 540000, 0x03, 0x1, 0x1, 240, 0x0BC, 0x030, 80, 0x026, 0x026, 2160000, 2160000, 0, 2, 2, 2, 4, 0x2, 54000, 54000}, ++{ 29700, 29700, 1000, 297000, 297000, 0x03, 0x1, 0x1, 264, 0x0d0, 0x034, 80, 0x026, 0x026, 2376000, 2376000, 0, 2, 2, 2, 4, 0x3, 29700, 29700}, ++ ++{ 54000, 54000, 1000, 540000, 540000, 0x03, 0x1, 0x1, 480, 0x17C, 0x060, 80, 0x026, 0x026, 4320000, 4320000, 1, 2, 2, 2, 4, 0x3, 54000, 54000}, ++{ 54000, 54000, 1250, 675000, 675000, 0x04, 0x1, 0x1, 400, 0x13C, 0x050, 50, 0x017, 0x017, 2700000, 2700000, 0, 1, 1, 2, 4, 0x2, 67500, 67500}, ++{ 54000, 54000, 1500, 810000, 810000, 0x04, 0x1, 0x1, 480, 0x17C, 0x060, 60, 0x01C, 0x01C, 3240000, 3240000, 0, 2, 2, 2, 2, 0x2, 81000, 81000}, ++{ 54000, 54000, 2000, 1080000, 1080000, 0x03, 0x1, 0x1, 240, 0x0BC, 0x030, 40, 0x012, 0x012, 2160000, 2160000, 0, 2, 2, 2, 1, 0x1, 108000, 108000}, ++{ 74250, 74250, 1000, 742500, 742500, 0x03, 0x1, 0x1, 660, 0x20C, 0x084, 80, 0x026, 0x026, 5940000, 5940000, 1, 2, 2, 2, 4, 0x3, 74250, 74250}, ++{ 74250, 74250, 1250, 928125, 928125, 0x04, 0x1, 0x1, 550, 0x1B4, 0x06E, 50, 0x017, 0x017, 3712500, 3712500, 1, 1, 1, 2, 4, 0x2, 92812, 92812}, ++{ 74250, 74250, 1500, 1113750, 1113750, 0x04, 0x1, 0x1, 660, 0x20C, 0x084, 60, 0x01C, 0x01C, 4455000, 4455000, 1, 2, 2, 2, 2, 0x2, 111375, 111375}, ++{ 74250, 74250, 2000, 1485000, 1485000, 0x03, 0x1, 0x1, 330, 0x104, 0x042, 40, 0x012, 0x012, 2970000, 2970000, 0, 2, 2, 2, 1, 0x1, 148500, 148500}, ++{ 99000, 99000, 1000, 990000, 990000, 0x03, 0x1, 0x1, 440, 0x15C, 0x058, 40, 0x012, 0x012, 3960000, 3960000, 1, 2, 2, 2, 2, 0x2, 99000, 99000}, ++{ 99000, 99000, 1250, 1237500, 1237500, 0x03, 0x1, 0x1, 275, 0x0D8, 0x037, 25, 0x00B, 0x00A, 2475000, 2475000, 0, 1, 1, 2, 2, 0x1, 123750, 123750}, ++{ 99000, 99000, 1500, 1485000, 1485000, 0x03, 0x1, 0x1, 330, 0x104, 0x042, 30, 0x00D, 0x00D, 2970000, 2970000, 0, 2, 2, 2, 1, 0x1, 148500, 148500}, ++{ 99000, 99000, 2000, 1980000, 1980000, 0x03, 0x1, 0x1, 440, 0x15C, 0x058, 40, 0x012, 0x012, 3960000, 3960000, 1, 2, 2, 2, 1, 0x1, 198000, 198000}, ++{148500, 148500, 1000, 1485000, 1485000, 0x03, 0x1, 0x1, 660, 0x20C, 0x084, 40, 0x012, 0x012, 5940000, 5940000, 1, 2, 2, 2, 2, 0x2, 148500, 148500}, ++{148500, 148500, 1250, 1856250, 1856250, 0x04, 0x1, 0x1, 550, 0x1B4, 0x06E, 25, 0x00B, 0x00A, 3712500, 3712500, 1, 1, 1, 2, 2, 0x1, 185625, 185625}, ++{148500, 148500, 1500, 2227500, 2227500, 0x03, 0x1, 0x1, 495, 0x188, 0x063, 30, 0x00D, 0x00D, 4455000, 4455000, 1, 1, 1, 2, 2, 0x1, 222750, 222750}, ++{148500, 148500, 2000, 2970000, 2970000, 0x03, 0x1, 0x1, 660, 0x20C, 0x084, 40, 0x012, 0x012, 5940000, 5940000, 1, 2, 2, 2, 1, 0x1, 297000, 297000}, ++{198000, 198000, 1000, 1980000, 1980000, 0x03, 0x1, 0x1, 220, 0x0AC, 0x02C, 10, 0x003, 0x003, 1980000, 1980000, 0, 1, 1, 2, 1, 0x0, 198000, 198000}, ++{198000, 198000, 1250, 2475000, 2475000, 0x03, 0x1, 0x1, 550, 0x1B4, 0x06E, 25, 0x00B, 0x00A, 4950000, 4950000, 1, 1, 1, 2, 2, 0x1, 247500, 247500}, ++{198000, 198000, 1500, 2970000, 2970000, 0x03, 0x1, 0x1, 330, 0x104, 0x042, 15, 0x006, 0x005, 2970000, 2970000, 0, 1, 1, 2, 1, 0x0, 297000, 297000}, ++{198000, 198000, 2000, 3960000, 3960000, 0x03, 0x1, 0x1, 440, 0x15C, 0x058, 20, 0x008, 0x008, 3960000, 3960000, 1, 1, 1, 2, 1, 0x0, 396000, 396000}, ++{297000, 297000, 1000, 2970000, 2970000, 0x03, 0x1, 0x1, 330, 0x104, 0x042, 10, 0x003, 0x003, 2970000, 2970000, 0, 1, 1, 2, 1, 0x0, 297000, 297000}, ++{297000, 297000, 1500, 4455000, 4455000, 0x03, 0x1, 0x1, 495, 0x188, 0x063, 15, 0x006, 0x005, 4455000, 4455000, 1, 1, 1, 2, 1, 0x0, 445500, 445500}, ++{297000, 297000, 2000, 5940000, 5940000, 0x03, 0x1, 0x1, 660, 0x20C, 0x084, 20, 0x008, 0x008, 5940000, 5940000, 1, 1, 1, 2, 1, 0x0, 594000, 594000}, ++{594000, 594000, 1000, 5940000, 5940000, 0x03, 0x1, 0x1, 660, 0x20C, 0x084, 10, 0x003, 0x003, 5940000, 5940000, 1, 1, 1, 2, 1, 0x0, 594000, 594000}, ++{594000, 594000, 750, 4455000, 4455000, 0x03, 0x1, 0x1, 495, 0x188, 0x063, 10, 0x003, 0x003, 4455000, 4455000, 1, 1, 1, 2, 1, 0x0, 445500, 445500}, ++{594000, 594000, 625, 3712500, 3712500, 0x04, 0x1, 0x1, 550, 0x1B4, 0x06E, 10, 0x003, 0x003, 3712500, 3712500, 1, 1, 1, 2, 1, 0x0, 371250, 371250}, ++{594000, 594000, 500, 2970000, 2970000, 0x03, 0x1, 0x1, 660, 0x20C, 0x084, 10, 0x003, 0x003, 5940000, 5940000, 1, 1, 1, 2, 2, 0x1, 297000, 297000}, ++}; ++ ++/* HDMI TX clock control settings, pixel clock is input */ ++static const struct hdmi_ctrl imx8qm_ctrl_table[] = { ++/*pclk_l pclk_h fd DRR_L DRR_H PLLD */ ++{ 25000, 42500, 1000, 250000, 425000, 0x05, 0x01, 0x01, 400, 0x182, 0x00A, 0, 0, 0, 2000000, 3400000, 0, 2, 2, 2, 4, 0x03, 25000, 42500}, ++{ 42500, 85000, 1000, 425000, 850000, 0x08, 0x03, 0x01, 320, 0x132, 0x00A, 0, 0, 0, 1700000, 3400000, 0, 1, 1, 2, 4, 0x02, 42500, 85000}, ++{ 85000, 170000, 1000, 850000, 1700000, 0x11, 0x00, 0x07, 340, 0x146, 0x00A, 0, 0, 0, 1700000, 3400000, 0, 1, 1, 2, 2, 0x01, 85000, 170000}, ++{170000, 340000, 1000, 1700000, 3400000, 0x22, 0x01, 0x07, 340, 0x146, 0x00A, 0, 0, 0, 1700000, 3400000, 0, 1, 1, 2, 1, 0x00, 170000, 340000}, ++{340000, 600000, 1000, 3400000, 6000000, 0x3C, 0x03, 0x06, 600, 0x24A, 0x00A, 0, 0, 0, 3400000, 6000000, 1, 1, 1, 2, 1, 0x00, 340000, 600000}, ++{ 25000, 34000, 1205, 312500, 425000, 0x04, 0x01, 0x01, 400, 0x182, 0x00A, 0, 0, 0, 2500000, 3400000, 0, 2, 2, 2, 4, 0x03, 31250, 42500}, ++{ 34000, 68000, 1205, 425000, 850000, 0x06, 0x02, 0x01, 300, 0x11E, 0x00A, 0, 0, 0, 1700000, 3400000, 0, 1, 1, 2, 4, 0x02, 42500, 85000}, ++{ 68000, 136000, 1205, 850000, 1700000, 0x0D, 0x02, 0x02, 325, 0x137, 0x00A, 0, 0, 0, 1700000, 3400000, 0, 1, 1, 2, 2, 0x01, 85000, 170000}, ++{136000, 272000, 1205, 1700000, 3400000, 0x1A, 0x02, 0x04, 325, 0x137, 0x00A, 0, 0, 0, 1700000, 3400000, 0, 1, 1, 2, 1, 0x00, 170000, 340000}, ++{272000, 480000, 1205, 3400000, 6000000, 0x30, 0x03, 0x05, 600, 0x24A, 0x00A, 0, 0, 0, 3400000, 6000000, 1, 1, 1, 2, 1, 0x00, 340000, 600000}, ++{ 25000, 28000, 1500, 375000, 420000, 0x03, 0x01, 0x01, 360, 0x15A, 0x00A, 0, 0, 0, 3000000, 3360000, 0, 2, 2, 2, 4, 0x03, 37500, 42000}, ++{ 28000, 56000, 1500, 420000, 840000, 0x06, 0x02, 0x01, 360, 0x15A, 0x00A, 0, 0, 0, 1680000, 3360000, 0, 1, 1, 2, 4, 0x02, 42000, 84000}, ++{ 56000, 113000, 1500, 840000, 1695000, 0x0B, 0x00, 0x05, 330, 0x13C, 0x00A, 0, 0, 0, 1680000, 3390000, 0, 1, 1, 2, 2, 0x01, 84000, 169500}, ++{113000, 226000, 1500, 1695000, 3390000, 0x16, 0x01, 0x05, 330, 0x13C, 0x00A, 0, 0, 0, 1695000, 3390000, 0, 1, 1, 2, 1, 0x00, 169500, 339000}, ++{226000, 400000, 1500, 3390000, 6000000, 0x28, 0x03, 0x04, 600, 0x24A, 0x00A, 0, 0, 0, 3390000, 6000000, 1, 1, 1, 2, 1, 0x00, 339000, 600000}, ++{ 25000, 42500, 2000, 500000, 850000, 0x05, 0x01, 0x01, 400, 0x182, 0x00A, 0, 0, 0, 2000000, 3400000, 0, 1, 1, 2, 4, 0x02, 50000, 85000}, ++{ 42500, 85000, 2000, 850000, 1700000, 0x08, 0x03, 0x01, 320, 0x132, 0x00A, 0, 0, 0, 1700000, 3400000, 0, 1, 1, 2, 2, 0x01, 85000, 170000}, ++{ 85000, 170000, 2000, 1700000, 3400000, 0x11, 0x00, 0x07, 340, 0x146, 0x00A, 0, 0, 0, 1700000, 3400000, 0, 1, 1, 2, 1, 0x00, 170000, 340000}, ++{170000, 300000, 2000, 3400000, 6000000, 0x22, 0x01, 0x06, 680, 0x29A, 0x00A, 0, 0, 0, 3400000, 6000000, 1, 1, 1, 2, 1, 0x00, 340000, 600000}, ++{594000, 594000, 5000, 2970000, 2970000, 0x3C, 0x03, 0x06, 600, 0x24A, 0x00A, 0, 0, 0, 5940000, 5940000, 1, 1, 1, 2, 2, 0x01, 297000, 297000}, ++{594000, 594000, 6250, 3712500, 3712500, 0x3C, 0x03, 0x06, 375, 0x169, 0x00A, 0, 0, 0, 3712500, 3712500, 1, 1, 1, 2, 1, 0x00, 371250, 371250}, ++{594000, 594000, 7500, 4455000, 4455000, 0x3C, 0x03, 0x06, 450, 0x1B4, 0x00A, 0, 0, 0, 4455000, 4455000, 1, 1, 1, 2, 1, 0x00, 445500, 445500}, ++}; ++ ++/* HDMI TX PLL tuning settings */ ++struct hdmi_pll_tuning { ++ u32 vco_freq_bin; ++ u32 vco_freq_min; ++ u32 vco_freq_max; ++ u32 volt_to_current_coarse; ++ u32 volt_to_current; ++ u32 ndac_ctrl; ++ u32 pmos_ctrl; ++ u32 ptat_ndac_ctrl; ++ u32 feedback_div_total; ++ u32 charge_pump_gain; ++ u32 coarse_code; ++ u32 v2i_code; ++ u32 vco_cal_code; ++}; ++ ++/* HDMI TX PLL tuning settings, pixel clock is output */ ++static const struct hdmi_pll_tuning imx8mq_pll_table[] = { ++/* bin VCO_freq min/max coar cod NDAC PMOS PTAT div-T P-Gain Coa V2I CAL */ ++ { 1, 1980000, 1980000, 0x4, 0x3, 0x0, 0x09, 0x09, 220, 0x42, 160, 5, 183 }, ++ { 2, 2160000, 2160000, 0x4, 0x3, 0x0, 0x09, 0x09, 240, 0x42, 166, 6, 208 }, ++ { 2, 2376000, 2376000, 0x4, 0x3, 0x0, 0x09, 0x09, 264, 0x42, 166, 6, 208 }, ++ { 3, 2475000, 2475000, 0x5, 0x3, 0x1, 0x00, 0x07, 275, 0x42, 167, 6, 209 }, ++ { 4, 2700000, 2700000, 0x5, 0x3, 0x1, 0x00, 0x07, 300, 0x42, 188, 6, 230 }, ++ { 4, 2700000, 2700000, 0x5, 0x3, 0x1, 0x00, 0x07, 400, 0x4C, 188, 6, 230 }, ++ { 5, 2970000, 2970000, 0x6, 0x3, 0x1, 0x00, 0x07, 330, 0x42, 183, 6, 225 }, ++ { 6, 3240000, 3240000, 0x6, 0x3, 0x1, 0x00, 0x07, 360, 0x42, 203, 7, 256 }, ++ { 6, 3240000, 3240000, 0x6, 0x3, 0x1, 0x00, 0x07, 480, 0x4C, 203, 7, 256 }, ++ { 7, 3712500, 3712500, 0x4, 0x3, 0x0, 0x07, 0x0F, 550, 0x4C, 212, 7, 257 }, ++ { 8, 3960000, 3960000, 0x5, 0x3, 0x0, 0x07, 0x0F, 440, 0x42, 184, 6, 226 }, ++ { 9, 4320000, 4320000, 0x5, 0x3, 0x1, 0x07, 0x0F, 480, 0x42, 205, 7, 258 }, ++ { 10, 4455000, 4455000, 0x5, 0x3, 0x0, 0x07, 0x0F, 495, 0x42, 219, 7, 272 }, ++ { 10, 4455000, 4455000, 0x5, 0x3, 0x0, 0x07, 0x0F, 660, 0x4C, 219, 7, 272 }, ++ { 11, 4950000, 4950000, 0x6, 0x3, 0x1, 0x00, 0x07, 550, 0x42, 213, 7, 258 }, ++ { 12, 5940000, 5940000, 0x7, 0x3, 0x1, 0x00, 0x07, 660, 0x42, 244, 8, 292 }, ++}; ++ ++/* HDMI TX PLL tuning settings, pixel clock is input */ ++static const struct hdmi_pll_tuning imx8qm_pll_table[] = { ++/* bin VCO_freq min/max coar cod NDAC PMOS PTAT div-T P-Gain pad only */ ++ { 0, 1700000, 2000000, 0x3, 0x1, 0x0, 0x8C, 0x2E, 300, 0x08D, 0, 0, 0 }, ++ { 0, 1700000, 2000000, 0x3, 0x1, 0x0, 0x8C, 0x2E, 320, 0x08E, 0, 0, 0 }, ++ { 0, 1700000, 2000000, 0x3, 0x1, 0x0, 0x8C, 0x2E, 325, 0x08E, 0, 0, 0 }, ++ { 0, 1700000, 2000000, 0x3, 0x1, 0x0, 0x8C, 0x2E, 330, 0x08E, 0, 0, 0 }, ++ { 0, 1700000, 2000000, 0x3, 0x1, 0x0, 0x8C, 0x2E, 340, 0x08F, 0, 0, 0 }, ++ { 0, 1700000, 2000000, 0x3, 0x1, 0x0, 0x8C, 0x2E, 360, 0x0A7, 0, 0, 0 }, ++ { 0, 1700000, 2000000, 0x3, 0x1, 0x0, 0x8C, 0x2E, 400, 0x0C5, 0, 0, 0 }, ++ { 1, 2000000, 2400000, 0x3, 0x1, 0x0, 0x8C, 0x2E, 300, 0x086, 0, 0, 0 }, ++ { 1, 2000000, 2400000, 0x3, 0x1, 0x0, 0x8C, 0x2E, 320, 0x087, 0, 0, 0 }, ++ { 1, 2000000, 2400000, 0x3, 0x1, 0x0, 0x8C, 0x2E, 325, 0x087, 0, 0, 0 }, ++ { 1, 2000000, 2400000, 0x3, 0x1, 0x0, 0x8C, 0x2E, 330, 0x104, 0, 0, 0 }, ++ { 1, 2000000, 2400000, 0x3, 0x1, 0x0, 0x8C, 0x2E, 340, 0x08B, 0, 0, 0 }, ++ { 1, 2000000, 2400000, 0x3, 0x1, 0x0, 0x8C, 0x2E, 360, 0x08D, 0, 0, 0 }, ++ { 1, 2000000, 2400000, 0x3, 0x1, 0x0, 0x8C, 0x2E, 400, 0x0A6, 0, 0, 0 }, ++ { 2, 2400000, 2800000, 0x3, 0x1, 0x0, 0x04, 0x0D, 300, 0x04E, 0, 0, 0 }, ++ { 2, 2400000, 2800000, 0x3, 0x1, 0x0, 0x04, 0x0D, 320, 0x04F, 0, 0, 0 }, ++ { 2, 2400000, 2800000, 0x3, 0x1, 0x0, 0x04, 0x0D, 325, 0x04F, 0, 0, 0 }, ++ { 2, 2400000, 2800000, 0x3, 0x1, 0x0, 0x04, 0x0D, 330, 0x085, 0, 0, 0 }, ++ { 2, 2400000, 2800000, 0x3, 0x1, 0x0, 0x04, 0x0D, 340, 0x085, 0, 0, 0 }, ++ { 2, 2400000, 2800000, 0x3, 0x1, 0x0, 0x04, 0x0D, 360, 0x086, 0, 0, 0 }, ++ { 2, 2400000, 2800000, 0x3, 0x1, 0x0, 0x04, 0x0D, 400, 0x08B, 0, 0, 0 }, ++ { 3, 2800000, 3400000, 0x3, 0x1, 0x0, 0x04, 0x0D, 300, 0x047, 0, 0, 0 }, ++ { 3, 2800000, 3400000, 0x3, 0x1, 0x0, 0x04, 0x0D, 320, 0x04B, 0, 0, 0 }, ++ { 3, 2800000, 3400000, 0x3, 0x1, 0x0, 0x04, 0x0D, 325, 0x04B, 0, 0, 0 }, ++ { 3, 2800000, 3400000, 0x3, 0x1, 0x0, 0x04, 0x0D, 330, 0x04B, 0, 0, 0 }, ++ { 3, 2800000, 3400000, 0x3, 0x1, 0x0, 0x04, 0x0D, 340, 0x04D, 0, 0, 0 }, ++ { 3, 2800000, 3400000, 0x3, 0x1, 0x0, 0x04, 0x0D, 360, 0x04E, 0, 0, 0 }, ++ { 3, 2800000, 3400000, 0x3, 0x1, 0x0, 0x04, 0x0D, 400, 0x085, 0, 0, 0 }, ++ { 4, 3400000, 3900000, 0x7, 0x1, 0x0, 0x8E, 0x2F, 375, 0x041, 0, 0, 0 }, ++ { 4, 3400000, 3900000, 0x7, 0x1, 0x0, 0x8E, 0x2F, 600, 0x08D, 0, 0, 0 }, ++ { 4, 3400000, 3900000, 0x7, 0x1, 0x0, 0x8E, 0x2F, 680, 0x0A6, 0, 0, 0 }, ++ { 5, 3900000, 4500000, 0x7, 0x1, 0x0, 0x8E, 0x2F, 450, 0x041, 0, 0, 0 }, ++ { 5, 3900000, 4500000, 0x7, 0x1, 0x0, 0x8E, 0x2F, 600, 0x087, 0, 0, 0 }, ++ { 5, 3900000, 4500000, 0x7, 0x1, 0x0, 0x8E, 0x2F, 680, 0x0A4, 0, 0, 0 }, ++ { 6, 4500000, 5200000, 0x7, 0x1, 0x0, 0x04, 0x0D, 600, 0x04F, 0, 0, 0 }, ++ { 6, 4500000, 5200000, 0x7, 0x1, 0x0, 0x04, 0x0D, 680, 0x086, 0, 0, 0 }, ++ { 7, 5200000, 6000000, 0x7, 0x1, 0x0, 0x04, 0x0D, 600, 0x04D, 0, 0, 0 }, ++ { 7, 5200000, 6000000, 0x7, 0x1, 0x0, 0x04, 0x0D, 680, 0x04F, 0, 0, 0 } ++}; ++ ++static void hdmi_arc_config(struct cdns_mhdp_device *mhdp) ++{ ++ u16 txpu_calib_code; ++ u16 txpd_calib_code; ++ u16 txpu_adj_calib_code; ++ u16 txpd_adj_calib_code; ++ u16 prev_calib_code; ++ u16 new_calib_code; ++ u16 rdata; ++ ++ /* Power ARC */ ++ cdns_phy_reg_write(mhdp, TXDA_CYA_AUXDA_CYA, 0x0001); ++ ++ prev_calib_code = cdns_phy_reg_read(mhdp, TX_DIG_CTRL_REG_2); ++ txpu_calib_code = cdns_phy_reg_read(mhdp, CMN_TXPUCAL_CTRL); ++ txpd_calib_code = cdns_phy_reg_read(mhdp, CMN_TXPDCAL_CTRL); ++ txpu_adj_calib_code = cdns_phy_reg_read(mhdp, CMN_TXPU_ADJ_CTRL); ++ txpd_adj_calib_code = cdns_phy_reg_read(mhdp, CMN_TXPD_ADJ_CTRL); ++ ++ new_calib_code = ((txpu_calib_code + txpd_calib_code) / 2) ++ + txpu_adj_calib_code + txpd_adj_calib_code; ++ ++ if (new_calib_code != prev_calib_code) { ++ rdata = cdns_phy_reg_read(mhdp, TX_ANA_CTRL_REG_1); ++ rdata &= 0xDFFF; ++ cdns_phy_reg_write(mhdp, TX_ANA_CTRL_REG_1, rdata); ++ cdns_phy_reg_write(mhdp, TX_DIG_CTRL_REG_2, new_calib_code); ++ mdelay(10); ++ rdata |= 0x2000; ++ cdns_phy_reg_write(mhdp, TX_ANA_CTRL_REG_1, rdata); ++ udelay(150); ++ } ++ ++ cdns_phy_reg_write(mhdp, TX_ANA_CTRL_REG_2, 0x0100); ++ udelay(100); ++ cdns_phy_reg_write(mhdp, TX_ANA_CTRL_REG_2, 0x0300); ++ udelay(100); ++ cdns_phy_reg_write(mhdp, TX_ANA_CTRL_REG_3, 0x0000); ++ udelay(100); ++ cdns_phy_reg_write(mhdp, TX_ANA_CTRL_REG_1, 0x2008); ++ udelay(100); ++ cdns_phy_reg_write(mhdp, TX_ANA_CTRL_REG_1, 0x2018); ++ udelay(100); ++ cdns_phy_reg_write(mhdp, TX_ANA_CTRL_REG_1, 0x2098); ++ cdns_phy_reg_write(mhdp, TX_ANA_CTRL_REG_2, 0x030C); ++ cdns_phy_reg_write(mhdp, TX_ANA_CTRL_REG_5, 0x0010); ++ udelay(100); ++ cdns_phy_reg_write(mhdp, TX_ANA_CTRL_REG_4, 0x4001); ++ mdelay(5); ++ cdns_phy_reg_write(mhdp, TX_ANA_CTRL_REG_1, 0x2198); ++ mdelay(5); ++ cdns_phy_reg_write(mhdp, TX_ANA_CTRL_REG_2, 0x030D); ++ udelay(100); ++ cdns_phy_reg_write(mhdp, TX_ANA_CTRL_REG_2, 0x030F); ++} ++ ++static void hdmi_phy_set_vswing(struct cdns_mhdp_device *mhdp) ++{ ++ const u32 num_lanes = 4; ++ u32 k; ++ ++ for (k = 0; k < num_lanes; k++) { ++ cdns_phy_reg_write(mhdp, (TX_DIAG_TX_DRV | (k << 9)), 0x7c0); ++ cdns_phy_reg_write(mhdp, (TX_TXCC_CPOST_MULT_00_0 | (k << 9)), 0x0); ++ cdns_phy_reg_write(mhdp, (TX_TXCC_CAL_SCLR_MULT_0 | (k << 9)), 0x120); ++ } ++} ++ ++static int hdmi_feedback_factor(struct cdns_mhdp_device *mhdp) ++{ ++ u32 feedback_factor; ++ ++ switch (mhdp->video_info.color_fmt) { ++ case YCBCR_4_2_2: ++ feedback_factor = 1000; ++ break; ++ case YCBCR_4_2_0: ++ switch (mhdp->video_info.color_depth) { ++ case 8: ++ feedback_factor = 500; ++ break; ++ case 10: ++ feedback_factor = 625; ++ break; ++ case 12: ++ feedback_factor = 750; ++ break; ++ case 16: ++ feedback_factor = 1000; ++ break; ++ default: ++ //DRM_ERROR("Invalid ColorDepth\n"); ++ printk(KERN_ALERT "Invalid ColorDepth %s %d \n",__FUNCTION__,__LINE__); ++ return 0; ++ } ++ break; ++ default: ++ /* Assume RGB/YUV444 */ ++ switch (mhdp->video_info.color_depth) { ++ case 10: ++ feedback_factor = 1250; ++ break; ++ case 12: ++ feedback_factor = 1500; ++ break; ++ case 16: ++ feedback_factor = 2000; ++ break; ++ default: ++ feedback_factor = 1000; ++ } ++ } ++ return feedback_factor; ++} ++ ++static int hdmi_phy_config(struct cdns_mhdp_device *mhdp, ++ const struct hdmi_ctrl *p_ctrl_table, ++ const struct hdmi_pll_tuning *p_pll_table, ++ char pclk_in) ++{ ++ const u32 num_lanes = 4; ++ u32 val, i, k; ++ ++ /* enable PHY isolation mode only for CMN */ ++ cdns_phy_reg_write(mhdp, PHY_PMA_ISOLATION_CTRL, 0xD000); ++ ++ /* set cmn_pll0_clk_datart1_div/cmn_pll0_clk_datart0_div dividers */ ++ val = cdns_phy_reg_read(mhdp, PHY_PMA_ISO_PLL_CTRL1); ++ val &= 0xFF00; ++ val |= 0x0012; ++ cdns_phy_reg_write(mhdp, PHY_PMA_ISO_PLL_CTRL1, val); ++ ++ /* assert PHY reset from isolation register */ ++ cdns_phy_reg_write(mhdp, PHY_ISO_CMN_CTRL, 0x0000); ++ /* assert PMA CMN reset */ ++ cdns_phy_reg_write(mhdp, PHY_PMA_ISO_CMN_CTRL, 0x0000); ++ ++ /* register XCVR_DIAG_BIDI_CTRL */ ++ for (k = 0; k < num_lanes; k++) ++ cdns_phy_reg_write(mhdp, XCVR_DIAG_BIDI_CTRL | (k << 9), 0x00FF); ++ ++ /* Describing Task phy_cfg_hdp */ ++ ++ val = cdns_phy_reg_read(mhdp, PHY_PMA_CMN_CTRL1); ++ val &= 0xFFF7; ++ val |= 0x0008; ++ cdns_phy_reg_write(mhdp, PHY_PMA_CMN_CTRL1, val); ++ ++ /* PHY Registers */ ++ val = cdns_phy_reg_read(mhdp, PHY_PMA_CMN_CTRL1); ++ val &= 0xCFFF; ++ val |= p_ctrl_table->cmn_ref_clk_dig_div << 12; ++ cdns_phy_reg_write(mhdp, PHY_PMA_CMN_CTRL1, val); ++ ++ val = cdns_phy_reg_read(mhdp, PHY_HDP_CLK_CTL); ++ val &= 0x00FF; ++ val |= 0x1200; ++ cdns_phy_reg_write(mhdp, PHY_HDP_CLK_CTL, val); ++ ++ /* Common control module control and diagnostic registers */ ++ val = cdns_phy_reg_read(mhdp, CMN_CDIAG_REFCLK_CTRL); ++ val &= 0x8FFF; ++ val |= p_ctrl_table->ref_clk_divider_scaler << 12; ++ val |= 0x00C0; ++ cdns_phy_reg_write(mhdp, CMN_CDIAG_REFCLK_CTRL, val); ++ ++ /* High speed clock used */ ++ val = cdns_phy_reg_read(mhdp, CMN_DIAG_HSCLK_SEL); ++ val &= 0xFF00; ++ val |= (p_ctrl_table->cmnda_hs_clk_0_sel >> 1) << 0; ++ val |= (p_ctrl_table->cmnda_hs_clk_1_sel >> 1) << 4; ++ cdns_phy_reg_write(mhdp, CMN_DIAG_HSCLK_SEL, val); ++ ++ for (k = 0; k < num_lanes; k++) { ++ val = cdns_phy_reg_read(mhdp, (XCVR_DIAG_HSCLK_SEL | (k << 9))); ++ val &= 0xCFFF; ++ val |= (p_ctrl_table->cmnda_hs_clk_0_sel >> 1) << 12; ++ cdns_phy_reg_write(mhdp, (XCVR_DIAG_HSCLK_SEL | (k << 9)), val); ++ } ++ ++ /* PLL 0 control state machine registers */ ++ val = p_ctrl_table->vco_ring_select << 12; ++ cdns_phy_reg_write(mhdp, CMN_PLLSM0_USER_DEF_CTRL, val); ++ ++ if (pclk_in == true) ++ val = 0x30A0; ++ else { ++ val = cdns_phy_reg_read(mhdp, CMN_PLL0_VCOCAL_START); ++ val &= 0xFE00; ++ val |= p_pll_table->vco_cal_code; ++ } ++ cdns_phy_reg_write(mhdp, CMN_PLL0_VCOCAL_START, val); ++ ++ cdns_phy_reg_write(mhdp, CMN_PLL0_VCOCAL_INIT_TMR, 0x0064); ++ cdns_phy_reg_write(mhdp, CMN_PLL0_VCOCAL_ITER_TMR, 0x000A); ++ ++ /* Common functions control and diagnostics registers */ ++ val = p_ctrl_table->cmnda_pll0_hs_sym_div_sel << 8; ++ val |= p_ctrl_table->cmnda_pll0_ip_div; ++ cdns_phy_reg_write(mhdp, CMN_DIAG_PLL0_INCLK_CTRL, val); ++ ++ cdns_phy_reg_write(mhdp, CMN_DIAG_PLL0_OVRD, 0x0000); ++ ++ val = p_ctrl_table->cmnda_pll0_fb_div_high; ++ val |= (1 << 15); ++ cdns_phy_reg_write(mhdp, CMN_DIAG_PLL0_FBH_OVRD, val); ++ ++ val = p_ctrl_table->cmnda_pll0_fb_div_low; ++ val |= (1 << 15); ++ cdns_phy_reg_write(mhdp, CMN_DIAG_PLL0_FBL_OVRD, val); ++ ++ if (pclk_in == false) { ++ val = p_ctrl_table->cmnda_pll0_pxdiv_low; ++ cdns_phy_reg_write(mhdp, CMN_DIAG_PLL0_PXL_DIVL, val); ++ ++ val = p_ctrl_table->cmnda_pll0_pxdiv_high; ++ val |= (1 << 15); ++ cdns_phy_reg_write(mhdp, CMN_DIAG_PLL0_PXL_DIVH, val); ++ } ++ ++ val = p_pll_table->volt_to_current_coarse; ++ val |= (p_pll_table->volt_to_current) << 4; ++ cdns_phy_reg_write(mhdp, CMN_DIAG_PLL0_V2I_TUNE, val); ++ ++ val = p_pll_table->charge_pump_gain; ++ cdns_phy_reg_write(mhdp, CMN_DIAG_PLL0_CP_TUNE, val); ++ ++ cdns_phy_reg_write(mhdp, CMN_DIAG_PLL0_LF_PROG, 0x0008); ++ ++ val = p_pll_table->pmos_ctrl; ++ val |= (p_pll_table->ndac_ctrl) << 8; ++ cdns_phy_reg_write(mhdp, CMN_DIAG_PLL0_PTATIS_TUNE1, val); ++ ++ val = p_pll_table->ptat_ndac_ctrl; ++ cdns_phy_reg_write(mhdp, CMN_DIAG_PLL0_PTATIS_TUNE2, val); ++ ++ if (pclk_in == true) ++ cdns_phy_reg_write(mhdp, CMN_DIAG_PLL0_TEST_MODE, 0x0022); ++ else ++ cdns_phy_reg_write(mhdp, CMN_DIAG_PLL0_TEST_MODE, 0x0020); ++ cdns_phy_reg_write(mhdp, CMN_PSM_CLK_CTRL, 0x0016); ++ ++ /* Transceiver control and diagnostic registers */ ++ for (k = 0; k < num_lanes; k++) { ++ val = cdns_phy_reg_read(mhdp, (XCVR_DIAG_PLLDRC_CTRL | (k << 9))); ++ val &= 0xBFFF; ++ cdns_phy_reg_write(mhdp, (XCVR_DIAG_PLLDRC_CTRL | (k << 9)), val); ++ } ++ ++ for (k = 0; k < num_lanes; k++) { ++ val = cdns_phy_reg_read(mhdp, (TX_DIAG_TX_CTRL | (k << 9))); ++ val &= 0xFF3F; ++ val |= (p_ctrl_table->hsclk_div_tx_sub_rate >> 1) << 6; ++ cdns_phy_reg_write(mhdp, (TX_DIAG_TX_CTRL | (k << 9)), val); ++ } ++ ++ /* ++ * for single ended reference clock val |= 0x0030; ++ * for differential clock val |= 0x0000; ++ */ ++ val = cdns_phy_reg_read(mhdp, PHY_PMA_CMN_CTRL1); ++ val &= 0xFF8F; ++ if (pclk_in == true) ++ val |= 0x0030; ++ cdns_phy_reg_write(mhdp, PHY_PMA_CMN_CTRL1, val); ++ ++ /* for differential clock on the refclk_p and ++ * refclk_m off chip pins: CMN_DIAG_ACYA[8]=1'b1 */ ++ cdns_phy_reg_write(mhdp, CMN_DIAG_ACYA, 0x0100); ++ ++ /* Deassert PHY reset */ ++ cdns_phy_reg_write(mhdp, PHY_ISO_CMN_CTRL, 0x0001); ++ cdns_phy_reg_write(mhdp, PHY_PMA_ISO_CMN_CTRL, 0x0003); ++ ++ /* Power state machine registers */ ++ for (k = 0; k < num_lanes; k++) ++ cdns_phy_reg_write(mhdp, XCVR_PSM_RCTRL | (k << 9), 0xFEFC); ++ ++ /* Assert cmn_macro_pwr_en */ ++ cdns_phy_reg_write(mhdp, PHY_PMA_ISO_CMN_CTRL, 0x0013); ++ ++ /* wait for cmn_macro_pwr_en_ack */ ++ for (i = 0; i < 10; i++) { ++ val = cdns_phy_reg_read(mhdp, PHY_PMA_ISO_CMN_CTRL); ++ if (val & (1 << 5)) ++ break; ++ msleep(20); ++ } ++ if (i == 10) { ++ //DRM_ERROR("PMA ouput macro power up failed\n"); ++ ++ printk(KERN_ALERT "PMA ouput macro power up failed %s %d \n",__FUNCTION__,__LINE__); ++ return false; ++ } ++ ++ /* wait for cmn_ready */ ++ for (i = 0; i < 10; i++) { ++ val = cdns_phy_reg_read(mhdp, PHY_PMA_CMN_CTRL1); ++ if (val & (1 << 0)) ++ break; ++ msleep(20); ++ } ++ if (i == 10) { ++ //DRM_ERROR("PMA output ready failed\n"); ++ ++ printk(KERN_ALERT "PMA output ready failed %s %d \n",__FUNCTION__,__LINE__); ++ return false; ++ } ++ ++ for (k = 0; k < num_lanes; k++) { ++ cdns_phy_reg_write(mhdp, TX_PSC_A0 | (k << 9), 0x6791); ++ cdns_phy_reg_write(mhdp, TX_PSC_A1 | (k << 9), 0x6790); ++ cdns_phy_reg_write(mhdp, TX_PSC_A2 | (k << 9), 0x0090); ++ cdns_phy_reg_write(mhdp, TX_PSC_A3 | (k << 9), 0x0090); ++ ++ val = cdns_phy_reg_read(mhdp, RX_PSC_CAL | (k << 9)); ++ val &= 0xFFBB; ++ cdns_phy_reg_write(mhdp, RX_PSC_CAL | (k << 9), val); ++ ++ val = cdns_phy_reg_read(mhdp, RX_PSC_A0 | (k << 9)); ++ val &= 0xFFBB; ++ cdns_phy_reg_write(mhdp, RX_PSC_A0 | (k << 9), val); ++ } ++ return true; ++} ++ ++static int hdmi_phy_cfg_t28hpc(struct cdns_mhdp_device *mhdp, ++ struct drm_display_mode *mode) ++{ ++ const struct hdmi_ctrl *p_ctrl_table; ++ const struct hdmi_pll_tuning *p_pll_table; ++ const u32 refclk_freq_khz = 27000; ++ const u8 pclk_in = false; ++ u32 pixel_freq = mode->clock; ++ u32 vco_freq, char_freq; ++ u32 div_total, feedback_factor; ++ u32 i, ret; ++ ++ feedback_factor = hdmi_feedback_factor(mhdp); ++ ++ char_freq = pixel_freq * feedback_factor / 1000; ++ ++ dev_info(mhdp->dev, "Pixel clock: %d KHz, character clock: %d, bpc is %0d-bit.\n", ++ pixel_freq, char_freq, mhdp->video_info.color_depth); ++ ++ /* Get right row from the ctrl_table table. ++ * Check if 'pixel_freq_khz' value matches the PIXEL_CLK_FREQ column. ++ * Consider only the rows with FEEDBACK_FACTOR column matching feedback_factor. */ ++ for (i = 0; i < ARRAY_SIZE(imx8mq_ctrl_table); i++) { ++ if (feedback_factor == imx8mq_ctrl_table[i].feedback_factor && ++ pixel_freq == imx8mq_ctrl_table[i].pixel_clk_freq_min) { ++ p_ctrl_table = &imx8mq_ctrl_table[i]; ++ break; ++ } ++ } ++ if (i == ARRAY_SIZE(imx8mq_ctrl_table)) { ++ dev_warn(mhdp->dev,"Pixel clk (%d KHz) not supported, color depth (%0d-bit)\n", ++ pixel_freq, mhdp->video_info.color_depth); ++ return 0; ++ } ++ ++ div_total = p_ctrl_table->pll_fb_div_total; ++ vco_freq = refclk_freq_khz * div_total / p_ctrl_table->cmnda_pll0_ip_div; ++ ++ /* Get right row from the imx8mq_pll_table table. ++ * Check if vco_freq_khz and feedback_div_total ++ * column matching with imx8mq_pll_table. */ ++ for (i = 0; i < ARRAY_SIZE(imx8mq_pll_table); i++) { ++ if (vco_freq == imx8mq_pll_table[i].vco_freq_min && ++ div_total == imx8mq_pll_table[i].feedback_div_total) { ++ p_pll_table = &imx8mq_pll_table[i]; ++ break; ++ } ++ } ++ if (i == ARRAY_SIZE(imx8mq_pll_table)) { ++ dev_warn(mhdp->dev,"VCO (%d KHz) not supported\n", vco_freq); ++ return 0; ++ } ++ dev_info(mhdp->dev, "VCO frequency is %d KHz\n", vco_freq); ++ ++ ret = hdmi_phy_config(mhdp, p_ctrl_table, p_pll_table, pclk_in); ++ if (ret == false) ++ return 0; ++ ++ return char_freq; ++} ++ ++static int hdmi_phy_cfg_ss28fdsoi(struct cdns_mhdp_device *mhdp, ++ struct drm_display_mode *mode) ++{ ++ const struct hdmi_ctrl *p_ctrl_table; ++ const struct hdmi_pll_tuning *p_pll_table; ++ const u8 pclk_in = true; ++ u32 pixel_freq = mode->clock; ++ u32 vco_freq, char_freq; ++ u32 div_total, feedback_factor; ++ u32 ret, i; ++ ++ feedback_factor = hdmi_feedback_factor(mhdp); ++ ++ char_freq = pixel_freq * feedback_factor / 1000; ++ ++ dev_info(mhdp->dev, "Pixel clock: %d KHz, character clock: %d, bpc is %0d-bit.\n", ++ pixel_freq, char_freq, mhdp->video_info.color_depth); ++ ++ /* Get right row from the ctrl_table table. ++ * Check if 'pixel_freq_khz' value matches the PIXEL_CLK_FREQ column. ++ * Consider only the rows with FEEDBACK_FACTOR column matching feedback_factor. */ ++ for (i = 0; i < ARRAY_SIZE(imx8qm_ctrl_table); i++) { ++ if (feedback_factor == imx8qm_ctrl_table[i].feedback_factor && ++ pixel_freq >= imx8qm_ctrl_table[i].pixel_clk_freq_min && ++ pixel_freq <= imx8qm_ctrl_table[i].pixel_clk_freq_max) { ++ p_ctrl_table = &imx8qm_ctrl_table[i]; ++ break; ++ } ++ } ++ if (i == ARRAY_SIZE(imx8qm_ctrl_table)) { ++ dev_warn(mhdp->dev,"Pixel clk (%d KHz) not supported, color depth (%0d-bit)\n", ++ pixel_freq, mhdp->video_info.color_depth); ++ return 0; ++ } ++ ++ div_total = p_ctrl_table->pll_fb_div_total; ++ vco_freq = pixel_freq * div_total / p_ctrl_table->cmnda_pll0_ip_div; ++ ++ /* Get right row from the imx8mq_pll_table table. ++ * Check if vco_freq_khz and feedback_div_total ++ * column matching with imx8mq_pll_table. */ ++ for (i = 0; i < ARRAY_SIZE(imx8qm_pll_table); i++) { ++ if (vco_freq >= imx8qm_pll_table[i].vco_freq_min && ++ vco_freq < imx8qm_pll_table[i].vco_freq_max && ++ div_total == imx8qm_pll_table[i].feedback_div_total) { ++ p_pll_table = &imx8qm_pll_table[i]; ++ break; ++ } ++ } ++ if (i == ARRAY_SIZE(imx8qm_pll_table)) { ++ dev_warn(mhdp->dev,"VCO (%d KHz) not supported\n", vco_freq); ++ return 0; ++ } ++ ++ dev_info(mhdp->dev, "VCO frequency is %d KHz\n", vco_freq); ++ ++ ret = hdmi_phy_config(mhdp, p_ctrl_table, p_pll_table, pclk_in); ++ if (ret == false) ++ return 0; ++ ++ return char_freq; ++} ++ ++static int hdmi_phy_power_up(struct cdns_mhdp_device *mhdp) ++{ ++ u32 val, i; ++ ++ /* set Power State to A2 */ ++ cdns_phy_reg_write(mhdp, PHY_HDP_MODE_CTRL, 0x0004); ++ ++ cdns_phy_reg_write(mhdp, TX_DIAG_ACYA_0, 1); ++ cdns_phy_reg_write(mhdp, TX_DIAG_ACYA_1, 1); ++ cdns_phy_reg_write(mhdp, TX_DIAG_ACYA_2, 1); ++ cdns_phy_reg_write(mhdp, TX_DIAG_ACYA_3, 1); ++ ++ /* Wait for Power State A2 Ack */ ++ for (i = 0; i < 10; i++) { ++ val = cdns_phy_reg_read(mhdp, PHY_HDP_MODE_CTRL); ++ if (val & (1 << 6)) ++ break; ++ msleep(20); ++ } ++ if (i == 10) { ++ dev_err(mhdp->dev, "Wait A2 Ack failed\n"); ++ return -1; ++ } ++ ++ /* Power up ARC */ ++ hdmi_arc_config(mhdp); ++ ++ /* Configure PHY in A0 mode (PHY must be in the A0 power ++ * state in order to transmit data) ++ */ ++ ++ printk(KERN_ALERT "DEBUG: %s %d \n",__FUNCTION__,__LINE__); ++ ++ // FIXME ++ cdns_phy_reg_write(mhdp, PHY_HDP_MODE_CTRL, 0x0101); //imx8mq ++ //cdns_phy_reg_write(mhdp, PHY_HDP_MODE_CTRL, 0x0001); ++ ++ /* Wait for Power State A0 Ack */ ++ for (i = 0; i < 10; i++) { ++ val = cdns_phy_reg_read(mhdp, PHY_HDP_MODE_CTRL); ++ if (val & (1 << 4)) ++ break; ++ msleep(20); ++ } ++ if (i == 10) { ++ dev_err(mhdp->dev, "Wait A0 Ack failed\n"); ++ return -1; ++ } ++ ++ printk(KERN_ALERT "DEBUG: %s %d \n",__FUNCTION__,__LINE__); ++ return 0; ++} ++ ++bool cdns_hdmi_phy_video_valid_imx8mq(struct cdns_mhdp_device *mhdp) ++{ ++ u32 rate = mhdp->valid_mode->clock; ++ int i; ++ ++ for (i = 0; i < ARRAY_SIZE(imx8mq_ctrl_table); i++) ++ if(rate == imx8mq_ctrl_table[i].pixel_clk_freq_min) ++ return true; ++ return false; ++} ++ ++int cdns_hdmi_phy_set_imx8mq(struct cdns_mhdp_device *mhdp) ++{ ++ struct drm_display_mode *mode = &mhdp->mode; ++ int ret; ++ ++ /* Check HDMI FW alive before HDMI PHY init */ ++ ret = cdns_mhdp_check_alive(mhdp); ++ if (ret == false) { ++ dev_err(mhdp->dev, "NO HDMI FW running\n"); ++ return -ENXIO; ++ } ++ ++ /* Configure PHY */ ++ mhdp->hdmi.char_rate = hdmi_phy_cfg_t28hpc(mhdp, mode); ++ if (mhdp->hdmi.char_rate == 0) { ++ dev_err(mhdp->dev, "failed to set phy pclock\n"); ++ return -EINVAL; ++ } ++ ++ ret = hdmi_phy_power_up(mhdp); ++ if (ret < 0) ++ return ret; ++ ++ hdmi_phy_set_vswing(mhdp); ++ ++ return true; ++} ++ ++bool cdns_hdmi_phy_video_valid_imx8qm(struct cdns_mhdp_device *mhdp) ++{ ++ u32 rate = mhdp->valid_mode->clock; ++ int i; ++ ++ for (i = 0; i < ARRAY_SIZE(imx8qm_ctrl_table); i++) ++ if(rate >= imx8qm_ctrl_table[i].pixel_clk_freq_min && ++ rate <= imx8qm_ctrl_table[i].pixel_clk_freq_max) ++ return true; ++ return false; ++} ++ ++int cdns_hdmi_phy_set_imx8qm(struct cdns_mhdp_device *mhdp) ++{ ++ struct drm_display_mode *mode = &mhdp->mode; ++ int ret; ++ ++ /* Check HDMI FW alive before HDMI PHY init */ ++ ret = cdns_mhdp_check_alive(mhdp); ++ if (ret == false) { ++ dev_err(mhdp->dev, "NO HDMI FW running\n"); ++ return -ENXIO; ++ } ++ ++ /* Configure PHY */ ++ mhdp->hdmi.char_rate = hdmi_phy_cfg_ss28fdsoi(mhdp, mode); ++ if (mhdp->hdmi.char_rate == 0) { ++ dev_err(mhdp->dev, "failed to set phy pclock\n"); ++ return -EINVAL; ++ } ++ ++ ret = hdmi_phy_power_up(mhdp); ++ if (ret < 0) ++ return ret; ++ ++ hdmi_phy_set_vswing(mhdp); ++ ++ return true; ++} +diff --git a/drivers/gpu/drm/imx/cdn-mhdp-imxdrv.c b/drivers/gpu/drm/imx/cdn-mhdp-imxdrv.c +new file mode 100644 +index 000000000000..daee92cb9ce5 +--- /dev/null ++++ b/drivers/gpu/drm/imx/cdn-mhdp-imxdrv.c +@@ -0,0 +1,211 @@ ++/* ++ * copyright (c) 2019 nxp semiconductor, inc. ++ * ++ * this program is free software; you can redistribute it and/or modify ++ * it under the terms of the gnu general public license version 2 as ++ * published by the free software foundation. ++ */ ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#include "cdns-mhdp-imx.h" ++#include "cdn-mhdp-phy.h" ++#include "imx-drm.h" ++ ++static void cdns_mhdp_imx_encoder_disable(struct drm_encoder *encoder) ++{ ++ // FIXME ++ struct drm_bridge* bridge = drm_bridge_chain_get_first_bridge(encoder); ++ struct cdns_mhdp_device *mhdp = bridge->driver_private; ++ ++ cdns_mhdp_plat_call(mhdp, plat_init); ++} ++ ++static void cdns_mhdp_imx_encoder_enable(struct drm_encoder *encoder) ++{ ++ // FIXME ++ struct drm_bridge* bridge = drm_bridge_chain_get_first_bridge(encoder); ++ struct cdns_mhdp_device *mhdp = bridge->driver_private; ++ ++ cdns_mhdp_plat_call(mhdp, plat_deinit); ++} ++ ++static int cdns_mhdp_imx_encoder_atomic_check(struct drm_encoder *encoder, ++ struct drm_crtc_state *crtc_state, ++ struct drm_connector_state *conn_state) ++{ ++ // FIXME ++ struct drm_bridge* bridge = drm_bridge_chain_get_first_bridge(encoder); ++ struct imx_crtc_state *imx_crtc_state = to_imx_crtc_state(crtc_state); ++ struct cdns_mhdp_device *mhdp = bridge->driver_private; ++ ++ if (mhdp->plat_data->video_format != 0) ++ imx_crtc_state->bus_format = mhdp->plat_data->video_format; ++ ++ if (mhdp->force_mode_set) ++ crtc_state->mode_changed = true; ++ ++ return 0; ++} ++ ++static const struct drm_encoder_helper_funcs cdns_mhdp_imx_encoder_helper_funcs = { ++ .enable = cdns_mhdp_imx_encoder_enable, ++ .disable = cdns_mhdp_imx_encoder_disable, ++ .atomic_check = cdns_mhdp_imx_encoder_atomic_check, ++}; ++ ++static const struct drm_encoder_funcs cdns_mhdp_imx_encoder_funcs = { ++ .destroy = drm_encoder_cleanup, ++}; ++ ++static struct cdns_plat_data imx8mq_hdmi_drv_data = { ++ .plat_name = "imx8mq-hdmi", ++ .bind = cdns_hdmi_bind, ++ .unbind = cdns_hdmi_unbind, ++ .phy_set = cdns_hdmi_phy_set_imx8mq, ++ .phy_video_valid = cdns_hdmi_phy_video_valid_imx8mq, ++ .bus_type = BUS_TYPE_NORMAL_APB, ++}; ++ ++static struct cdns_plat_data imx8mq_dp_drv_data = { ++ .plat_name = "imx8mq-dp", ++ .bind = cdns_dp_bind, ++ .unbind = cdns_dp_unbind, ++ .phy_set = cdns_dp_phy_set_imx8mq, ++ .bus_type = BUS_TYPE_NORMAL_APB, ++}; ++ ++static const struct of_device_id cdns_mhdp_imx_dt_ids[] = { ++ { .compatible = "cdn,imx8mq-hdmi", ++ .data = &imx8mq_hdmi_drv_data ++ }, ++ /*{ .compatible = "cdn,imx8mq-dp", ++ .data = &imx8mq_dp_drv_data ++ }*/ ++ {}, ++}; ++MODULE_DEVICE_TABLE(of, cdns_mhdp_imx_dt_ids); ++ ++static int cdns_mhdp_imx_bind(struct device *dev, struct device *master, ++ void *data) ++{ ++ struct platform_device *pdev = to_platform_device(dev); ++ const struct cdns_plat_data *plat_data; ++ const struct of_device_id *match; ++ struct drm_device *drm = data; ++ struct drm_encoder *encoder; ++ struct imx_mhdp_device *imx_mhdp; ++ int ret; ++ ++ if (!pdev->dev.of_node) ++ return -ENODEV; ++ ++ imx_mhdp = devm_kzalloc(&pdev->dev, sizeof(*imx_mhdp), GFP_KERNEL); ++ if (!imx_mhdp) ++ return -ENOMEM; ++ ++ match = of_match_node(cdns_mhdp_imx_dt_ids, pdev->dev.of_node); ++ plat_data = match->data; ++ encoder = &imx_mhdp->encoder; ++ ++ encoder->possible_crtcs = drm_of_find_possible_crtcs(drm, dev->of_node); ++ ++ ret = of_property_read_string(pdev->dev.of_node, "firmware-name", ++ &imx_mhdp->firmware_name); ++ /* ++ * If we failed to find the CRTC(s) which this encoder is ++ * supposed to be connected to, it's because the CRTC has ++ * not been registered yet. Defer probing, and hope that ++ * the required CRTC is added later. ++ */ ++ if (encoder->possible_crtcs == 0) { ++ printk(KERN_ALERT "DEBUG: %s %d encoder crtcs not found.\n",__FUNCTION__,__LINE__); ++ ++ return -EPROBE_DEFER; ++ } ++ ++ drm_encoder_helper_add(encoder, &cdns_mhdp_imx_encoder_helper_funcs); ++ drm_encoder_init(drm, encoder, &cdns_mhdp_imx_encoder_funcs, ++ DRM_MODE_ENCODER_TMDS, NULL); ++ ++ ++ imx_mhdp->mhdp.plat_data = plat_data; ++ imx_mhdp->mhdp.dev = dev; ++ imx_mhdp->mhdp.bus_type = plat_data->bus_type; ++ ret = plat_data->bind(pdev, encoder, &imx_mhdp->mhdp); ++ /* ++ * If cdns_mhdp_bind() fails we'll never call cdns_mhdp_unbind(), ++ * which would have called the encoder cleanup. Do it manually. ++ */ ++ if (ret < 0) ++ drm_encoder_cleanup(encoder); ++ ++ return ret; ++} ++ ++static void cdns_mhdp_imx_unbind(struct device *dev, struct device *master, ++ void *data) ++{ ++ struct imx_mhdp_device *imx_mhdp = dev_get_drvdata(dev); ++ ++ imx_mhdp->mhdp.plat_data->unbind(dev); ++} ++ ++static const struct component_ops cdns_mhdp_imx_ops = { ++ .bind = cdns_mhdp_imx_bind, ++ .unbind = cdns_mhdp_imx_unbind, ++}; ++ ++static int cdns_mhdp_imx_suspend(struct device *dev) ++{ ++ struct imx_mhdp_device *imx_mhdp = dev_get_drvdata(dev); ++ ++ cdns_mhdp_plat_call(&imx_mhdp->mhdp, suspend); ++ ++ return 0; ++} ++ ++static int cdns_mhdp_imx_resume(struct device *dev) ++{ ++ struct imx_mhdp_device *imx_mhdp = dev_get_drvdata(dev); ++ ++ cdns_mhdp_plat_call(&imx_mhdp->mhdp, resume); ++ ++ return 0; ++} ++ ++static int cdns_mhdp_imx_probe(struct platform_device *pdev) ++{ ++ return component_add(&pdev->dev, &cdns_mhdp_imx_ops); ++} ++ ++static int cdns_mhdp_imx_remove(struct platform_device *pdev) ++{ ++ component_del(&pdev->dev, &cdns_mhdp_imx_ops); ++ ++ return 0; ++} ++ ++static const struct dev_pm_ops cdns_mhdp_imx_pm_ops = { ++ SET_LATE_SYSTEM_SLEEP_PM_OPS(cdns_mhdp_imx_suspend, cdns_mhdp_imx_resume) ++}; ++ ++static struct platform_driver cdns_mhdp_imx_platform_driver = { ++ .probe = cdns_mhdp_imx_probe, ++ .remove = cdns_mhdp_imx_remove, ++ .driver = { ++ .name = "cdns-mhdp-imx", ++ .of_match_table = cdns_mhdp_imx_dt_ids, ++ .pm = &cdns_mhdp_imx_pm_ops, ++ }, ++}; ++ ++module_platform_driver(cdns_mhdp_imx_platform_driver); ++ ++MODULE_AUTHOR("Sandor YU "); ++MODULE_LICENSE("GPL"); ++MODULE_ALIAS("platform:cdnhdmi-imx"); +diff --git a/drivers/gpu/drm/imx/cdn-mhdp-phy.h b/drivers/gpu/drm/imx/cdn-mhdp-phy.h +new file mode 100644 +index 000000000000..6ad1f372d0b8 +--- /dev/null ++++ b/drivers/gpu/drm/imx/cdn-mhdp-phy.h +@@ -0,0 +1,155 @@ ++/* ++ * Copyright (C) 2019 NXP Semiconductor, Inc. ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License as published by ++ * the Free Software Foundation; either version 2 of the License, or ++ * (at your option) any later version. ++ */ ++ ++#ifndef _CDN_DP_PHY_H ++#define _CDN_DP_PHY_H ++ ++#include ++ ++#define CMN_SSM_BIAS_TMR 0x0022 ++#define CMN_PLLSM0_PLLEN_TMR 0x0029 ++#define CMN_PLLSM0_PLLPRE_TMR 0x002A ++#define CMN_PLLSM0_PLLVREF_TMR 0x002B ++#define CMN_PLLSM0_PLLLOCK_TMR 0x002C ++#define CMN_PLLSM0_USER_DEF_CTRL 0x002F ++#define CMN_PSM_CLK_CTRL 0x0061 ++#define CMN_CDIAG_REFCLK_CTRL 0x0062 ++#define CMN_PLL0_VCOCAL_START 0x0081 ++#define CMN_PLL0_VCOCAL_INIT_TMR 0x0084 ++#define CMN_PLL0_VCOCAL_ITER_TMR 0x0085 ++#define CMN_PLL0_INTDIV 0x0094 ++#define CMN_PLL0_FRACDIV 0x0095 ++#define CMN_PLL0_HIGH_THR 0x0096 ++#define CMN_PLL0_DSM_DIAG 0x0097 ++#define CMN_PLL0_SS_CTRL1 0x0098 ++#define CMN_PLL0_SS_CTRL2 0x0099 ++#define CMN_ICAL_INIT_TMR 0x00C4 ++#define CMN_ICAL_ITER_TMR 0x00C5 ++#define CMN_RXCAL_INIT_TMR 0x00D4 ++#define CMN_RXCAL_ITER_TMR 0x00D5 ++#define CMN_TXPUCAL_CTRL 0x00E0 ++#define CMN_TXPUCAL_INIT_TMR 0x00E4 ++#define CMN_TXPUCAL_ITER_TMR 0x00E5 ++#define CMN_TXPDCAL_CTRL 0x00F0 ++#define CMN_TXPDCAL_INIT_TMR 0x00F4 ++#define CMN_TXPDCAL_ITER_TMR 0x00F5 ++#define CMN_ICAL_ADJ_INIT_TMR 0x0102 ++#define CMN_ICAL_ADJ_ITER_TMR 0x0103 ++#define CMN_RX_ADJ_INIT_TMR 0x0106 ++#define CMN_RX_ADJ_ITER_TMR 0x0107 ++#define CMN_TXPU_ADJ_CTRL 0x0108 ++#define CMN_TXPU_ADJ_INIT_TMR 0x010A ++#define CMN_TXPU_ADJ_ITER_TMR 0x010B ++#define CMN_TXPD_ADJ_CTRL 0x010c ++#define CMN_TXPD_ADJ_INIT_TMR 0x010E ++#define CMN_TXPD_ADJ_ITER_TMR 0x010F ++#define CMN_DIAG_PLL0_FBH_OVRD 0x01C0 ++#define CMN_DIAG_PLL0_FBL_OVRD 0x01C1 ++#define CMN_DIAG_PLL0_OVRD 0x01C2 ++#define CMN_DIAG_PLL0_TEST_MODE 0x01C4 ++#define CMN_DIAG_PLL0_V2I_TUNE 0x01C5 ++#define CMN_DIAG_PLL0_CP_TUNE 0x01C6 ++#define CMN_DIAG_PLL0_LF_PROG 0x01C7 ++#define CMN_DIAG_PLL0_PTATIS_TUNE1 0x01C8 ++#define CMN_DIAG_PLL0_PTATIS_TUNE2 0x01C9 ++#define CMN_DIAG_PLL0_INCLK_CTRL 0x01CA ++#define CMN_DIAG_PLL0_PXL_DIVH 0x01CB ++#define CMN_DIAG_PLL0_PXL_DIVL 0x01CC ++#define CMN_DIAG_HSCLK_SEL 0x01E0 ++#define CMN_DIAG_PER_CAL_ADJ 0x01EC ++#define CMN_DIAG_CAL_CTRL 0x01ED ++#define CMN_DIAG_ACYA 0x01FF ++#define XCVR_PSM_RCTRL 0x4001 ++#define XCVR_PSM_CAL_TMR 0x4002 ++#define XCVR_PSM_A0IN_TMR 0x4003 ++#define TX_TXCC_CAL_SCLR_MULT_0 0x4047 ++#define TX_TXCC_CPOST_MULT_00_0 0x404C ++#define TX_TXCC_MGNFS_MULT_000_0 0x4050 ++#define XCVR_DIAG_PLLDRC_CTRL 0x40E0 ++#define XCVR_DIAG_PLLDRC_CTRL 0x40E0 ++#define XCVR_DIAG_HSCLK_SEL 0x40E1 ++#define XCVR_DIAG_BIDI_CTRL 0x40E8 ++#define XCVR_DIAG_LANE_FCM_EN_MGN_TMR 0x40F2 ++#define XCVR_DIAG_LANE_FCM_EN_MGN 0x40F2 ++#define TX_PSC_A0 0x4100 ++#define TX_PSC_A1 0x4101 ++#define TX_PSC_A2 0x4102 ++#define TX_PSC_A3 0x4103 ++#define TX_RCVDET_CTRL 0x4120 ++#define TX_RCVDET_EN_TMR 0x4122 ++#define TX_RCVDET_EN_TMR 0x4122 ++#define TX_RCVDET_ST_TMR 0x4123 ++#define TX_RCVDET_ST_TMR 0x4123 ++#define TX_BIST_CTRL 0x4140 ++#define TX_BIST_UDDWR 0x4141 ++#define TX_DIAG_TX_CTRL 0x41E0 ++#define TX_DIAG_TX_DRV 0x41E1 ++#define TX_DIAG_BGREF_PREDRV_DELAY 0x41E7 ++#define TX_DIAG_BGREF_PREDRV_DELAY 0x41E7 ++#define XCVR_PSM_RCTRL_1 0x4201 ++#define TX_TXCC_CAL_SCLR_MULT_1 0x4247 ++#define TX_TXCC_CPOST_MULT_00_1 0x424C ++#define TX_TXCC_MGNFS_MULT_000_1 0x4250 ++#define XCVR_DIAG_PLLDRC_CTRL_1 0x42E0 ++#define XCVR_DIAG_HSCLK_SEL_1 0x42E1 ++#define XCVR_DIAG_LANE_FCM_EN_MGN_TMR_1 0x42F2 ++#define TX_RCVDET_EN_TMR_1 0x4322 ++#define TX_RCVDET_ST_TMR_1 0x4323 ++#define TX_DIAG_ACYA_0 0x41FF ++#define TX_DIAG_ACYA_1 0x43FF ++#define TX_DIAG_ACYA_2 0x45FF ++#define TX_DIAG_ACYA_3 0x47FF ++#define TX_ANA_CTRL_REG_1 0x5020 ++#define TX_ANA_CTRL_REG_2 0x5021 ++#define TXDA_COEFF_CALC 0x5022 ++#define TX_DIG_CTRL_REG_1 0x5023 ++#define TX_DIG_CTRL_REG_2 0x5024 ++#define TXDA_CYA_AUXDA_CYA 0x5025 ++#define TX_ANA_CTRL_REG_3 0x5026 ++#define TX_ANA_CTRL_REG_4 0x5027 ++#define TX_ANA_CTRL_REG_5 0x5029 ++#define RX_PSC_A0 0x8000 ++#define RX_PSC_CAL 0x8006 ++#define PMA_LANE_CFG 0xC000 ++#define PIPE_CMN_CTRL1 0xC001 ++#define PIPE_CMN_CTRL2 0xC002 ++#define PIPE_COM_LOCK_CFG1 0xC003 ++#define PIPE_COM_LOCK_CFG2 0xC004 ++#define PIPE_RCV_DET_INH 0xC005 ++#define PHY_HDP_MODE_CTRL 0xC008 ++#define PHY_HDP_CLK_CTL 0xC009 ++#define STS 0xC00F ++#define PHY_ISO_CMN_CTRL 0xC010 ++#define PHY_ISO_CMN_CTRL 0xC010 ++#define PHY_HDP_TX_CTL_L0 0xC408 ++#define PHY_DP_TX_CTL 0xC408 ++#define PHY_HDP_TX_CTL_L1 0xC448 ++#define PHY_HDP_TX_CTL_L2 0xC488 ++#define PHY_HDP_TX_CTL_L3 0xC4C8 ++#define PHY_PMA_CMN_CTRL1 0xC800 ++#define PMA_CMN_CTRL1 0xC800 ++#define PHY_PMA_ISO_CMN_CTRL 0xC810 ++#define PHY_PMA_ISO_PLL_CTRL1 0xC812 ++#define PHY_PMA_ISOLATION_CTRL 0xC81F ++#define PHY_ISOLATION_CTRL 0xC81F ++#define PHY_PMA_ISO_XCVR_CTRL 0xCC11 ++#define PHY_PMA_ISO_LINK_MODE 0xCC12 ++#define PHY_PMA_ISO_PWRST_CTRL 0xCC13 ++#define PHY_PMA_ISO_TX_DATA_LO 0xCC14 ++#define PHY_PMA_ISO_TX_DATA_HI 0xCC15 ++#define PHY_PMA_ISO_RX_DATA_LO 0xCC16 ++#define PHY_PMA_ISO_RX_DATA_HI 0xCC17 ++ ++int cdns_dp_phy_set_imx8mq(struct cdns_mhdp_device *hdp); ++int cdns_dp_phy_set_imx8qm(struct cdns_mhdp_device *hdp); ++bool cdns_hdmi_phy_video_valid_imx8mq(struct cdns_mhdp_device *hdp); ++bool cdns_hdmi_phy_video_valid_imx8qm(struct cdns_mhdp_device *hdp); ++int cdns_hdmi_phy_set_imx8mq(struct cdns_mhdp_device *hdp); ++int cdns_hdmi_phy_set_imx8qm(struct cdns_mhdp_device *hdp); ++#endif /* _CDNS_MHDP_PHY_H */ +diff --git a/drivers/gpu/drm/imx/cdns-mhdp-imx.h b/drivers/gpu/drm/imx/cdns-mhdp-imx.h +new file mode 100644 +index 000000000000..b95907ddc578 +--- /dev/null ++++ b/drivers/gpu/drm/imx/cdns-mhdp-imx.h +@@ -0,0 +1,75 @@ ++/* ++ * Cadence High-Definition Multimedia Interface (HDMI) driver ++ * ++ * Copyright (C) 2019 NXP Semiconductor, Inc. ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License as published by ++ * the Free Software Foundation; either version 2 of the License, or ++ * (at your option) any later version. ++ * ++ */ ++#ifndef CDNS_MHDP_IMX_H_ ++#define CDNS_MHDP_IMX_H_ ++ ++#include ++#include ++ ++ ++struct imx_mhdp_device; ++ ++struct imx_hdp_clks { ++ struct clk *av_pll; ++ struct clk *dig_pll; ++ struct clk *clk_ipg; ++ struct clk *clk_core; ++ struct clk *clk_pxl; ++ struct clk *clk_pxl_mux; ++ struct clk *clk_pxl_link; ++ ++ struct clk *lpcg_hdp; ++ struct clk *lpcg_msi; ++ struct clk *lpcg_pxl; ++ struct clk *lpcg_vif; ++ struct clk *lpcg_lis; ++ struct clk *lpcg_apb; ++ struct clk *lpcg_apb_csr; ++ struct clk *lpcg_apb_ctrl; ++ ++ struct clk *lpcg_i2s; ++ struct clk *clk_i2s_bypass; ++}; ++ ++struct imx_mhdp_device { ++ struct cdns_mhdp_device mhdp; ++ struct drm_encoder encoder; ++ ++ struct mutex audio_mutex; ++ spinlock_t audio_lock; ++ bool connected; ++ bool active; ++ bool suspended; ++ struct imx_hdp_clks clks; ++ const struct firmware *fw; ++ const char *firmware_name; ++ ++ int bus_type; ++ ++ struct device *pd_mhdp_dev; ++ struct device *pd_pll0_dev; ++ struct device *pd_pll1_dev; ++ struct device_link *pd_mhdp_link; ++ struct device_link *pd_pll0_link; ++ struct device_link *pd_pll1_link; ++}; ++ ++void cdns_mhdp_plat_init_imx8qm(struct cdns_mhdp_device *mhdp); ++void cdns_mhdp_plat_deinit_imx8qm(struct cdns_mhdp_device *mhdp); ++void cdns_mhdp_pclk_rate_imx8qm(struct cdns_mhdp_device *mhdp); ++int cdns_mhdp_firmware_init_imx8qm(struct cdns_mhdp_device *mhdp); ++int cdns_mhdp_resume_imx8qm(struct cdns_mhdp_device *mhdp); ++int cdns_mhdp_suspend_imx8qm(struct cdns_mhdp_device *mhdp); ++int cdns_mhdp_power_on_imx8qm(struct cdns_mhdp_device *mhdp); ++int cdns_mhdp_power_on_ls1028a(struct cdns_mhdp_device *mhdp); ++void cdns_mhdp_pclk_rate_ls1028a(struct cdns_mhdp_device *mhdp); ++#endif /* CDNS_MHDP_IMX_H_ */ +diff --git a/drivers/gpu/drm/imx/dcss/dcss-dev.c b/drivers/gpu/drm/imx/dcss/dcss-dev.c +index c849533ca83e..fe4600b8f833 100644 +--- a/drivers/gpu/drm/imx/dcss/dcss-dev.c ++++ b/drivers/gpu/drm/imx/dcss/dcss-dev.c +@@ -17,6 +17,11 @@ + + static void dcss_clocks_enable(struct dcss_dev *dcss) + { ++ if (dcss->hdmi_output) { ++ clk_prepare_enable(dcss->pll_phy_ref_clk); ++ clk_prepare_enable(dcss->pll_src_clk); ++ } ++ + clk_prepare_enable(dcss->axi_clk); + clk_prepare_enable(dcss->apb_clk); + clk_prepare_enable(dcss->rtrm_clk); +@@ -31,6 +36,11 @@ static void dcss_clocks_disable(struct dcss_dev *dcss) + clk_disable_unprepare(dcss->rtrm_clk); + clk_disable_unprepare(dcss->apb_clk); + clk_disable_unprepare(dcss->axi_clk); ++ ++ if (dcss->hdmi_output) { ++ clk_disable_unprepare(dcss->pll_src_clk); ++ clk_disable_unprepare(dcss->pll_phy_ref_clk); ++ } + } + + static void dcss_disable_dtg_and_ss_cb(void *data) +@@ -139,6 +149,8 @@ static int dcss_clks_init(struct dcss_dev *dcss) + {"pix", &dcss->pix_clk}, + {"rtrm", &dcss->rtrm_clk}, + {"dtrc", &dcss->dtrc_clk}, ++ {"pll_src", &dcss->pll_src_clk}, ++ {"pll_phy_ref", &dcss->pll_phy_ref_clk}, + }; + + for (i = 0; i < ARRAY_SIZE(clks); i++) { +@@ -160,6 +172,8 @@ static void dcss_clks_release(struct dcss_dev *dcss) + devm_clk_put(dcss->dev, dcss->pix_clk); + devm_clk_put(dcss->dev, dcss->axi_clk); + devm_clk_put(dcss->dev, dcss->apb_clk); ++ devm_clk_put(dcss->dev, dcss->pll_src_clk); ++ devm_clk_put(dcss->dev, dcss->pll_phy_ref_clk); + } + + struct dcss_dev *dcss_dev_create(struct device *dev, bool hdmi_output) +@@ -254,7 +268,8 @@ int dcss_dev_suspend(struct device *dev) + struct dcss_kms_dev *kms = container_of(ddev, struct dcss_kms_dev, base); + int ret; + +- drm_bridge_connector_disable_hpd(kms->connector); ++ if (!dcss_drv_is_componentized(dev)) ++ drm_bridge_connector_disable_hpd(kms->connector); + + drm_mode_config_helper_suspend(ddev); + +@@ -289,7 +304,8 @@ int dcss_dev_resume(struct device *dev) + + drm_mode_config_helper_resume(ddev); + +- drm_bridge_connector_enable_hpd(kms->connector); ++ if (!dcss_drv_is_componentized(dev)) ++ drm_bridge_connector_enable_hpd(kms->connector); + + return 0; + } +diff --git a/drivers/gpu/drm/imx/dcss/dcss-dev.h b/drivers/gpu/drm/imx/dcss/dcss-dev.h +index 1e582270c6ea..083edf6d715f 100644 +--- a/drivers/gpu/drm/imx/dcss/dcss-dev.h ++++ b/drivers/gpu/drm/imx/dcss/dcss-dev.h +@@ -93,6 +93,7 @@ struct dcss_dev { + + struct dcss_dev *dcss_drv_dev_to_dcss(struct device *dev); + struct drm_device *dcss_drv_dev_to_drm(struct device *dev); ++bool dcss_drv_is_componentized(struct device *dev); + struct dcss_dev *dcss_dev_create(struct device *dev, bool hdmi_output); + void dcss_dev_destroy(struct dcss_dev *dcss); + int dcss_dev_runtime_suspend(struct device *dev); +diff --git a/drivers/gpu/drm/imx/dcss/dcss-drv.c b/drivers/gpu/drm/imx/dcss/dcss-drv.c +index 8dc2f85c514b..3e542c091d3d 100644 +--- a/drivers/gpu/drm/imx/dcss/dcss-drv.c ++++ b/drivers/gpu/drm/imx/dcss/dcss-drv.c +@@ -6,6 +6,7 @@ + #include + #include + #include ++#include + #include + + #include "dcss-dev.h" +@@ -14,6 +15,8 @@ + struct dcss_drv { + struct dcss_dev *dcss; + struct dcss_kms_dev *kms; ++ ++ bool is_componentized; + }; + + struct dcss_dev *dcss_drv_dev_to_dcss(struct device *dev) +@@ -30,30 +33,24 @@ struct drm_device *dcss_drv_dev_to_drm(struct device *dev) + return mdrv ? &mdrv->kms->base : NULL; + } + +-static int dcss_drv_platform_probe(struct platform_device *pdev) ++bool dcss_drv_is_componentized(struct device *dev) ++{ ++ struct dcss_drv *mdrv = dev_get_drvdata(dev); ++ return mdrv->is_componentized; ++} ++ ++static int dcss_drv_init(struct device *dev, bool componentized) + { +- struct device *dev = &pdev->dev; +- struct device_node *remote; + struct dcss_drv *mdrv; + int err = 0; +- bool hdmi_output = true; +- +- if (!dev->of_node) +- return -ENODEV; +- +- remote = of_graph_get_remote_node(dev->of_node, 0, 0); +- if (!remote) +- return -ENODEV; +- +- hdmi_output = !of_device_is_compatible(remote, "fsl,imx8mq-nwl-dsi"); +- +- of_node_put(remote); + + mdrv = kzalloc(sizeof(*mdrv), GFP_KERNEL); + if (!mdrv) + return -ENOMEM; + +- mdrv->dcss = dcss_dev_create(dev, hdmi_output); ++ mdrv->is_componentized = componentized; ++ ++ mdrv->dcss = dcss_dev_create(dev, componentized); + if (IS_ERR(mdrv->dcss)) { + err = PTR_ERR(mdrv->dcss); + goto err; +@@ -61,7 +58,7 @@ static int dcss_drv_platform_probe(struct platform_device *pdev) + + dev_set_drvdata(dev, mdrv); + +- mdrv->kms = dcss_kms_attach(mdrv->dcss); ++ mdrv->kms = dcss_kms_attach(mdrv->dcss, componentized); + if (IS_ERR(mdrv->kms)) { + err = PTR_ERR(mdrv->kms); + goto dcss_shutoff; +@@ -79,19 +76,73 @@ static int dcss_drv_platform_probe(struct platform_device *pdev) + return err; + } + +-static int dcss_drv_platform_remove(struct platform_device *pdev) ++static void dcss_drv_deinit(struct device *dev, bool componentized) + { +- struct dcss_drv *mdrv = dev_get_drvdata(&pdev->dev); ++ struct dcss_drv *mdrv = dev_get_drvdata(dev); + + if (!mdrv) +- return 0; ++ return; + +- dcss_kms_detach(mdrv->kms); ++ dcss_kms_detach(mdrv->kms, componentized); + dcss_dev_destroy(mdrv->dcss); + +- dev_set_drvdata(&pdev->dev, NULL); ++ dev_set_drvdata(dev, NULL); + + kfree(mdrv); ++} ++ ++static int dcss_drv_bind(struct device *dev) ++{ ++ return dcss_drv_init(dev, true); ++} ++ ++static void dcss_drv_unbind(struct device *dev) ++{ ++ return dcss_drv_deinit(dev, true); ++} ++ ++static const struct component_master_ops dcss_master_ops = { ++ .bind = dcss_drv_bind, ++ .unbind = dcss_drv_unbind, ++}; ++ ++static int compare_of(struct device *dev, void *data) ++{ ++ return dev->of_node == data; ++} ++ ++static int dcss_drv_platform_probe(struct platform_device *pdev) ++{ ++ struct device *dev = &pdev->dev; ++ struct component_match *match = NULL; ++ struct device_node *remote; ++ ++ if (!dev->of_node) ++ return -ENODEV; ++ ++ remote = of_graph_get_remote_node(dev->of_node, 0, 0); ++ if (!remote) ++ return -ENODEV; ++ ++ if (of_device_is_compatible(remote, "fsl,imx8mq-nwl-dsi")) { ++ of_node_put(remote); ++ return dcss_drv_init(dev, false); ++ } ++ ++ drm_of_component_match_add(dev, &match, compare_of, remote); ++ of_node_put(remote); ++ ++ return component_master_add_with_match(dev, &dcss_master_ops, match); ++} ++ ++static int dcss_drv_platform_remove(struct platform_device *pdev) ++{ ++ struct dcss_drv *mdrv = dev_get_drvdata(&pdev->dev); ++ ++ if (mdrv->is_componentized) ++ component_master_del(&pdev->dev, &dcss_master_ops); ++ else ++ dcss_drv_deinit(&pdev->dev, false); + + return 0; + } +diff --git a/drivers/gpu/drm/imx/dcss/dcss-dtg.c b/drivers/gpu/drm/imx/dcss/dcss-dtg.c +index 30de00540f63..c7a688b2a3b6 100644 +--- a/drivers/gpu/drm/imx/dcss/dcss-dtg.c ++++ b/drivers/gpu/drm/imx/dcss/dcss-dtg.c +@@ -83,6 +83,7 @@ struct dcss_dtg { + u32 ctx_id; + + bool in_use; ++ bool hdmi_output; + + u32 dis_ulc_x; + u32 dis_ulc_y; +@@ -93,6 +94,9 @@ struct dcss_dtg { + + int ctxld_kick_irq; + bool ctxld_kick_irq_en; ++ ++ struct clk *pll_src_clk; ++ struct clk *pll_phy_ref_clk; + }; + + static void dcss_dtg_write(struct dcss_dtg *dtg, u32 val, u32 ofs) +@@ -159,6 +163,7 @@ int dcss_dtg_init(struct dcss_dev *dcss, unsigned long dtg_base) + dcss->dtg = dtg; + dtg->dev = dcss->dev; + dtg->ctxld = dcss->ctxld; ++ dtg->hdmi_output = dcss->hdmi_output; + + dtg->base_reg = ioremap(dtg_base, SZ_4K); + if (!dtg->base_reg) { +@@ -170,6 +175,9 @@ int dcss_dtg_init(struct dcss_dev *dcss, unsigned long dtg_base) + dtg->base_ofs = dtg_base; + dtg->ctx_id = CTX_DB; + ++ dtg->pll_src_clk = dcss->pll_src_clk; ++ dtg->pll_phy_ref_clk = dcss->pll_phy_ref_clk; ++ + dtg->alpha = 255; + + dtg->control_status |= OVL_DATA_MODE | BLENDER_VIDEO_ALPHA_SEL | +@@ -220,8 +228,22 @@ void dcss_dtg_sync_set(struct dcss_dtg *dtg, struct videomode *vm) + dis_lrc_y = vm->vsync_len + vm->vfront_porch + vm->vback_porch + + vm->vactive - 1; + ++ if (dtg->hdmi_output) { ++ int err; ++ ++ clk_disable_unprepare(dtg->pll_src_clk); ++ err = clk_set_parent(dtg->pll_src_clk, dtg->pll_phy_ref_clk); ++ if (err < 0) ++ dev_warn(dtg->dev, "clk_set_parent() returned %d", err); ++ clk_prepare_enable(dtg->pll_src_clk); ++ } ++ + clk_disable_unprepare(dcss->pix_clk); +- clk_set_rate(dcss->pix_clk, vm->pixelclock); ++ if (dtg->hdmi_output) { ++ clk_set_rate(dcss->pix_clk, vm->pixelclock); ++ } else { ++ clk_set_rate(dcss->pix_clk, (vm->pixelclock * 700)/1000); ++ } + clk_prepare_enable(dcss->pix_clk); + + actual_clk = clk_get_rate(dcss->pix_clk); +@@ -406,4 +428,3 @@ bool dcss_dtg_vblank_irq_valid(struct dcss_dtg *dtg) + { + return !!(dcss_readl(dtg->base_reg + DCSS_DTG_INT_STATUS) & LINE1_IRQ); + } +- +diff --git a/drivers/gpu/drm/imx/dcss/dcss-kms.c b/drivers/gpu/drm/imx/dcss/dcss-kms.c +index b549ce5e7607..da66c3151e85 100644 +--- a/drivers/gpu/drm/imx/dcss/dcss-kms.c ++++ b/drivers/gpu/drm/imx/dcss/dcss-kms.c +@@ -13,6 +13,7 @@ + #include + #include + #include ++#include + + #include "dcss-dev.h" + #include "dcss-kms.h" +@@ -70,6 +71,7 @@ static int dcss_kms_bridge_connector_init(struct dcss_kms_dev *kms) + struct drm_crtc *crtc = (struct drm_crtc *)&kms->crtc; + struct drm_panel *panel; + struct drm_bridge *bridge; ++ struct drm_connector_list_iter iter; + int ret; + + ret = drm_of_find_panel_or_bridge(ddev->dev->of_node, 0, 0, +@@ -92,26 +94,26 @@ static int dcss_kms_bridge_connector_init(struct dcss_kms_dev *kms) + return ret; + } + +- ret = drm_bridge_attach(encoder, bridge, NULL, +- DRM_BRIDGE_ATTACH_NO_CONNECTOR); ++ ret = drm_bridge_attach(encoder, bridge, NULL, 0); + if (ret < 0) { + dev_err(ddev->dev, "Unable to attach bridge %pOF\n", + bridge->of_node); + return ret; + } + +- kms->connector = drm_bridge_connector_init(ddev, encoder); +- if (IS_ERR(kms->connector)) { +- dev_err(ddev->dev, "Unable to create bridge connector.\n"); +- return PTR_ERR(kms->connector); +- } ++ /* ++ * FIXME: This hack to look up the connector is copied from mxsfb. ++ */ ++ drm_connector_list_iter_begin(ddev, &iter); ++ kms->connector = drm_connector_list_iter_next(&iter); ++ drm_connector_list_iter_end(&iter); + + drm_connector_attach_encoder(kms->connector, encoder); + + return 0; + } + +-struct dcss_kms_dev *dcss_kms_attach(struct dcss_dev *dcss) ++struct dcss_kms_dev *dcss_kms_attach(struct dcss_dev *dcss, bool componentized) + { + struct dcss_kms_dev *kms; + struct drm_device *drm; +@@ -136,19 +138,28 @@ struct dcss_kms_dev *dcss_kms_attach(struct dcss_dev *dcss) + + drm->irq_enabled = true; + +- ret = dcss_kms_bridge_connector_init(kms); +- if (ret) +- goto cleanup_mode_config; ++ if (!componentized) { ++ ret = dcss_kms_bridge_connector_init(kms); ++ if (ret) ++ goto cleanup_mode_config; ++ } + + ret = dcss_crtc_init(crtc, drm); + if (ret) + goto cleanup_mode_config; + ++ if (componentized) { ++ ret = component_bind_all(dcss->dev, kms); ++ if (ret) ++ goto cleanup_crtc; ++ } ++ + drm_mode_config_reset(drm); + + drm_kms_helper_poll_init(drm); + +- drm_bridge_connector_enable_hpd(kms->connector); ++ if (!componentized) ++ drm_bridge_connector_enable_hpd(kms->connector); + + ret = drm_dev_register(drm, 0); + if (ret) +@@ -159,7 +170,8 @@ struct dcss_kms_dev *dcss_kms_attach(struct dcss_dev *dcss) + return kms; + + cleanup_crtc: +- drm_bridge_connector_disable_hpd(kms->connector); ++ if (!componentized) ++ drm_bridge_connector_disable_hpd(kms->connector); + drm_kms_helper_poll_fini(drm); + dcss_crtc_deinit(crtc, drm); + +@@ -170,17 +182,21 @@ struct dcss_kms_dev *dcss_kms_attach(struct dcss_dev *dcss) + return ERR_PTR(ret); + } + +-void dcss_kms_detach(struct dcss_kms_dev *kms) ++void dcss_kms_detach(struct dcss_kms_dev *kms, bool componentized) + { + struct drm_device *drm = &kms->base; ++ struct dcss_dev *dcss = drm->dev_private; + + drm_dev_unregister(drm); +- drm_bridge_connector_disable_hpd(kms->connector); ++ if (!componentized) ++ drm_bridge_connector_disable_hpd(kms->connector); + drm_kms_helper_poll_fini(drm); + drm_atomic_helper_shutdown(drm); + drm_crtc_vblank_off(&kms->crtc.base); + drm->irq_enabled = false; + drm_mode_config_cleanup(drm); + dcss_crtc_deinit(&kms->crtc, drm); ++ if (componentized) ++ component_unbind_all(dcss->dev, drm); + drm->dev_private = NULL; + } +diff --git a/drivers/gpu/drm/imx/dcss/dcss-kms.h b/drivers/gpu/drm/imx/dcss/dcss-kms.h +index dfe5dd99eea3..c3e0d0684785 100644 +--- a/drivers/gpu/drm/imx/dcss/dcss-kms.h ++++ b/drivers/gpu/drm/imx/dcss/dcss-kms.h +@@ -32,8 +32,8 @@ struct dcss_kms_dev { + struct drm_connector *connector; + }; + +-struct dcss_kms_dev *dcss_kms_attach(struct dcss_dev *dcss); +-void dcss_kms_detach(struct dcss_kms_dev *kms); ++struct dcss_kms_dev *dcss_kms_attach(struct dcss_dev *dcss, bool componetized); ++void dcss_kms_detach(struct dcss_kms_dev *kms, bool componetized); + int dcss_crtc_init(struct dcss_crtc *crtc, struct drm_device *drm); + void dcss_crtc_deinit(struct dcss_crtc *crtc, struct drm_device *drm); + struct dcss_plane *dcss_plane_init(struct drm_device *drm, +diff --git a/include/drm/bridge/cdns-mhdp-cbs.h b/include/drm/bridge/cdns-mhdp-cbs.h +new file mode 100644 +index 000000000000..ed67e184d3ed +--- /dev/null ++++ b/include/drm/bridge/cdns-mhdp-cbs.h +@@ -0,0 +1,29 @@ ++/* SPDX-License-Identifier: GPL-2.0 */ ++/* ++ * Cadence MHDP DP bridge callbacks. ++ * ++ * Copyright: 2018 Cadence Design Systems, Inc. ++ * ++ * Author: Piotr Sroka ++ */ ++ ++#ifndef CDNS_MHDP_CBS_H ++#define CDNS_MHDP_CBS_H ++ ++#include ++ ++struct cdns_mhdp_mst_cbs_funcs { ++ struct drm_encoder *(*create_mst_encoder)(void *priv_data, ++ struct drm_bridge *bridge); ++ void (*destroy_mst_encoder)(void *priv_data, struct drm_bridge *bridge); ++}; ++ ++struct cdns_mhdp_mst_cbs { ++ struct cdns_mhdp_mst_cbs_funcs funcs; ++ void *priv_data; ++}; ++ ++int mhdp_bridge_attach_mst_cbs(struct drm_bridge *bridge, ++ struct cdns_mhdp_mst_cbs *cbs); ++ ++#endif +diff --git a/include/drm/bridge/cdns-mhdp-common.h b/include/drm/bridge/cdns-mhdp-common.h +new file mode 100755 +index 000000000000..752bf493f026 +--- /dev/null ++++ b/include/drm/bridge/cdns-mhdp-common.h +@@ -0,0 +1,812 @@ ++/* SPDX-License-Identifier: GPL-2.0 */ ++/* ++ * Copyright (C) Fuzhou Rockchip Electronics Co.Ltd ++ * Author: Chris Zhong ++ * ++ * This software is licensed under the terms of the GNU General Public ++ * License version 2, as published by the Free Software Foundation, and ++ * may be copied, distributed, and modified under those terms. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ */ ++ ++#ifndef CDNS_MHDP_COMMON_H_ ++#define CDNS_MHDP_COMMON_H_ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#define ADDR_IMEM 0x10000 ++#define ADDR_DMEM 0x20000 ++#define ADDR_PHY_AFE 0x80000 ++ ++/* APB CFG addr */ ++#define APB_CTRL 0 ++#define XT_INT_CTRL 0x04 ++#define MAILBOX_FULL_ADDR 0x08 ++#define MAILBOX_EMPTY_ADDR 0x0c ++#define MAILBOX0_WR_DATA 0x10 ++#define MAILBOX0_RD_DATA 0x14 ++#define KEEP_ALIVE 0x18 ++#define VER_L 0x1c ++#define VER_H 0x20 ++#define VER_LIB_L_ADDR 0x24 ++#define VER_LIB_H_ADDR 0x28 ++#define SW_DEBUG_L 0x2c ++#define SW_DEBUG_H 0x30 ++#define MAILBOX_INT_MASK 0x34 ++#define MAILBOX_INT_STATUS 0x38 ++#define SW_CLK_L 0x3c ++#define SW_CLK_H 0x40 ++#define SW_EVENTS0 0x44 ++#define SW_EVENTS1 0x48 ++#define SW_EVENTS2 0x4c ++#define SW_EVENTS3 0x50 ++#define XT_OCD_CTRL 0x60 ++#define APB_INT_MASK 0x6c ++#define APB_STATUS_MASK 0x70 ++ ++/* audio decoder addr */ ++#define AUDIO_SRC_CNTL 0x30000 ++#define AUDIO_SRC_CNFG 0x30004 ++#define COM_CH_STTS_BITS 0x30008 ++#define STTS_BIT_CH(x) (0x3000c + ((x) << 2)) ++#define SPDIF_CTRL_ADDR 0x3004c ++#define SPDIF_CH1_CS_3100_ADDR 0x30050 ++#define SPDIF_CH1_CS_6332_ADDR 0x30054 ++#define SPDIF_CH1_CS_9564_ADDR 0x30058 ++#define SPDIF_CH1_CS_12796_ADDR 0x3005c ++#define SPDIF_CH1_CS_159128_ADDR 0x30060 ++#define SPDIF_CH1_CS_191160_ADDR 0x30064 ++#define SPDIF_CH2_CS_3100_ADDR 0x30068 ++#define SPDIF_CH2_CS_6332_ADDR 0x3006c ++#define SPDIF_CH2_CS_9564_ADDR 0x30070 ++#define SPDIF_CH2_CS_12796_ADDR 0x30074 ++#define SPDIF_CH2_CS_159128_ADDR 0x30078 ++#define SPDIF_CH2_CS_191160_ADDR 0x3007c ++#define SMPL2PKT_CNTL 0x30080 ++#define SMPL2PKT_CNFG 0x30084 ++#define FIFO_CNTL 0x30088 ++#define FIFO_STTS 0x3008c ++ ++/* source pif addr */ ++#define SOURCE_PIF_WR_ADDR 0x30800 ++#define SOURCE_PIF_WR_REQ 0x30804 ++#define SOURCE_PIF_RD_ADDR 0x30808 ++#define SOURCE_PIF_RD_REQ 0x3080c ++#define SOURCE_PIF_DATA_WR 0x30810 ++#define SOURCE_PIF_DATA_RD 0x30814 ++#define SOURCE_PIF_FIFO1_FLUSH 0x30818 ++#define SOURCE_PIF_FIFO2_FLUSH 0x3081c ++#define SOURCE_PIF_STATUS 0x30820 ++#define SOURCE_PIF_INTERRUPT_SOURCE 0x30824 ++#define SOURCE_PIF_INTERRUPT_MASK 0x30828 ++#define SOURCE_PIF_PKT_ALLOC_REG 0x3082c ++#define SOURCE_PIF_PKT_ALLOC_WR_EN 0x30830 ++#define SOURCE_PIF_SW_RESET 0x30834 ++ ++/* bellow registers need access by mailbox */ ++/* source phy comp */ ++#define PHY_DATA_SEL 0x0818 ++#define LANES_CONFIG 0x0814 ++ ++/* source car addr */ ++#define SOURCE_HDTX_CAR 0x0900 ++#define SOURCE_DPTX_CAR 0x0904 ++#define SOURCE_PHY_CAR 0x0908 ++#define SOURCE_CEC_CAR 0x090c ++#define SOURCE_CBUS_CAR 0x0910 ++#define SOURCE_PKT_CAR 0x0918 ++#define SOURCE_AIF_CAR 0x091c ++#define SOURCE_CIPHER_CAR 0x0920 ++#define SOURCE_CRYPTO_CAR 0x0924 ++ ++/* mhdp tx_top_comp */ ++#define SCHEDULER_H_SIZE 0x1000 ++#define SCHEDULER_V_SIZE 0x1004 ++#define HDTX_SIGNAL_FRONT_WIDTH 0x100c ++#define HDTX_SIGNAL_SYNC_WIDTH 0x1010 ++#define HDTX_SIGNAL_BACK_WIDTH 0x1014 ++#define HDTX_CONTROLLER 0x1018 ++#define HDTX_HPD 0x1020 ++#define HDTX_CLOCK_REG_0 0x1024 ++#define HDTX_CLOCK_REG_1 0x1028 ++ ++/* clock meters addr */ ++#define CM_CTRL 0x0a00 ++#define CM_I2S_CTRL 0x0a04 ++#define CM_SPDIF_CTRL 0x0a08 ++#define CM_VID_CTRL 0x0a0c ++#define CM_LANE_CTRL 0x0a10 ++#define I2S_NM_STABLE 0x0a14 ++#define I2S_NCTS_STABLE 0x0a18 ++#define SPDIF_NM_STABLE 0x0a1c ++#define SPDIF_NCTS_STABLE 0x0a20 ++#define NMVID_MEAS_STABLE 0x0a24 ++#define I2S_MEAS 0x0a40 ++#define SPDIF_MEAS 0x0a80 ++#define NMVID_MEAS 0x0ac0 ++ ++/* source vif addr */ ++#define BND_HSYNC2VSYNC 0x0b00 ++#define HSYNC2VSYNC_F1_L1 0x0b04 ++#define HSYNC2VSYNC_F2_L1 0x0b08 ++#define HSYNC2VSYNC_STATUS 0x0b0c ++#define HSYNC2VSYNC_POL_CTRL 0x0b10 ++ ++/* dptx phy addr */ ++#define DP_TX_PHY_CONFIG_REG 0x2000 ++#define DP_TX_PHY_SW_RESET 0x2004 ++#define DP_TX_PHY_SCRAMBLER_SEED 0x2008 ++#define DP_TX_PHY_TRAINING_01_04 0x200c ++#define DP_TX_PHY_TRAINING_05_08 0x2010 ++#define DP_TX_PHY_TRAINING_09_10 0x2014 ++#define TEST_COR 0x23fc ++ ++/* dptx hpd addr */ ++#define HPD_IRQ_DET_MIN_TIMER 0x2100 ++#define HPD_IRQ_DET_MAX_TIMER 0x2104 ++#define HPD_UNPLGED_DET_MIN_TIMER 0x2108 ++#define HPD_STABLE_TIMER 0x210c ++#define HPD_FILTER_TIMER 0x2110 ++#define HPD_EVENT_MASK 0x211c ++#define HPD_EVENT_DET 0x2120 ++ ++/* dpyx framer addr */ ++#define DP_FRAMER_GLOBAL_CONFIG 0x2200 ++#define DP_SW_RESET 0x2204 ++#define DP_FRAMER_TU 0x2208 ++#define DP_FRAMER_PXL_REPR 0x220c ++#define DP_FRAMER_SP 0x2210 ++#define AUDIO_PACK_CONTROL 0x2214 ++#define DP_VC_TABLE(x) (0x2218 + ((x) << 2)) ++#define DP_VB_ID 0x2258 ++#define DP_MTPH_LVP_CONTROL 0x225c ++#define DP_MTPH_SYMBOL_VALUES 0x2260 ++#define DP_MTPH_ECF_CONTROL 0x2264 ++#define DP_MTPH_ACT_CONTROL 0x2268 ++#define DP_MTPH_STATUS 0x226c ++#define DP_INTERRUPT_SOURCE 0x2270 ++#define DP_INTERRUPT_MASK 0x2274 ++#define DP_FRONT_BACK_PORCH 0x2278 ++#define DP_BYTE_COUNT 0x227c ++ ++/* dptx stream addr */ ++#define MSA_HORIZONTAL_0 0x2280 ++#define MSA_HORIZONTAL_1 0x2284 ++#define MSA_VERTICAL_0 0x2288 ++#define MSA_VERTICAL_1 0x228c ++#define MSA_MISC 0x2290 ++#define STREAM_CONFIG 0x2294 ++#define AUDIO_PACK_STATUS 0x2298 ++#define VIF_STATUS 0x229c ++#define PCK_STUFF_STATUS_0 0x22a0 ++#define PCK_STUFF_STATUS_1 0x22a4 ++#define INFO_PACK_STATUS 0x22a8 ++#define RATE_GOVERNOR_STATUS 0x22ac ++#define DP_HORIZONTAL 0x22b0 ++#define DP_VERTICAL_0 0x22b4 ++#define DP_VERTICAL_1 0x22b8 ++#define DP_BLOCK_SDP 0x22bc ++ ++/* dptx glbl addr */ ++#define DPTX_LANE_EN 0x2300 ++#define DPTX_ENHNCD 0x2304 ++#define DPTX_INT_MASK 0x2308 ++#define DPTX_INT_STATUS 0x230c ++ ++/* dp aux addr */ ++#define DP_AUX_HOST_CONTROL 0x2800 ++#define DP_AUX_INTERRUPT_SOURCE 0x2804 ++#define DP_AUX_INTERRUPT_MASK 0x2808 ++#define DP_AUX_SWAP_INVERSION_CONTROL 0x280c ++#define DP_AUX_SEND_NACK_TRANSACTION 0x2810 ++#define DP_AUX_CLEAR_RX 0x2814 ++#define DP_AUX_CLEAR_TX 0x2818 ++#define DP_AUX_TIMER_STOP 0x281c ++#define DP_AUX_TIMER_CLEAR 0x2820 ++#define DP_AUX_RESET_SW 0x2824 ++#define DP_AUX_DIVIDE_2M 0x2828 ++#define DP_AUX_TX_PREACHARGE_LENGTH 0x282c ++#define DP_AUX_FREQUENCY_1M_MAX 0x2830 ++#define DP_AUX_FREQUENCY_1M_MIN 0x2834 ++#define DP_AUX_RX_PRE_MIN 0x2838 ++#define DP_AUX_RX_PRE_MAX 0x283c ++#define DP_AUX_TIMER_PRESET 0x2840 ++#define DP_AUX_NACK_FORMAT 0x2844 ++#define DP_AUX_TX_DATA 0x2848 ++#define DP_AUX_RX_DATA 0x284c ++#define DP_AUX_TX_STATUS 0x2850 ++#define DP_AUX_RX_STATUS 0x2854 ++#define DP_AUX_RX_CYCLE_COUNTER 0x2858 ++#define DP_AUX_MAIN_STATES 0x285c ++#define DP_AUX_MAIN_TIMER 0x2860 ++#define DP_AUX_AFE_OUT 0x2864 ++ ++/* crypto addr */ ++#define CRYPTO_HDCP_REVISION 0x5800 ++#define HDCP_CRYPTO_CONFIG 0x5804 ++#define CRYPTO_INTERRUPT_SOURCE 0x5808 ++#define CRYPTO_INTERRUPT_MASK 0x580c ++#define CRYPTO22_CONFIG 0x5818 ++#define CRYPTO22_STATUS 0x581c ++#define SHA_256_DATA_IN 0x583c ++#define SHA_256_DATA_OUT_(x) (0x5850 + ((x) << 2)) ++#define AES_32_KEY_(x) (0x5870 + ((x) << 2)) ++#define AES_32_DATA_IN 0x5880 ++#define AES_32_DATA_OUT_(x) (0x5884 + ((x) << 2)) ++#define CRYPTO14_CONFIG 0x58a0 ++#define CRYPTO14_STATUS 0x58a4 ++#define CRYPTO14_PRNM_OUT 0x58a8 ++#define CRYPTO14_KM_0 0x58ac ++#define CRYPTO14_KM_1 0x58b0 ++#define CRYPTO14_AN_0 0x58b4 ++#define CRYPTO14_AN_1 0x58b8 ++#define CRYPTO14_YOUR_KSV_0 0x58bc ++#define CRYPTO14_YOUR_KSV_1 0x58c0 ++#define CRYPTO14_MI_0 0x58c4 ++#define CRYPTO14_MI_1 0x58c8 ++#define CRYPTO14_TI_0 0x58cc ++#define CRYPTO14_KI_0 0x58d0 ++#define CRYPTO14_KI_1 0x58d4 ++#define CRYPTO14_BLOCKS_NUM 0x58d8 ++#define CRYPTO14_KEY_MEM_DATA_0 0x58dc ++#define CRYPTO14_KEY_MEM_DATA_1 0x58e0 ++#define CRYPTO14_SHA1_MSG_DATA 0x58e4 ++#define CRYPTO14_SHA1_V_VALUE_(x) (0x58e8 + ((x) << 2)) ++#define TRNG_CTRL 0x58fc ++#define TRNG_DATA_RDY 0x5900 ++#define TRNG_DATA 0x5904 ++ ++/* cipher addr */ ++#define HDCP_REVISION 0x60000 ++#define INTERRUPT_SOURCE 0x60004 ++#define INTERRUPT_MASK 0x60008 ++#define HDCP_CIPHER_CONFIG 0x6000c ++#define AES_128_KEY_0 0x60010 ++#define AES_128_KEY_1 0x60014 ++#define AES_128_KEY_2 0x60018 ++#define AES_128_KEY_3 0x6001c ++#define AES_128_RANDOM_0 0x60020 ++#define AES_128_RANDOM_1 0x60024 ++#define CIPHER14_KM_0 0x60028 ++#define CIPHER14_KM_1 0x6002c ++#define CIPHER14_STATUS 0x60030 ++#define CIPHER14_RI_PJ_STATUS 0x60034 ++#define CIPHER_MODE 0x60038 ++#define CIPHER14_AN_0 0x6003c ++#define CIPHER14_AN_1 0x60040 ++#define CIPHER22_AUTH 0x60044 ++#define CIPHER14_R0_DP_STATUS 0x60048 ++#define CIPHER14_BOOTSTRAP 0x6004c ++ ++#define DPTX_FRMR_DATA_CLK_RSTN_EN BIT(11) ++#define DPTX_FRMR_DATA_CLK_EN BIT(10) ++#define DPTX_PHY_DATA_RSTN_EN BIT(9) ++#define DPTX_PHY_DATA_CLK_EN BIT(8) ++#define DPTX_PHY_CHAR_RSTN_EN BIT(7) ++#define DPTX_PHY_CHAR_CLK_EN BIT(6) ++#define SOURCE_AUX_SYS_CLK_RSTN_EN BIT(5) ++#define SOURCE_AUX_SYS_CLK_EN BIT(4) ++#define DPTX_SYS_CLK_RSTN_EN BIT(3) ++#define DPTX_SYS_CLK_EN BIT(2) ++#define CFG_DPTX_VIF_CLK_RSTN_EN BIT(1) ++#define CFG_DPTX_VIF_CLK_EN BIT(0) ++ ++#define SOURCE_PHY_RSTN_EN BIT(1) ++#define SOURCE_PHY_CLK_EN BIT(0) ++ ++#define SOURCE_PKT_SYS_RSTN_EN BIT(3) ++#define SOURCE_PKT_SYS_CLK_EN BIT(2) ++#define SOURCE_PKT_DATA_RSTN_EN BIT(1) ++#define SOURCE_PKT_DATA_CLK_EN BIT(0) ++ ++#define SPDIF_CDR_CLK_RSTN_EN BIT(5) ++#define SPDIF_CDR_CLK_EN BIT(4) ++#define SOURCE_AIF_SYS_RSTN_EN BIT(3) ++#define SOURCE_AIF_SYS_CLK_EN BIT(2) ++#define SOURCE_AIF_CLK_RSTN_EN BIT(1) ++#define SOURCE_AIF_CLK_EN BIT(0) ++ ++#define SOURCE_CIPHER_SYSTEM_CLK_RSTN_EN BIT(3) ++#define SOURCE_CIPHER_SYS_CLK_EN BIT(2) ++#define SOURCE_CIPHER_CHAR_CLK_RSTN_EN BIT(1) ++#define SOURCE_CIPHER_CHAR_CLK_EN BIT(0) ++ ++#define SOURCE_CRYPTO_SYS_CLK_RSTN_EN BIT(1) ++#define SOURCE_CRYPTO_SYS_CLK_EN BIT(0) ++ ++#define APB_IRAM_PATH BIT(2) ++#define APB_DRAM_PATH BIT(1) ++#define APB_XT_RESET BIT(0) ++ ++#define MAILBOX_INT_MASK_BIT BIT(1) ++#define PIF_INT_MASK_BIT BIT(0) ++#define ALL_INT_MASK 3 ++ ++/* mailbox */ ++#define MB_OPCODE_ID 0 ++#define MB_MODULE_ID 1 ++#define MB_SIZE_MSB_ID 2 ++#define MB_SIZE_LSB_ID 3 ++#define MB_DATA_ID 4 ++ ++#define MB_MODULE_ID_DP_TX 0x01 ++#define MB_MODULE_ID_HDMI_TX 0x03 ++#define MB_MODULE_ID_HDCP_TX 0x07 ++#define MB_MODULE_ID_HDCP_RX 0x08 ++#define MB_MODULE_ID_HDCP_GENERAL 0x09 ++#define MB_MODULE_ID_GENERAL 0x0A ++ ++/* general opcode */ ++#define GENERAL_MAIN_CONTROL 0x01 ++#define GENERAL_TEST_ECHO 0x02 ++#define GENERAL_BUS_SETTINGS 0x03 ++#define GENERAL_TEST_ACCESS 0x04 ++#define GENERAL_WRITE_REGISTER 0x05 ++#define GENERAL_WRITE_FIELD 0x06 ++#define GENERAL_READ_REGISTER 0x07 ++#define GENERAL_GET_HPD_STATE 0x11 ++ ++/* DPTX opcode */ ++#define DPTX_SET_POWER_MNG 0x00 ++#define DPTX_SET_HOST_CAPABILITIES 0x01 ++#define DPTX_GET_EDID 0x02 ++#define DPTX_READ_DPCD 0x03 ++#define DPTX_WRITE_DPCD 0x04 ++#define DPTX_ENABLE_EVENT 0x05 ++#define DPTX_WRITE_REGISTER 0x06 ++#define DPTX_READ_REGISTER 0x07 ++#define DPTX_WRITE_FIELD 0x08 ++#define DPTX_TRAINING_CONTROL 0x09 ++#define DPTX_READ_EVENT 0x0a ++#define DPTX_READ_LINK_STAT 0x0b ++#define DPTX_SET_VIDEO 0x0c ++#define DPTX_SET_AUDIO 0x0d ++#define DPTX_GET_LAST_AUX_STAUS 0x0e ++#define DPTX_SET_LINK_BREAK_POINT 0x0f ++#define DPTX_FORCE_LANES 0x10 ++#define DPTX_HPD_STATE 0x11 ++#define DPTX_ADJUST_LT 0x12 ++ ++/* HDMI TX opcode */ ++#define HDMI_TX_READ 0x00 ++#define HDMI_TX_WRITE 0x01 ++#define HDMI_TX_UPDATE_READ 0x02 ++#define HDMI_TX_EDID 0x03 ++#define HDMI_TX_EVENTS 0x04 ++#define HDMI_TX_HPD_STATUS 0x05 ++#define HDMI_TX_DEBUG_ECHO 0xAA ++#define HDMI_TX_TEST 0xBB ++#define HDMI_TX_EDID_INTERNAL 0xF0 ++ ++#define FW_STANDBY 0 ++#define FW_ACTIVE 1 ++ ++#define MHDP_EVENT_ENABLE_HPD BIT(0) ++#define MHDP_EVENT_ENABLE_TRAINING BIT(1) ++ ++#define LINK_TRAINING_NOT_ACTIVE 0 ++#define LINK_TRAINING_RUN 1 ++#define LINK_TRAINING_RESTART 2 ++ ++#define CONTROL_VIDEO_IDLE 0 ++#define CONTROL_VIDEO_VALID 1 ++ ++#define TU_CNT_RST_EN BIT(15) ++#define VIF_BYPASS_INTERLACE BIT(13) ++#define INTERLACE_FMT_DET BIT(12) ++#define INTERLACE_DTCT_WIN 0x20 ++ ++#define DP_FRAMER_SP_INTERLACE_EN BIT(2) ++#define DP_FRAMER_SP_HSP BIT(1) ++#define DP_FRAMER_SP_VSP BIT(0) ++ ++/* capability */ ++#define AUX_HOST_INVERT 3 ++#define FAST_LT_SUPPORT 1 ++#define FAST_LT_NOT_SUPPORT 0 ++#define LANE_MAPPING_NORMAL 0x1b ++#define LANE_MAPPING_FLIPPED 0xe4 ++#define ENHANCED 1 ++#define SCRAMBLER_EN BIT(4) ++ ++#define FULL_LT_STARTED BIT(0) ++#define FASE_LT_STARTED BIT(1) ++#define CLK_RECOVERY_FINISHED BIT(2) ++#define EQ_PHASE_FINISHED BIT(3) ++#define FASE_LT_START_FINISHED BIT(4) ++#define CLK_RECOVERY_FAILED BIT(5) ++#define EQ_PHASE_FAILED BIT(6) ++#define FASE_LT_FAILED BIT(7) ++ ++#define DPTX_HPD_EVENT BIT(0) ++#define DPTX_TRAINING_EVENT BIT(1) ++#define HDCP_TX_STATUS_EVENT BIT(4) ++#define HDCP2_TX_IS_KM_STORED_EVENT BIT(5) ++#define HDCP2_TX_STORE_KM_EVENT BIT(6) ++#define HDCP_TX_IS_RECEIVER_ID_VALID_EVENT BIT(7) ++ ++#define TU_SIZE 30 ++#define CDNS_DP_MAX_LINK_RATE 540000 ++ ++#define F_HDMI_ENCODING(x) (((x) & ((1 << 2) - 1)) << 16) ++#define F_VIF_DATA_WIDTH(x) (((x) & ((1 << 2) - 1)) << 2) ++#define F_HDMI_MODE(x) (((x) & ((1 << 2) - 1)) << 0) ++#define F_GCP_EN(x) (((x) & ((1 << 1) - 1)) << 12) ++#define F_DATA_EN(x) (((x) & ((1 << 1) - 1)) << 15) ++#define F_HDMI2_PREAMBLE_EN(x) (((x) & ((1 << 1) - 1)) << 18) ++#define F_PIC_3D(x) (((x) & ((1 << 4) - 1)) << 7) ++#define F_BCH_EN(x) (((x) & ((1 << 1) - 1)) << 11) ++#define F_SOURCE_PHY_MHDP_SEL(x) (((x) & ((1 << 2) - 1)) << 3) ++#define F_HPD_VALID_WIDTH(x) (((x) & ((1 << 12) - 1)) << 0) ++#define F_HPD_GLITCH_WIDTH(x) (((x) & ((1 << 8) - 1)) << 12) ++#define F_HDMI2_CTRL_IL_MODE(x) (((x) & ((1 << 1) - 1)) << 19) ++#define F_SOURCE_PHY_LANE0_SWAP(x) (((x) & ((1 << 2) - 1)) << 0) ++#define F_SOURCE_PHY_LANE1_SWAP(x) (((x) & ((1 << 2) - 1)) << 2) ++#define F_SOURCE_PHY_LANE2_SWAP(x) (((x) & ((1 << 2) - 1)) << 4) ++#define F_SOURCE_PHY_LANE3_SWAP(x) (((x) & ((1 << 2) - 1)) << 6) ++#define F_SOURCE_PHY_COMB_BYPASS(x) (((x) & ((1 << 1) - 1)) << 21) ++#define F_SOURCE_PHY_20_10(x) (((x) & ((1 << 1) - 1)) << 22) ++#define F_PKT_ALLOC_ADDRESS(x) (((x) & ((1 << 4) - 1)) << 0) ++#define F_ACTIVE_IDLE_TYPE(x) (((x) & ((1 << 1) - 1)) << 17) ++#define F_FIFO1_FLUSH(x) (((x) & ((1 << 1) - 1)) << 0) ++#define F_PKT_ALLOC_WR_EN(x) (((x) & ((1 << 1) - 1)) << 0) ++#define F_DATA_WR(x) (x) ++#define F_WR_ADDR(x) (((x) & ((1 << 4) - 1)) << 0) ++#define F_HOST_WR(x) (((x) & ((1 << 1) - 1)) << 0) ++#define F_TYPE_VALID(x) (((x) & ((1 << 1) - 1)) << 16) ++#define F_PACKET_TYPE(x) (((x) & ((1 << 8) - 1)) << 8) ++ ++/* audio */ ++#define AUDIO_PACK_EN BIT(8) ++#define SAMPLING_FREQ(x) (((x) & 0xf) << 16) ++#define ORIGINAL_SAMP_FREQ(x) (((x) & 0xf) << 24) ++#define SYNC_WR_TO_CH_ZERO BIT(1) ++#define I2S_DEC_START BIT(1) ++#define AUDIO_SW_RST BIT(0) ++#define SMPL2PKT_EN BIT(1) ++#define MAX_NUM_CH(x) (((x) & 0x1f) - 1) ++#define NUM_OF_I2S_PORTS(x) ((((x) / 2 - 1) & 0x3) << 5) ++#define AUDIO_TYPE_LPCM (2 << 7) ++#define CFG_SUB_PCKT_NUM(x) ((((x) - 1) & 0x7) << 11) ++#define AUDIO_CH_NUM(x) ((((x) - 1) & 0x1f) << 2) ++#define TRANS_SMPL_WIDTH_16 0 ++#define TRANS_SMPL_WIDTH_24 BIT(11) ++#define TRANS_SMPL_WIDTH_32 (2 << 11) ++#define I2S_DEC_PORT_EN(x) (((x) & 0xf) << 17) ++#define SPDIF_ENABLE BIT(21) ++#define SPDIF_AVG_SEL BIT(20) ++#define SPDIF_JITTER_BYPASS BIT(19) ++#define SPDIF_FIFO_MID_RANGE(x) (((x) & 0xff) << 11) ++#define SPDIF_JITTER_THRSH(x) (((x) & 0xff) << 3) ++#define SPDIF_JITTER_AVG_WIN(x) ((x) & 0x7) ++ ++/* Reference cycles when using lane clock as reference */ ++#define LANE_REF_CYC 0x8000 ++ ++#define HOTPLUG_DEBOUNCE_MS 200 ++ ++#define IRQ_IN 0 ++#define IRQ_OUT 1 ++#define IRQ_NUM 2 ++ ++#define cdns_mhdp_plat_call(mhdp, operation) \ ++ (!(mhdp) ? -ENODEV : (((mhdp)->plat_data && (mhdp)->plat_data->operation) ? \ ++ (mhdp)->plat_data->operation(mhdp) : ENOIOCTLCMD)) ++ ++/* bus access type */ ++enum { ++ BUS_TYPE_NORMAL_APB = 0, ++ BUS_TYPE_NORMAL_SAPB = 1, ++ BUS_TYPE_LOW4K_APB = 2, ++ BUS_TYPE_LOW4K_SAPB = 3, ++}; ++ ++enum voltage_swing_level { ++ VOLTAGE_LEVEL_0, ++ VOLTAGE_LEVEL_1, ++ VOLTAGE_LEVEL_2, ++ VOLTAGE_LEVEL_3, ++}; ++ ++enum pre_emphasis_level { ++ PRE_EMPHASIS_LEVEL_0, ++ PRE_EMPHASIS_LEVEL_1, ++ PRE_EMPHASIS_LEVEL_2, ++ PRE_EMPHASIS_LEVEL_3, ++}; ++ ++enum pattern_set { ++ PTS1 = BIT(0), ++ PTS2 = BIT(1), ++ PTS3 = BIT(2), ++ PTS4 = BIT(3), ++ DP_NONE = BIT(4) ++}; ++ ++enum vic_color_depth { ++ BCS_6 = 0x1, ++ BCS_8 = 0x2, ++ BCS_10 = 0x4, ++ BCS_12 = 0x8, ++ BCS_16 = 0x10, ++}; ++ ++enum vic_bt_type { ++ BT_601 = 0x0, ++ BT_709 = 0x1, ++}; ++ ++enum audio_format { ++ AFMT_I2S = 0, ++ AFMT_SPDIF_INT = 1, ++ AFMT_SPDIF_EXT = 2, ++ AFMT_UNUSED, ++}; ++ ++enum { ++ MODE_DVI, ++ MODE_HDMI_1_4, ++ MODE_HDMI_2_0, ++}; ++ ++struct audio_info { ++ enum audio_format format; ++ int sample_rate; ++ int channels; ++ int sample_width; ++ int connector_type; ++}; ++ ++enum vic_pxl_encoding_format { ++ PXL_RGB = 0x1, ++ YCBCR_4_4_4 = 0x2, ++ YCBCR_4_2_2 = 0x4, ++ YCBCR_4_2_0 = 0x8, ++ Y_ONLY = 0x10, ++}; ++ ++struct video_info { ++ bool h_sync_polarity; ++ bool v_sync_polarity; ++ bool interlaced; ++ int color_depth; ++ enum vic_pxl_encoding_format color_fmt; ++}; ++ ++struct cdns_mhdp_host { ++ unsigned int link_rate; ++ u8 lanes_cnt; ++ u8 volt_swing; ++ u8 pre_emphasis; ++ u8 pattern_supp; ++ u8 fast_link; ++ u8 lane_mapping; ++ u8 enhanced; ++}; ++ ++struct cdns_mhdp_sink { ++ unsigned int link_rate; ++ u8 lanes_cnt; ++ u8 pattern_supp; ++ u8 fast_link; ++ u8 enhanced; ++}; ++ ++struct cdns_mhdp_bridge; ++struct cdns_mhdp_connector; ++ ++struct cdns_mhdp_bridge { ++ struct cdns_mhdp_device *mhdp; ++ struct drm_bridge base; ++ int pbn; ++ int8_t stream_id; ++ struct cdns_mhdp_connector *connector; ++ bool is_active; ++}; ++ ++struct cdns_mhdp_connector { ++ struct drm_connector base; ++ bool is_mst_connector; ++ struct drm_dp_mst_port *port; ++ struct cdns_mhdp_bridge *bridge; ++}; ++ ++struct cdns_mhdp_cec { ++ struct cec_adapter *adap; ++ struct device *dev; ++ struct mutex lock; ++ ++ struct cec_msg msg; ++ struct task_struct *cec_worker; ++}; ++ ++struct cdns_plat_data { ++ /* Vendor PHY support */ ++ int (*bind)(struct platform_device *pdev, ++ struct drm_encoder *encoder, ++ struct cdns_mhdp_device *mhdp); ++ void (*unbind)(struct device *dev); ++ ++ void (*plat_init)(struct cdns_mhdp_device *mhdp); ++ void (*plat_deinit)(struct cdns_mhdp_device *mhdp); ++ ++ int (*phy_set)(struct cdns_mhdp_device *mhdp); ++ bool (*phy_video_valid)(struct cdns_mhdp_device *mhdp); ++ int (*firmware_init)(struct cdns_mhdp_device *mhdp); ++ void (*pclk_rate)(struct cdns_mhdp_device *mhdp); ++ ++ int (*suspend)(struct cdns_mhdp_device *mhdp); ++ int (*resume)(struct cdns_mhdp_device *mhdp); ++ ++ int (*power_on)(struct cdns_mhdp_device *mhdp); ++ int (*power_off)(struct cdns_mhdp_device *mhdp); ++ ++ int bus_type; ++ int video_format; ++ char is_dp; ++ char *plat_name; ++}; ++ ++struct drm_dp_link { ++ unsigned char revision; ++ unsigned int rate; ++ unsigned int num_lanes; ++ unsigned long capabilities; ++}; ++ ++struct cdns_mhdp_device { ++ void __iomem *regs_base; ++ void __iomem *regs_sec; ++ ++ int bus_type; ++ ++ struct device *dev; ++ ++ struct cdns_mhdp_connector connector; ++ struct clk *spdif_clk; ++ struct reset_control *spdif_rst; ++ ++ struct platform_device *audio_pdev; ++ struct audio_info audio_info; ++ ++ struct cdns_mhdp_bridge bridge; ++ struct phy *phy; ++ ++ struct video_info video_info; ++ struct drm_display_mode mode; ++ const struct drm_display_mode *valid_mode; ++ unsigned int fw_version; ++ ++ struct drm_dp_mst_topology_mgr mst_mgr; ++ struct delayed_work hotplug_work; ++ ++ u32 lane_mapping; ++ bool link_up; ++ bool power_up; ++ bool plugged; ++ bool force_mode_set; ++ bool is_hpd; ++ bool is_ls1028a; ++ struct mutex lock; ++ struct mutex iolock; ++ ++ int irq[IRQ_NUM]; ++ ++ union { ++ struct _dp_data { ++ struct drm_dp_link link; ++ struct drm_dp_aux aux; ++ struct cdns_mhdp_host host; ++ struct cdns_mhdp_sink sink; ++ struct cdns_mhdp_mst_cbs cbs; ++ bool is_mst; ++ bool can_mst; ++ } dp; ++ struct _hdmi_data { ++ struct cdns_mhdp_cec cec; ++ u32 char_rate; ++ u32 hdmi_type; ++ } hdmi; ++ }; ++ const struct cdns_plat_data *plat_data; ++ ++}; ++ ++u32 cdns_mhdp_bus_read(struct cdns_mhdp_device *mhdp, u32 offset); ++void cdns_mhdp_bus_write(u32 val, struct cdns_mhdp_device *mhdp, u32 offset); ++void cdns_mhdp_clock_reset(struct cdns_mhdp_device *mhdp); ++void cdns_mhdp_set_fw_clk(struct cdns_mhdp_device *mhdp, unsigned long clk); ++u32 cdns_mhdp_get_fw_clk(struct cdns_mhdp_device *mhdp); ++int cdns_mhdp_load_firmware(struct cdns_mhdp_device *mhdp, const u32 *i_mem, ++ u32 i_size, const u32 *d_mem, u32 d_size); ++int cdns_mhdp_set_firmware_active(struct cdns_mhdp_device *mhdp, bool enable); ++int cdns_mhdp_set_host_cap(struct cdns_mhdp_device *mhdp, bool flip); ++int cdns_mhdp_event_config(struct cdns_mhdp_device *mhdp); ++u32 cdns_mhdp_get_event(struct cdns_mhdp_device *mhdp); ++int cdns_mhdp_get_hpd_status(struct cdns_mhdp_device *mhdp); ++int cdns_mhdp_dpcd_write(struct cdns_mhdp_device *mhdp, u32 addr, u8 value); ++int cdns_mhdp_dpcd_read(struct cdns_mhdp_device *mhdp, ++ u32 addr, u8 *data, u16 len); ++int cdns_mhdp_get_edid_block(void *mhdp, u8 *edid, ++ unsigned int block, size_t length); ++int cdns_mhdp_train_link(struct cdns_mhdp_device *mhdp); ++int cdns_mhdp_set_video_status(struct cdns_mhdp_device *mhdp, int active); ++int cdns_mhdp_config_video(struct cdns_mhdp_device *mhdp); ++ ++/* Audio */ ++int cdns_mhdp_audio_stop(struct cdns_mhdp_device *mhdp, ++ struct audio_info *audio); ++int cdns_mhdp_audio_mute(struct cdns_mhdp_device *mhdp, bool enable); ++int cdns_mhdp_audio_config(struct cdns_mhdp_device *mhdp, ++ struct audio_info *audio); ++int cdns_mhdp_register_audio_driver(struct device *dev); ++void cdns_mhdp_unregister_audio_driver(struct device *dev); ++ ++int cdns_mhdp_reg_read(struct cdns_mhdp_device *mhdp, u32 addr); ++int cdns_mhdp_reg_write(struct cdns_mhdp_device *mhdp, u32 addr, u32 val); ++int cdns_mhdp_reg_write_bit(struct cdns_mhdp_device *mhdp, u16 addr, ++ u8 start_bit, u8 bits_no, u32 val); ++int cdns_mhdp_adjust_lt(struct cdns_mhdp_device *mhdp, u8 nlanes, ++ u16 udelay, u8 *lanes_data, ++ u8 *dpcd); ++ ++int cdns_mhdp_read_hpd(struct cdns_mhdp_device *mhdp); ++u32 cdns_phy_reg_read(struct cdns_mhdp_device *mhdp, u32 addr); ++int cdns_phy_reg_write(struct cdns_mhdp_device *mhdp, u32 addr, u32 val); ++int cdns_mhdp_mailbox_send(struct cdns_mhdp_device *mhdp, u8 module_id, ++ u8 opcode, u16 size, u8 *message); ++int cdns_mhdp_mailbox_read_receive(struct cdns_mhdp_device *mhdp, ++ u8 *buff, u16 buff_size); ++int cdns_mhdp_mailbox_validate_receive(struct cdns_mhdp_device *mhdp, ++ u8 module_id, u8 opcode, ++ u16 req_size); ++int cdns_mhdp_mailbox_read(struct cdns_mhdp_device *mhdp); ++ ++void cdns_mhdp_infoframe_set(struct cdns_mhdp_device *mhdp, ++ u8 entry_id, u8 packet_len, u8 *packet, u8 packet_type); ++int cdns_hdmi_get_edid_block(void *data, u8 *edid, u32 block, size_t length); ++int cdns_hdmi_scdc_read(struct cdns_mhdp_device *mhdp, u8 addr, u8 *data); ++int cdns_hdmi_scdc_write(struct cdns_mhdp_device *mhdp, u8 addr, u8 value); ++int cdns_hdmi_ctrl_init(struct cdns_mhdp_device *mhdp, int protocol, u32 char_rate); ++int cdns_hdmi_mode_config(struct cdns_mhdp_device *mhdp, struct drm_display_mode *mode, ++ struct video_info *video_info); ++int cdns_hdmi_disable_gcp(struct cdns_mhdp_device *mhdp); ++int cdns_hdmi_enable_gcp(struct cdns_mhdp_device *mhdp); ++ ++bool cdns_mhdp_check_alive(struct cdns_mhdp_device *mhdp); ++ ++/* HDMI */ ++int cdns_hdmi_probe(struct platform_device *pdev, ++ struct cdns_mhdp_device *mhdp); ++void cdns_hdmi_remove(struct platform_device *pdev); ++void cdns_hdmi_unbind(struct device *dev); ++int cdns_hdmi_bind(struct platform_device *pdev, ++ struct drm_encoder *encoder, struct cdns_mhdp_device *mhdp); ++void cdns_hdmi_set_sample_rate(struct cdns_mhdp_device *mhdp, unsigned int rate); ++void cdns_hdmi_audio_enable(struct cdns_mhdp_device *mhdp); ++void cdns_hdmi_audio_disable(struct cdns_mhdp_device *mhdp); ++/* DP */ ++int cdns_dp_probe(struct platform_device *pdev, ++ struct cdns_mhdp_device *mhdp); ++void cdns_dp_remove(struct platform_device *pdev); ++void cdns_dp_unbind(struct device *dev); ++int cdns_dp_bind(struct platform_device *pdev, ++ struct drm_encoder *encoder, struct cdns_mhdp_device *mhdp); ++ ++/* CEC */ ++#ifdef CONFIG_DRM_CDNS_HDMI_CEC ++int cdns_mhdp_register_cec_driver(struct device *dev); ++int cdns_mhdp_unregister_cec_driver(struct device *dev); ++#endif ++ ++#endif /* CDNS_MHDP_COMMON_H_ */ +-- +2.30.0 +