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code/machine/mipssim.h
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code/machine/mipssim.h
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// mipssim.h
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// Internal data structures for simulating the MIPS instruction set.
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//
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// DO NOT CHANGE -- part of the machine emulation
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//
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// Copyright (c) 1992-1993 The Regents of the University of California.
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// All rights reserved. See copyright.h for copyright notice and limitation
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// of liability and disclaimer of warranty provisions.
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#ifndef MIPSSIM_H
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#define MIPSSIM_H
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#include "copyright.h"
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/*
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* OpCode values. The names are straight from the MIPS
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* manual except for the following special ones:
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*
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* OP_UNIMP - means that this instruction is legal, but hasn't
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* been implemented in the simulator yet.
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* OP_RES - means that this is a reserved opcode (it isn't
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* supported by the architecture).
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*/
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#define OP_ADD 1
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#define OP_ADDI 2
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#define OP_ADDIU 3
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#define OP_ADDU 4
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#define OP_AND 5
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#define OP_ANDI 6
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#define OP_BEQ 7
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#define OP_BGEZ 8
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#define OP_BGEZAL 9
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#define OP_BGTZ 10
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#define OP_BLEZ 11
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#define OP_BLTZ 12
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#define OP_BLTZAL 13
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#define OP_BNE 14
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#define OP_DIV 16
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#define OP_DIVU 17
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#define OP_J 18
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#define OP_JAL 19
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#define OP_JALR 20
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#define OP_JR 21
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#define OP_LB 22
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#define OP_LBU 23
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#define OP_LH 24
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#define OP_LHU 25
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#define OP_LUI 26
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#define OP_LW 27
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#define OP_LWL 28
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#define OP_LWR 29
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#define OP_MFHI 31
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#define OP_MFLO 32
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#define OP_MTHI 34
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#define OP_MTLO 35
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#define OP_MULT 36
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#define OP_MULTU 37
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#define OP_NOR 38
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#define OP_OR 39
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#define OP_ORI 40
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#define OP_RFE 41
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#define OP_SB 42
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#define OP_SH 43
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#define OP_SLL 44
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#define OP_SLLV 45
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#define OP_SLT 46
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#define OP_SLTI 47
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#define OP_SLTIU 48
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#define OP_SLTU 49
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#define OP_SRA 50
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#define OP_SRAV 51
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#define OP_SRL 52
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#define OP_SRLV 53
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#define OP_SUB 54
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#define OP_SUBU 55
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#define OP_SW 56
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#define OP_SWL 57
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#define OP_SWR 58
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#define OP_XOR 59
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#define OP_XORI 60
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#define OP_SYSCALL 61
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#define OP_UNIMP 62
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#define OP_RES 63
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#define MaxOpcode 63
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/*
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* Miscellaneous definitions:
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*/
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#define IndexToAddr(x) ((x) << 2)
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#define SIGN_BIT 0x80000000
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#define R31 31
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/*
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* The table below is used to translate bits 31:26 of the instruction
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* into a value suitable for the "opCode" field of a MemWord structure,
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* or into a special value for further decoding.
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*/
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#define SPECIAL 100
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#define BCOND 101
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#define IFMT 1
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#define JFMT 2
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#define RFMT 3
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struct OpInfo {
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int opCode; /* Translated op code. */
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int format; /* Format type (IFMT or JFMT or RFMT) */
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};
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static OpInfo opTable[] = {
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{SPECIAL, RFMT}, {BCOND, IFMT}, {OP_J, JFMT}, {OP_JAL, JFMT},
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{OP_BEQ, IFMT}, {OP_BNE, IFMT}, {OP_BLEZ, IFMT}, {OP_BGTZ, IFMT},
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{OP_ADDI, IFMT}, {OP_ADDIU, IFMT}, {OP_SLTI, IFMT}, {OP_SLTIU, IFMT},
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{OP_ANDI, IFMT}, {OP_ORI, IFMT}, {OP_XORI, IFMT}, {OP_LUI, IFMT},
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{OP_UNIMP, IFMT}, {OP_UNIMP, IFMT}, {OP_UNIMP, IFMT}, {OP_UNIMP, IFMT},
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{OP_RES, IFMT}, {OP_RES, IFMT}, {OP_RES, IFMT}, {OP_RES, IFMT},
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{OP_RES, IFMT}, {OP_RES, IFMT}, {OP_RES, IFMT}, {OP_RES, IFMT},
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{OP_RES, IFMT}, {OP_RES, IFMT}, {OP_RES, IFMT}, {OP_RES, IFMT},
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{OP_LB, IFMT}, {OP_LH, IFMT}, {OP_LWL, IFMT}, {OP_LW, IFMT},
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{OP_LBU, IFMT}, {OP_LHU, IFMT}, {OP_LWR, IFMT}, {OP_RES, IFMT},
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{OP_SB, IFMT}, {OP_SH, IFMT}, {OP_SWL, IFMT}, {OP_SW, IFMT},
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{OP_RES, IFMT}, {OP_RES, IFMT}, {OP_SWR, IFMT}, {OP_RES, IFMT},
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{OP_UNIMP, IFMT}, {OP_UNIMP, IFMT}, {OP_UNIMP, IFMT}, {OP_UNIMP, IFMT},
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{OP_RES, IFMT}, {OP_RES, IFMT}, {OP_RES, IFMT}, {OP_RES, IFMT},
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{OP_UNIMP, IFMT}, {OP_UNIMP, IFMT}, {OP_UNIMP, IFMT}, {OP_UNIMP, IFMT},
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{OP_RES, IFMT}, {OP_RES, IFMT}, {OP_RES, IFMT}, {OP_RES, IFMT}
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};
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/*
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* The table below is used to convert the "funct" field of SPECIAL
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* instructions into the "opCode" field of a MemWord.
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*/
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static int specialTable[] = {
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OP_SLL, OP_RES, OP_SRL, OP_SRA, OP_SLLV, OP_RES, OP_SRLV, OP_SRAV,
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OP_JR, OP_JALR, OP_RES, OP_RES, OP_SYSCALL, OP_UNIMP, OP_RES, OP_RES,
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OP_MFHI, OP_MTHI, OP_MFLO, OP_MTLO, OP_RES, OP_RES, OP_RES, OP_RES,
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OP_MULT, OP_MULTU, OP_DIV, OP_DIVU, OP_RES, OP_RES, OP_RES, OP_RES,
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OP_ADD, OP_ADDU, OP_SUB, OP_SUBU, OP_AND, OP_OR, OP_XOR, OP_NOR,
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OP_RES, OP_RES, OP_SLT, OP_SLTU, OP_RES, OP_RES, OP_RES, OP_RES,
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OP_RES, OP_RES, OP_RES, OP_RES, OP_RES, OP_RES, OP_RES, OP_RES,
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OP_RES, OP_RES, OP_RES, OP_RES, OP_RES, OP_RES, OP_RES, OP_RES
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};
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// Stuff to help print out each instruction, for debugging
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enum RegType { NONE, RS, RT, RD, EXTRA };
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struct OpString {
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const char *string; // Printed version of instruction
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RegType args[3];
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};
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static struct OpString opStrings[] = {
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{"Shouldn't happen", {NONE, NONE, NONE}},
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{"ADD r%d,r%d,r%d", {RD, RS, RT}},
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{"ADDI r%d,r%d,%d", {RT, RS, EXTRA}},
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{"ADDIU r%d,r%d,%d", {RT, RS, EXTRA}},
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{"ADDU r%d,r%d,r%d", {RD, RS, RT}},
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{"AND r%d,r%d,r%d", {RD, RS, RT}},
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{"ANDI r%d,r%d,%d", {RT, RS, EXTRA}},
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{"BEQ r%d,r%d,%d", {RS, RT, EXTRA}},
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{"BGEZ r%d,%d", {RS, EXTRA, NONE}},
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{"BGEZAL r%d,%d", {RS, EXTRA, NONE}},
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{"BGTZ r%d,%d", {RS, EXTRA, NONE}},
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{"BLEZ r%d,%d", {RS, EXTRA, NONE}},
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{"BLTZ r%d,%d", {RS, EXTRA, NONE}},
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{"BLTZAL r%d,%d", {RS, EXTRA, NONE}},
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{"BNE r%d,r%d,%d", {RS, RT, EXTRA}},
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{"Shouldn't happen", {NONE, NONE, NONE}},
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{"DIV r%d,r%d", {RS, RT, NONE}},
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{"DIVU r%d,r%d", {RS, RT, NONE}},
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{"J 4*%d", {EXTRA, NONE, NONE}},
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{"JAL 4*%d", {EXTRA, NONE, NONE}},
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{"JALR r%d,r%d", {RD, RS, NONE}},
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{"JR r%d,r%d", {RD, RS, NONE}},
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{"LB r%d,%d(r%d)", {RT, EXTRA, RS}},
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{"LBU r%d,%d(r%d)", {RT, EXTRA, RS}},
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{"LH r%d,%d(r%d)", {RT, EXTRA, RS}},
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{"LHU r%d,%d(r%d)", {RT, EXTRA, RS}},
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{"LUI r%d,%d", {RT, EXTRA, NONE}},
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{"LW r%d,%d(r%d)", {RT, EXTRA, RS}},
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{"LWL r%d,%d(r%d)", {RT, EXTRA, RS}},
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{"LWR r%d,%d(r%d)", {RT, EXTRA, RS}},
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{"Shouldn't happen", {NONE, NONE, NONE}},
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{"MFHI r%d", {RD, NONE, NONE}},
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{"MFLO r%d", {RD, NONE, NONE}},
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{"Shouldn't happen", {NONE, NONE, NONE}},
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{"MTHI r%d", {RS, NONE, NONE}},
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{"MTLO r%d", {RS, NONE, NONE}},
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{"MULT r%d,r%d", {RS, RT, NONE}},
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{"MULTU r%d,r%d", {RS, RT, NONE}},
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{"NOR r%d,r%d,r%d", {RD, RS, RT}},
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{"OR r%d,r%d,r%d", {RD, RS, RT}},
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{"ORI r%d,r%d,%d", {RT, RS, EXTRA}},
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{"RFE", {NONE, NONE, NONE}},
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{"SB r%d,%d(r%d)", {RT, EXTRA, RS}},
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{"SH r%d,%d(r%d)", {RT, EXTRA, RS}},
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{"SLL r%d,r%d,%d", {RD, RT, EXTRA}},
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{"SLLV r%d,r%d,r%d", {RD, RT, RS}},
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{"SLT r%d,r%d,r%d", {RD, RS, RT}},
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{"SLTI r%d,r%d,%d", {RT, RS, EXTRA}},
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{"SLTIU r%d,r%d,%d", {RT, RS, EXTRA}},
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{"SLTU r%d,r%d,r%d", {RD, RS, RT}},
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{"SRA r%d,r%d,%d", {RD, RT, EXTRA}},
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{"SRAV r%d,r%d,r%d", {RD, RT, RS}},
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{"SRL r%d,r%d,%d", {RD, RT, EXTRA}},
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{"SRLV r%d,r%d,r%d", {RD, RT, RS}},
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{"SUB r%d,r%d,r%d", {RD, RS, RT}},
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{"SUBU r%d,r%d,r%d", {RD, RS, RT}},
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{"SW r%d,%d(r%d)", {RT, EXTRA, RS}},
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{"SWL r%d,%d(r%d)", {RT, EXTRA, RS}},
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{"SWR r%d,%d(r%d)", {RT, EXTRA, RS}},
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{"XOR r%d,r%d,r%d", {RD, RS, RT}},
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{"XORI r%d,r%d,%d", {RT, RS, EXTRA}},
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{"SYSCALL", {NONE, NONE, NONE}},
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{"Unimplemented", {NONE, NONE, NONE}},
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{"Reserved", {NONE, NONE, NONE}}
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};
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#endif // MIPSSIM_H
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