ephase/reform2_mkkernel
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Yorick Barbanneau 2021-04-15 02:13:53 +02:00
commit 1bbd8d5146
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FROM debian:bullseye-slim
RUN apt update \
&& apt install -y --no-install-recommends gzip \
gcc-aarch64-linux-gnu \
make \
bc \
device-tree-compiler \
qemu-system-aarch64 \
qemu-user-static \
build-essential \
bison flex \
libssl-dev \
bash \
git \
ca-certificates
COPY docker/entrypoint.sh /tmp
COPY src/ /tmp
WORKDIR /tmp
CMD /tmp/entrypoint.sh
#CMD bash

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MNT Reform Kernel build script
------------------------------
Work in progress script for building Linux Kernel for the MNT Refom 2 computer.
## Build with docker
Build the image :
```
docker build -t reform_kernel_build .
```
Then run the container with with a directory mapped to `/output`:
```
docker run -v /home/docker/output:/output --env KERNEL_VERSION=5.11 --rm reform_kernel_build
```
You need to pass `KERNEL_VERSION` environment variable to your container do tell
`make_kernel.sh` which version to compile.
Kernel and dtb files will be in the directory mapped to `/output` in the
container.
## Licence
This work is derivated from MNT script found [here][l_mnt_image] and licenced
under the GPLv3 Licence
[l_mnt_image]:https://source.mnt.re/reform/reform-system-image/

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#!/bin/bash
# Entrypoint for reform-build-kernel docker image
if [ -f /output/Image ]
then
printf "Kernel image exist in destination aborting compilation.\n"
exit 0
fi
if ./make_kernel.sh
then
cp linux/arch/arm64/boot/Image /output/
cp linux/arch/arm64/boot/dts/freescale/imx8mq-mnt-reform2.dtb /output/imx8mq-mnt-reform2-single-display.dtb
cp linux/arch/arm64/boot/dts/freescale/imx8mq-mnt-reform2-hdmi.dtb /output/imx8mq-mnt-reform2-dual-display.dtb
else
printf "Error when building Kernel\n" 1>&2
exit 10
fi
exit 0

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// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Copyright 2018 Boundary Devices
* Copyright 2019-2021 MNT Research GmbH
*/
/dts-v1/;
#include "dt-bindings/input/input.h"
#include "dt-bindings/pwm/pwm.h"
#include "dt-bindings/usb/pd.h"
#include "dt-bindings/gpio/gpio.h"
#include "imx8mq.dtsi"
/ {
model = "MNT Reform 2";
compatible = "boundary,imx8mq-nitrogen8m_som", "fsl,imx8mq";
chosen {
stdout-path = "serial0:115200n8";
};
// 4GB of RAM
memory@40000000 {
device_type = "memory";
reg = <0x00000000 0x40000000 0 0xc0000000>; // TODO: confirm what this means
};
reg_vref_0v9: regulator-vref-0v9 {
compatible = "regulator-fixed";
regulator-name = "vref-0v9";
regulator-min-microvolt = <900000>;
regulator-max-microvolt = <900000>;
regulator-always-on;
};
reg_vref_1v2: regulator-vref-1v2 {
compatible = "regulator-fixed";
regulator-name = "vref-1v2";
regulator-min-microvolt = <1200000>;
regulator-max-microvolt = <1200000>;
regulator-always-on;
};
reg_vref_1v8: regulator-vref-1v8 {
compatible = "regulator-fixed";
regulator-name = "vref-1v8";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-always-on;
};
reg_vref_2v5: regulator-vref-2v5 {
compatible = "regulator-fixed";
regulator-name = "vref-2v5";
regulator-min-microvolt = <2500000>;
regulator-max-microvolt = <2500000>;
regulator-always-on;
};
reg_vref_3v3: regulator-vref-3v3 {
compatible = "regulator-fixed";
regulator-name = "vref-3v3";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-always-on;
};
reg_vref_5v: regulator-vref-5v {
compatible = "regulator-fixed";
regulator-name = "vref-5v";
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
regulator-always-on;
};
backlight: backlight {
compatible = "pwm-backlight";
pwms = <&pwm2 0 10000>;
enable-gpios = <&gpio1 10 GPIO_ACTIVE_HIGH>;
brightness-levels = <0 32 64 128 160 200 255>;
default-brightness-level = <6>;
};
panel {
compatible = "innolux,n125hce-gn1", "simple-panel";
power = <&reg_vref_3v3>;
backlight = <&backlight>;
no-hpd;
port@0 {
panel_in: endpoint {
remote-endpoint = <&edp_bridge_out>;
};
};
};
sound {
compatible = "simple-audio-card";
simple-audio-card,name = "wm8960-audio";
simple-audio-card,format = "i2s";
simple-audio-card,frame-master = <&dai_cpu_master>;
simple-audio-card,bitclock-master = <&dai_cpu_master>;
simple-audio-card,convert-rate = <48000>;
simple-audio-card,widgets =
"Microphone", "Mic Jack",
"Line", "Line In",
"Line", "Line Out",
"Speaker", "Speaker",
"Headphone", "Headphone Jack";
simple-audio-card,routing =
"Headphone Jack", "HP_L",
"Headphone Jack", "HP_R",
"Speaker", "SPK_LP",
"Speaker", "SPK_LN",
"Speaker", "SPK_RP",
"Speaker", "SPK_RN",
"Mic Jack", "MICB",
"LINPUT1", "Mic Jack",
"LINPUT2", "Line In",
"RINPUT2", "Line In";
dai_cpu_master: simple-audio-card,cpu {
sound-dai = <&sai2>;
};
dailink0: simple-audio-card,codec {
sound-dai = <&codec>;
};
};
pcie0_refclk: pcie0-refclk {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <100000000>;
};
pcie1_refclk: pcie1-refclk {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <100000000>;
};
};
&A53_0 {
cpu-supply = <&reg_arm_dram>;
};
&A53_1 {
cpu-supply = <&reg_arm_dram>;
};
&A53_2 {
cpu-supply = <&reg_arm_dram>;
};
&A53_3 {
cpu-supply = <&reg_arm_dram>;
};
/ {
soc@0 {
bus@32c00000 {
hdmi: hdmi@32c00000 {
status = "okay";
compatible = "cdn,imx8mq-hdmi";
reg = <0x32c00000 0x100000>,
<0x32e40000 0x40000>;
interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "plug_in", "plug_out";
lane-mapping = <0xe4>; // 0=0, 1=1, 2=2, 3=3 (no swapping)
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
#address-cells = <1>;
#size-cells = <0>;
hdmi_in: endpoint@0 {
reg = <0>;
remote-endpoint = <&dcss_hdmi_out>;
};
};
};
};
dcss: display-controller@32e00000 {
status = "okay";
compatible = "nxp,imx8mq-dcss";
reg = <0x32e00000 0x2d000>, <0x32e2f000 0x1000>;
interrupts = <6>, <8>, <9>;
interrupt-names = "ctxld", "ctxld_kick", "vblank";
interrupt-parent = <&irqsteer>;
clocks = <&clk IMX8MQ_CLK_DISP_APB_ROOT>,
<&clk IMX8MQ_CLK_DISP_AXI_ROOT>,
<&clk IMX8MQ_CLK_DISP_RTRM_ROOT>,
<&clk IMX8MQ_VIDEO2_PLL_OUT>,
<&clk IMX8MQ_CLK_DISP_DTRC>,
<&clk IMX8MQ_VIDEO2_PLL1_REF_SEL>,
<&clk IMX8MQ_CLK_PHY_27MHZ>;
clock-names = "apb", "axi", "rtrm", "pix", "dtrc", "pll_src", "pll_phy_ref";
assigned-clocks = <&clk IMX8MQ_CLK_DISP_AXI>,
<&clk IMX8MQ_CLK_DISP_RTRM>,
<&clk IMX8MQ_VIDEO2_PLL1_REF_SEL>,
<&clk IMX8MQ_VIDEO_PLL1_REF_SEL>,
<&clk IMX8MQ_CLK_DC_PIXEL>;
assigned-clock-parents = <&clk IMX8MQ_SYS1_PLL_800M>,
<&clk IMX8MQ_SYS1_PLL_800M>,
<&clk IMX8MQ_CLK_27M>,
<&clk IMX8MQ_CLK_25M>,
<&clk IMX8MQ_VIDEO_PLL1_OUT>;
assigned-clock-rates = <800000000>,
<400000000>,
<27000000>,
<25000000>,
<594000000>;
// external display (HDMI)
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
#address-cells = <1>;
#size-cells = <0>;
dcss_hdmi_out: endpoint@0 {
reg = <0>;
remote-endpoint = <&hdmi_in>;
};
};
};
};
};
};
};
// internal display
&lcdif {
status = "okay";
port@0 {
lcdif_mipi_dsi: endpoint {
remote-endpoint = <&mipi_dsi_in>;
};
};
};
&dphy {
status = "okay";
};
&fec1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_fec1>;
phy-mode = "rgmii-id";
phy-handle = <&ethphy0>;
fsl,magic-packet;
status = "okay";
mdio {
#address-cells = <1>;
#size-cells = <0>;
ethphy0: ethernet-phy@4 {
compatible = "ethernet-phy-ieee802.3-c22";
reg = <4>;
interrupts = <&gpio1 11 IRQ_TYPE_LEVEL_LOW>;
reset-gpios = <&gpio1 9 GPIO_ACTIVE_LOW>; // TODO: useful?
};
};
};
&i2c1 {
clock-frequency = <400000>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c1>;
status = "okay";
// I2C Mux on Nitrogen8M_SOM
i2cmux@70 {
compatible = "nxp,pca9546";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c1_pca9546>;
reg = <0x70>;
reset-gpios = <&gpio1 4 GPIO_ACTIVE_LOW>;
#address-cells = <1>;
#size-cells = <0>;
i2c1a: i2c1@0 {
reg = <0>;
#address-cells = <1>;
#size-cells = <0>;
// Regulator on Nitrogen8M_SOM
reg_arm_dram: fan53555@60 {
compatible = "fcs,fan53555";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_reg_arm_dram>;
reg = <0x60>;
regulator-min-microvolt = <900000>;
regulator-max-microvolt = <1000000>;
regulator-ramp-delay = <8000>;
regulator-always-on;
vsel-gpios = <&gpio3 24 GPIO_ACTIVE_HIGH>;
};
};
i2c1b: i2c1@1 {
reg = <1>;
#address-cells = <1>;
#size-cells = <0>;
// Regulator on Nitrogen8M_SOM
reg_dram_1p1v: fan53555@60 {
compatible = "fcs,fan53555";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_reg_dram_1p1v>;
reg = <0x60>;
regulator-min-microvolt = <1100000>;
regulator-max-microvolt = <1100000>;
regulator-ramp-delay = <8000>;
regulator-always-on;
vsel-gpios = <&gpio2 11 GPIO_ACTIVE_HIGH>;
};
};
i2c1c: i2c1@2 {
reg = <2>;
#address-cells = <1>;
#size-cells = <0>;
// Regulator on Nitrogen8M_SOM
reg_soc_gpu_vpu: fan53555@60 {
compatible = "fcs,fan53555";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_reg_soc_gpu_vpu>;
reg = <0x60>;
regulator-min-microvolt = <900000>;
regulator-max-microvolt = <1000000>;
regulator-ramp-delay = <8000>;
regulator-always-on;
vsel-gpios = <&gpio2 20 GPIO_ACTIVE_HIGH>;
};
};
// No peripheral connected, available on DSI connector
i2c1d: i2c1@3 {
reg = <3>;
#address-cells = <1>;
#size-cells = <0>;
};
};
};
// No peripheral connected, available on CSI connector
&i2c2 {
status = "disabled";
};
&i2c3 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c3>;
status = "okay";
// Audio chip on motherboard
codec: wm8960@1a {
compatible = "wlf,wm8960";
reg = <0x1a>;
clocks = <&clk IMX8MQ_CLK_SAI2>;
clock-names = "mclk";
#sound-dai-cells = <0>;
};
// Realtime clock chip on motherboard
pcf8523: pcf8523@68 {
compatible = "nxp,pcf8523";
reg = <0x68>;
};
};
&i2c4 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c4>;
status = "okay";
// DSI to eDP converter on motherboard
edp_bridge: sn65dsi86@2c {
compatible = "ti,sn65dsi86";
reg = <0x2c>;
enable-gpios = <&gpio3 20 GPIO_ACTIVE_HIGH>;
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
edp_bridge_in: endpoint {
remote-endpoint = <&mipi_dsi_out>;
};
};
port@1 {
reg = <1>;
edp_bridge_out: endpoint {
remote-endpoint = <&panel_in>;
};
};
};
};
};
// TODO: add external pin numbers
&iomuxc {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_hog>;
pinctrl_hog: hoggrp {
fsl,pins = <
MX8MQ_IOMUXC_SAI5_RXC_GPIO3_IO20 0x19 // WL_EN on Nitrogen8M_SOM, pin 38, goes to /EN input of SN65DSI86
MX8MQ_IOMUXC_GPIO1_IO14_GPIO1_IO14 0x56 // TODO: check pullup of usb hub reset on the board (0x40)
>;
};
pinctrl_fec1: fec1grp {
fsl,pins = <
MX8MQ_IOMUXC_ENET_MDC_ENET1_MDC 0x3
MX8MQ_IOMUXC_ENET_MDIO_ENET1_MDIO 0x23
MX8MQ_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x1f
MX8MQ_IOMUXC_ENET_TXC_ENET1_RGMII_TXC 0x1f
MX8MQ_IOMUXC_ENET_TD0_ENET1_RGMII_TD0 0x1f
MX8MQ_IOMUXC_ENET_TD1_ENET1_RGMII_TD1 0x1f
MX8MQ_IOMUXC_ENET_TD2_ENET1_RGMII_TD2 0x1f
MX8MQ_IOMUXC_ENET_TD3_ENET1_RGMII_TD3 0x1f
MX8MQ_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x91
MX8MQ_IOMUXC_ENET_RXC_ENET1_RGMII_RXC 0x91
MX8MQ_IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x91
MX8MQ_IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x91
MX8MQ_IOMUXC_ENET_RD2_ENET1_RGMII_RD2 0x91
MX8MQ_IOMUXC_ENET_RD3_ENET1_RGMII_RD3 0x91
MX8MQ_IOMUXC_GPIO1_IO09_GPIO1_IO9 0x19
MX8MQ_IOMUXC_GPIO1_IO11_GPIO1_IO11 0x59
>;
};
pinctrl_i2c1: i2c1grp {
fsl,pins = <
MX8MQ_IOMUXC_I2C1_SCL_I2C1_SCL 0x4000007f
MX8MQ_IOMUXC_I2C1_SDA_I2C1_SDA 0x4000007f
>;
};
pinctrl_i2c1_pca9546: i2c1-pca9546grp {
fsl,pins = <
MX8MQ_IOMUXC_GPIO1_IO04_GPIO1_IO4 0x46
>;
};
pinctrl_i2c2: i2c2grp {
fsl,pins = <
MX8MQ_IOMUXC_I2C2_SCL_I2C2_SCL 0x4000007f
MX8MQ_IOMUXC_I2C2_SDA_I2C2_SDA 0x4000007f
>;
};
pinctrl_i2c3: i2c3grp {
fsl,pins = <
MX8MQ_IOMUXC_I2C3_SCL_I2C3_SCL 0x4000007f
MX8MQ_IOMUXC_I2C3_SDA_I2C3_SDA 0x4000007f
>;
};
pinctrl_i2c4: i2c4grp {
fsl,pins = <
MX8MQ_IOMUXC_I2C4_SCL_I2C4_SCL 0x4000007f
MX8MQ_IOMUXC_I2C4_SDA_I2C4_SDA 0x4000007f
>;
};
pinctrl_pcie0: pcie0grp {
fsl,pins = <
MX8MQ_IOMUXC_ECSPI1_MOSI_GPIO5_IO7 0x16
>;
};
pinctrl_pcie1: pcie1grp {
fsl,pins = <
MX8MQ_IOMUXC_SAI5_RXD2_GPIO3_IO23 0x16
>;
};
pinctrl_pwm2: pwm2grp {
fsl,pins = <
MX8MQ_IOMUXC_SPDIF_RX_PWM2_OUT 0x16
>;
};
pinctrl_pwm3: pwm3grp {
fsl,pins = <
MX8MQ_IOMUXC_SPDIF_TX_PWM3_OUT 0x16
>;
};
// Backlight
pinctrl_pwm4: pwm4grp {
fsl,pins = <
MX8MQ_IOMUXC_SAI3_MCLK_PWM4_OUT 0x16
>;
};
pinctrl_reg_arm_dram: reg-arm-dram {
fsl,pins = <
MX8MQ_IOMUXC_SAI5_RXD3_GPIO3_IO24 0x16
>;
};
pinctrl_reg_dram_1p1v: reg-dram-1p1v {
fsl,pins = <
MX8MQ_IOMUXC_SD1_STROBE_GPIO2_IO11 0x16
>;
};
pinctrl_reg_soc_gpu_vpu: reg-soc-gpu-vpu {
fsl,pins = <
MX8MQ_IOMUXC_SD2_WP_GPIO2_IO20 0x16
>;
};
pinctrl_sai2: sai2grp {
fsl,pins = <
MX8MQ_IOMUXC_SAI2_RXD0_SAI2_RX_DATA0 0xd6 /* Pin 166 */
MX8MQ_IOMUXC_SAI2_RXFS_SAI2_RX_SYNC 0xd6 /* Pin 168 */
MX8MQ_IOMUXC_SAI2_TXC_SAI2_TX_BCLK 0xd6 /* Pin 170 */
MX8MQ_IOMUXC_SAI2_TXFS_SAI2_TX_SYNC 0xd6 /* Pin 172 */
MX8MQ_IOMUXC_SAI2_RXC_SAI2_RX_BCLK 0xd6 /* Pin 174 */
MX8MQ_IOMUXC_SAI2_MCLK_SAI2_MCLK 0xd6 /* Pin 176 */
MX8MQ_IOMUXC_SAI2_TXD0_SAI2_TX_DATA0 0xd6 /* Pin 168 */
>;
};
pinctrl_uart1: uart1grp {
fsl,pins = <
MX8MQ_IOMUXC_UART1_RXD_UART1_DCE_RX 0x45
MX8MQ_IOMUXC_UART1_TXD_UART1_DCE_TX 0x45
>;
};
pinctrl_uart2: uart2grp {
fsl,pins = <
MX8MQ_IOMUXC_UART2_RXD_UART2_DCE_RX 0x45
MX8MQ_IOMUXC_UART2_TXD_UART2_DCE_TX 0x45
>;
};
pinctrl_uart3: uart3grp {
fsl,pins = <
MX8MQ_IOMUXC_UART3_RXD_UART3_DCE_RX 0x45
MX8MQ_IOMUXC_UART3_TXD_UART3_DCE_TX 0x45
>;
};
pinctrl_usdhc1: usdhc1grp {
fsl,pins = <
MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK 0x83
MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD 0xc3
MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0 0xc3
MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1 0xc3
MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2 0xc3
MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3 0xc3
MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4 0xc3
MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5 0xc3
MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6 0xc3
MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7 0xc3
MX8MQ_IOMUXC_SD1_RESET_B_GPIO2_IO10 0x41
>;
};
pinctrl_usdhc1_100mhz: usdhc1-100mhzgrp {
fsl,pins = <
MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK 0x8d
MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD 0xcd
MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0 0xcd
MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1 0xcd
MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2 0xcd
MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3 0xcd
MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4 0xcd
MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5 0xcd
MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6 0xcd
MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7 0xcd
>;
};
pinctrl_usdhc1_200mhz: usdhc1-200mhzgrp {
fsl,pins = <
MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK 0x9f
MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD 0xdf
MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0 0xdf
MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1 0xdf
MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2 0xdf
MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3 0xdf
MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4 0xdf
MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5 0xdf
MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6 0xdf
MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7 0xdf
>;
};
pinctrl_usdhc2: usdhc2grp {
fsl,pins = <
MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK 0x03
MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD 0xc3
MX8MQ_IOMUXC_SD2_DATA0_USDHC2_DATA0 0xc3
MX8MQ_IOMUXC_SD2_DATA1_USDHC2_DATA1 0xc3
MX8MQ_IOMUXC_SD2_DATA2_USDHC2_DATA2 0xc3
MX8MQ_IOMUXC_SD2_DATA3_USDHC2_DATA3 0xc
>;
};
pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp {
fsl,pins = <
MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK 0x0d
MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD 0xcd
MX8MQ_IOMUXC_SD2_DATA0_USDHC2_DATA0 0xcd
MX8MQ_IOMUXC_SD2_DATA1_USDHC2_DATA1 0xcd
MX8MQ_IOMUXC_SD2_DATA2_USDHC2_DATA2 0xcd
MX8MQ_IOMUXC_SD2_DATA3_USDHC2_DATA3 0xcd
>;
};
pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp {
fsl,pins = <
MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK 0x1e
MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD 0xce
MX8MQ_IOMUXC_SD2_DATA0_USDHC2_DATA0 0xce
MX8MQ_IOMUXC_SD2_DATA1_USDHC2_DATA1 0xce
MX8MQ_IOMUXC_SD2_DATA2_USDHC2_DATA2 0xce
MX8MQ_IOMUXC_SD2_DATA3_USDHC2_DATA3 0xce
>;
};
pinctrl_wdog: wdoggrp {
fsl,pins = <
MX8MQ_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B 0xc6
>;
};
};
&mipi_dsi {
status = "okay";
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
#address-cells = <1>;
#size-cells = <0>;
reg = <0>;
mipi_dsi_in: endpoint@0 {
reg = <0>;
remote-endpoint = <&lcdif_mipi_dsi>;
};
};
port@1 {
reg = <1>;
mipi_dsi_out: endpoint {
remote-endpoint = <&edp_bridge_in>;
};
};
};
};
&pcie0 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_pcie0>;
reset-gpio = <&gpio5 7 GPIO_ACTIVE_LOW>;
internal-refclk;
clocks = <&clk IMX8MQ_CLK_PCIE1_ROOT>,
<&clk IMX8MQ_CLK_PCIE1_AUX>,
<&clk IMX8MQ_CLK_PCIE1_PHY>,
<&pcie0_refclk>;
clock-names = "pcie", "pcie_aux", "pcie_phy", "pcie_bus";
assigned-clocks = <&clk IMX8MQ_CLK_PCIE1_CTRL>,
<&clk IMX8MQ_CLK_PCIE1_PHY>;
assigned-clock-parents = <&clk IMX8MQ_SYS2_PLL_250M>,
<&clk IMX8MQ_SYS2_PLL_100M>;
status = "okay";
};
&pcie1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_pcie1>;
reset-gpio = <&gpio3 23 GPIO_ACTIVE_LOW>;
clocks = <&clk IMX8MQ_CLK_PCIE2_ROOT>,
<&clk IMX8MQ_CLK_PCIE2_AUX>,
<&clk IMX8MQ_CLK_PCIE2_PHY>,
<&pcie1_refclk>;
clock-names = "pcie", "pcie_aux", "pcie_phy", "pcie_bus";
status = "okay";
};
&pwm2 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_pwm2>;
status = "okay";
};
&pwm3 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_pwm3>;
status = "okay";
};
// Backlight control
&pwm4 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_pwm4>;
status = "okay";
};
&sai2 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_sai2>;
assigned-clocks = <&clk IMX8MQ_CLK_SAI2>;
assigned-clock-parents = <&clk IMX8MQ_AUDIO_PLL1_OUT>;
assigned-clock-rates = <12288000>;
status = "okay";
fsl,sai-asynchronous;
};
// Don't use i.MX8M internal RTC because we have a dedicated one
&snvs_rtc {
status = "disabled";
};
// Console
&uart1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart1>;
status = "okay";
};
// Auxiliary serial port on motherboard
&uart2 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart2>;
status = "okay";
};
// connected to LPC11U24 chip on the motherboard
&uart3 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart3>;
status = "okay";
};
&usb_dwc3_0 {
status = "okay";
dr_mode = "host";
};
&usb_dwc3_1 {
status = "okay";
dr_mode = "host";
};
&usb3_phy0 {
vbus-supply = <&reg_vref_5v>;
status = "okay";
};
&usb3_phy1 {
vbus-supply = <&reg_vref_5v>;
status = "okay";
};
// eMMC on Nitrogen8M_SOM
// TODO: HS currently doesn't work
&usdhc1 {
bus-width = <8>;
fsl,strobe-dll-delay-target = <5>;
fsl,tuning-start-tap = <63>;
fsl,tuning-step = <2>;
non-removable;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usdhc1>;
vmmc-supply = <&reg_vref_1v8>;
vqmmc-1-8-v;
status = "okay";
};
// SD Card on motherboard
// TODO: check keep-power-in-suspend, cap-sdio-irq
&usdhc2 {
assigned-clocks = <&clk IMX8MQ_CLK_USDHC2>;
assigned-clock-rates = <200000000>;
bus-width = <4>;
no-1-8-v; // We don't support 1.8V signaling
pinctrl-names = "default", "state_100mhz", "state_200mhz";
pinctrl-0 = <&pinctrl_usdhc2>;
pinctrl-1 = <&pinctrl_usdhc2_100mhz>;
pinctrl-2 = <&pinctrl_usdhc2_200mhz>;
vmmc-supply = <&reg_vref_3v3>;
status = "okay";
};
&wdog1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_wdog>;
fsl,ext-reset-output; // TODO check source for what this means
status = "okay";
};

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src/dts/imx8mq-mnt-reform2.dts Normal file
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// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Copyright 2018 Boundary Devices
* Copyright 2019-2021 MNT Research GmbH
*/
/dts-v1/;
#include "dt-bindings/input/input.h"
#include "dt-bindings/pwm/pwm.h"
#include "dt-bindings/usb/pd.h"
#include "dt-bindings/gpio/gpio.h"
#include "imx8mq.dtsi"
/ {
model = "MNT Reform 2";
compatible = "boundary,imx8mq-nitrogen8m_som", "fsl,imx8mq";
chosen {
stdout-path = "serial0:115200n8";
};
// 4GB of RAM
memory@40000000 {
device_type = "memory";
reg = <0x00000000 0x40000000 0 0xc0000000>; // TODO: confirm what this means
};
reg_vref_0v9: regulator-vref-0v9 {
compatible = "regulator-fixed";
regulator-name = "vref-0v9";
regulator-min-microvolt = <900000>;
regulator-max-microvolt = <900000>;
regulator-always-on;
};
reg_vref_1v2: regulator-vref-1v2 {
compatible = "regulator-fixed";
regulator-name = "vref-1v2";
regulator-min-microvolt = <1200000>;
regulator-max-microvolt = <1200000>;
regulator-always-on;
};
reg_vref_1v8: regulator-vref-1v8 {
compatible = "regulator-fixed";
regulator-name = "vref-1v8";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-always-on;
};
reg_vref_2v5: regulator-vref-2v5 {
compatible = "regulator-fixed";
regulator-name = "vref-2v5";
regulator-min-microvolt = <2500000>;
regulator-max-microvolt = <2500000>;
regulator-always-on;
};
reg_vref_3v3: regulator-vref-3v3 {
compatible = "regulator-fixed";
regulator-name = "vref-3v3";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-always-on;
};
reg_vref_5v: regulator-vref-5v {
compatible = "regulator-fixed";
regulator-name = "vref-5v";
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
regulator-always-on;
};
backlight: backlight {
compatible = "pwm-backlight";
pwms = <&pwm2 0 10000>;
enable-gpios = <&gpio1 10 GPIO_ACTIVE_HIGH>;
brightness-levels = <0 32 64 128 160 200 255>;
default-brightness-level = <6>;
};
panel {
compatible = "innolux,n125hce-gn1", "simple-panel";
power = <&reg_vref_3v3>;
backlight = <&backlight>;
no-hpd;
port@0 {
panel_in: endpoint {
remote-endpoint = <&edp_bridge_out>;
};
};
};
sound {
compatible = "simple-audio-card";
simple-audio-card,name = "wm8960-audio";
simple-audio-card,format = "i2s";
simple-audio-card,frame-master = <&dai_cpu_master>;
simple-audio-card,bitclock-master = <&dai_cpu_master>;
simple-audio-card,convert-rate = <48000>;
simple-audio-card,widgets =
"Microphone", "Mic Jack",
"Line", "Line In",
"Line", "Line Out",
"Speaker", "Speaker",
"Headphone", "Headphone Jack";
simple-audio-card,routing =
"Headphone Jack", "HP_L",
"Headphone Jack", "HP_R",
"Speaker", "SPK_LP",
"Speaker", "SPK_LN",
"Speaker", "SPK_RP",
"Speaker", "SPK_RN",
"Mic Jack", "MICB",
"LINPUT1", "Mic Jack",
"LINPUT2", "Line In",
"RINPUT2", "Line In";
dai_cpu_master: simple-audio-card,cpu {
sound-dai = <&sai2>;
};
dailink0: simple-audio-card,codec {
sound-dai = <&codec>;
};
};
pcie0_refclk: pcie0-refclk {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <100000000>;
};
pcie1_refclk: pcie1-refclk {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <100000000>;
};
};
&A53_0 {
cpu-supply = <&reg_arm_dram>;
};
&A53_1 {
cpu-supply = <&reg_arm_dram>;
};
&A53_2 {
cpu-supply = <&reg_arm_dram>;
};
&A53_3 {
cpu-supply = <&reg_arm_dram>;
};
/ {
soc@0 {
bus@32c00000 {
dcss: display-controller@32e00000 {
status = "okay";
compatible = "nxp,imx8mq-dcss";
reg = <0x32e00000 0x2d000>, <0x32e2f000 0x1000>;
interrupts = <6>, <8>, <9>;
interrupt-names = "ctxld", "ctxld_kick", "vblank";
interrupt-parent = <&irqsteer>;
clocks = <&clk IMX8MQ_CLK_DISP_APB_ROOT>,
<&clk IMX8MQ_CLK_DISP_AXI_ROOT>,
<&clk IMX8MQ_CLK_DISP_RTRM_ROOT>,
<&clk IMX8MQ_CLK_DC_PIXEL>,
<&clk IMX8MQ_CLK_DISP_DTRC>,
<&clk IMX8MQ_VIDEO2_PLL1_REF_SEL>,
<&clk IMX8MQ_CLK_PHY_27MHZ>;
clock-names = "apb", "axi", "rtrm", "pix", "dtrc", "pll_src", "pll_phy_ref";
assigned-clocks = <&clk IMX8MQ_CLK_DISP_AXI>,
<&clk IMX8MQ_CLK_DISP_RTRM>,
<&clk IMX8MQ_VIDEO2_PLL1_REF_SEL>,
<&clk IMX8MQ_VIDEO_PLL1_REF_SEL>,
<&clk IMX8MQ_CLK_DC_PIXEL>;
assigned-clock-parents = <&clk IMX8MQ_SYS1_PLL_800M>,
<&clk IMX8MQ_SYS1_PLL_800M>,
<&clk IMX8MQ_CLK_27M>,
<&clk IMX8MQ_CLK_25M>,
<&clk IMX8MQ_VIDEO_PLL1_OUT>;
assigned-clock-rates = <800000000>,
<400000000>,
<27000000>,
<25000000>,
<594000000>;
// internal display (MIPI-DSI/eDP)
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
#address-cells = <1>;
#size-cells = <0>;
dcss_dsi_out: endpoint@0 {
reg = <0>;
remote-endpoint = <&mipi_dsi_in>;
};
};
};
};
};
};
};
// LCDIF is not used, but has to be active or DCSS won't work
&lcdif {
status = "okay";
/delete-node/ port@0;
};
&dphy {
status = "okay";
};
&fec1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_fec1>;
phy-mode = "rgmii-id";
phy-handle = <&ethphy0>;
fsl,magic-packet;
status = "okay";
mdio {
#address-cells = <1>;
#size-cells = <0>;
ethphy0: ethernet-phy@4 {
compatible = "ethernet-phy-ieee802.3-c22";
reg = <4>;
interrupts = <&gpio1 11 IRQ_TYPE_LEVEL_LOW>;
reset-gpios = <&gpio1 9 GPIO_ACTIVE_LOW>; // TODO: useful?
};
};
};
&i2c1 {
clock-frequency = <400000>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c1>;
status = "okay";
// I2C Mux on Nitrogen8M_SOM
i2cmux@70 {
compatible = "nxp,pca9546";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c1_pca9546>;
reg = <0x70>;
reset-gpios = <&gpio1 4 GPIO_ACTIVE_LOW>;
#address-cells = <1>;
#size-cells = <0>;
i2c1a: i2c1@0 {
reg = <0>;
#address-cells = <1>;
#size-cells = <0>;
// Regulator on Nitrogen8M_SOM
reg_arm_dram: fan53555@60 {
compatible = "fcs,fan53555";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_reg_arm_dram>;
reg = <0x60>;
regulator-min-microvolt = <900000>;
regulator-max-microvolt = <1000000>;
regulator-ramp-delay = <8000>;
regulator-always-on;
vsel-gpios = <&gpio3 24 GPIO_ACTIVE_HIGH>;
};
};
i2c1b: i2c1@1 {
reg = <1>;
#address-cells = <1>;
#size-cells = <0>;
// Regulator on Nitrogen8M_SOM
reg_dram_1p1v: fan53555@60 {
compatible = "fcs,fan53555";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_reg_dram_1p1v>;
reg = <0x60>;
regulator-min-microvolt = <1100000>;
regulator-max-microvolt = <1100000>;
regulator-ramp-delay = <8000>;
regulator-always-on;
vsel-gpios = <&gpio2 11 GPIO_ACTIVE_HIGH>;
};
};
i2c1c: i2c1@2 {
reg = <2>;
#address-cells = <1>;
#size-cells = <0>;
// Regulator on Nitrogen8M_SOM
reg_soc_gpu_vpu: fan53555@60 {
compatible = "fcs,fan53555";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_reg_soc_gpu_vpu>;
reg = <0x60>;
regulator-min-microvolt = <900000>;
regulator-max-microvolt = <1000000>;
regulator-ramp-delay = <8000>;
regulator-always-on;
vsel-gpios = <&gpio2 20 GPIO_ACTIVE_HIGH>;
};
};
// No peripheral connected, available on DSI connector
i2c1d: i2c1@3 {
reg = <3>;
#address-cells = <1>;
#size-cells = <0>;
};
};
};
// No peripheral connected, available on CSI connector
&i2c2 {
status = "disabled";
};
&i2c3 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c3>;
status = "okay";
// Audio chip on motherboard
codec: wm8960@1a {
compatible = "wlf,wm8960";
reg = <0x1a>;
clocks = <&clk IMX8MQ_CLK_SAI2>;
clock-names = "mclk";
#sound-dai-cells = <0>;
};
// Realtime clock chip on motherboard
pcf8523: pcf8523@68 {
compatible = "nxp,pcf8523";
reg = <0x68>;
};
};
&i2c4 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c4>;
status = "okay";
// DSI to eDP converter on motherboard
edp_bridge: sn65dsi86@2c {
compatible = "ti,sn65dsi86";
reg = <0x2c>;
enable-gpios = <&gpio3 20 GPIO_ACTIVE_HIGH>;
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
edp_bridge_in: endpoint {
remote-endpoint = <&mipi_dsi_out>;
};
};
port@1 {
reg = <1>;
edp_bridge_out: endpoint {
remote-endpoint = <&panel_in>;
};
};
};
};
};
// TODO: add external pin numbers
&iomuxc {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_hog>;
pinctrl_hog: hoggrp {
fsl,pins = <
MX8MQ_IOMUXC_SAI5_RXC_GPIO3_IO20 0x19 // WL_EN on Nitrogen8M_SOM, pin 38, goes to /EN input of SN65DSI86
MX8MQ_IOMUXC_GPIO1_IO14_GPIO1_IO14 0x56 // TODO: check pullup of usb hub reset on the board (0x40)
>;
};
pinctrl_fec1: fec1grp {
fsl,pins = <
MX8MQ_IOMUXC_ENET_MDC_ENET1_MDC 0x3
MX8MQ_IOMUXC_ENET_MDIO_ENET1_MDIO 0x23
MX8MQ_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x1f
MX8MQ_IOMUXC_ENET_TXC_ENET1_RGMII_TXC 0x1f
MX8MQ_IOMUXC_ENET_TD0_ENET1_RGMII_TD0 0x1f
MX8MQ_IOMUXC_ENET_TD1_ENET1_RGMII_TD1 0x1f
MX8MQ_IOMUXC_ENET_TD2_ENET1_RGMII_TD2 0x1f
MX8MQ_IOMUXC_ENET_TD3_ENET1_RGMII_TD3 0x1f
MX8MQ_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x91
MX8MQ_IOMUXC_ENET_RXC_ENET1_RGMII_RXC 0x91
MX8MQ_IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x91
MX8MQ_IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x91
MX8MQ_IOMUXC_ENET_RD2_ENET1_RGMII_RD2 0x91
MX8MQ_IOMUXC_ENET_RD3_ENET1_RGMII_RD3 0x91
MX8MQ_IOMUXC_GPIO1_IO09_GPIO1_IO9 0x19
MX8MQ_IOMUXC_GPIO1_IO11_GPIO1_IO11 0x59
>;
};
pinctrl_i2c1: i2c1grp {
fsl,pins = <
MX8MQ_IOMUXC_I2C1_SCL_I2C1_SCL 0x4000007f
MX8MQ_IOMUXC_I2C1_SDA_I2C1_SDA 0x4000007f
>;
};
pinctrl_i2c1_pca9546: i2c1-pca9546grp {
fsl,pins = <
MX8MQ_IOMUXC_GPIO1_IO04_GPIO1_IO4 0x46
>;
};
pinctrl_i2c2: i2c2grp {
fsl,pins = <
MX8MQ_IOMUXC_I2C2_SCL_I2C2_SCL 0x4000007f
MX8MQ_IOMUXC_I2C2_SDA_I2C2_SDA 0x4000007f
>;
};
pinctrl_i2c3: i2c3grp {
fsl,pins = <
MX8MQ_IOMUXC_I2C3_SCL_I2C3_SCL 0x4000007f
MX8MQ_IOMUXC_I2C3_SDA_I2C3_SDA 0x4000007f
>;
};
pinctrl_i2c4: i2c4grp {
fsl,pins = <
MX8MQ_IOMUXC_I2C4_SCL_I2C4_SCL 0x4000007f
MX8MQ_IOMUXC_I2C4_SDA_I2C4_SDA 0x4000007f
>;
};
pinctrl_pcie0: pcie0grp {
fsl,pins = <
MX8MQ_IOMUXC_ECSPI1_MOSI_GPIO5_IO7 0x16
>;
};
pinctrl_pcie1: pcie1grp {
fsl,pins = <
MX8MQ_IOMUXC_SAI5_RXD2_GPIO3_IO23 0x16
>;
};
pinctrl_pwm2: pwm2grp {
fsl,pins = <
MX8MQ_IOMUXC_SPDIF_RX_PWM2_OUT 0x16
>;
};
pinctrl_pwm3: pwm3grp {
fsl,pins = <
MX8MQ_IOMUXC_SPDIF_TX_PWM3_OUT 0x16
>;
};
// Backlight
pinctrl_pwm4: pwm4grp {
fsl,pins = <
MX8MQ_IOMUXC_SAI3_MCLK_PWM4_OUT 0x16
>;
};
pinctrl_reg_arm_dram: reg-arm-dram {
fsl,pins = <
MX8MQ_IOMUXC_SAI5_RXD3_GPIO3_IO24 0x16
>;
};
pinctrl_reg_dram_1p1v: reg-dram-1p1v {
fsl,pins = <
MX8MQ_IOMUXC_SD1_STROBE_GPIO2_IO11 0x16
>;
};
pinctrl_reg_soc_gpu_vpu: reg-soc-gpu-vpu {
fsl,pins = <
MX8MQ_IOMUXC_SD2_WP_GPIO2_IO20 0x16
>;
};
pinctrl_sai2: sai2grp {
fsl,pins = <
MX8MQ_IOMUXC_SAI2_RXD0_SAI2_RX_DATA0 0xd6 /* Pin 166 */
MX8MQ_IOMUXC_SAI2_RXFS_SAI2_RX_SYNC 0xd6 /* Pin 168 */
MX8MQ_IOMUXC_SAI2_TXC_SAI2_TX_BCLK 0xd6 /* Pin 170 */
MX8MQ_IOMUXC_SAI2_TXFS_SAI2_TX_SYNC 0xd6 /* Pin 172 */
MX8MQ_IOMUXC_SAI2_RXC_SAI2_RX_BCLK 0xd6 /* Pin 174 */
MX8MQ_IOMUXC_SAI2_MCLK_SAI2_MCLK 0xd6 /* Pin 176 */
MX8MQ_IOMUXC_SAI2_TXD0_SAI2_TX_DATA0 0xd6 /* Pin 168 */
>;
};
pinctrl_uart1: uart1grp {
fsl,pins = <
MX8MQ_IOMUXC_UART1_RXD_UART1_DCE_RX 0x45
MX8MQ_IOMUXC_UART1_TXD_UART1_DCE_TX 0x45
>;
};
pinctrl_uart2: uart2grp {
fsl,pins = <
MX8MQ_IOMUXC_UART2_RXD_UART2_DCE_RX 0x45
MX8MQ_IOMUXC_UART2_TXD_UART2_DCE_TX 0x45
>;
};
pinctrl_uart3: uart3grp {
fsl,pins = <
MX8MQ_IOMUXC_UART3_RXD_UART3_DCE_RX 0x45
MX8MQ_IOMUXC_UART3_TXD_UART3_DCE_TX 0x45
>;
};
pinctrl_usdhc1: usdhc1grp {
fsl,pins = <
MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK 0x83
MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD 0xc3
MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0 0xc3
MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1 0xc3
MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2 0xc3
MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3 0xc3
MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4 0xc3
MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5 0xc3
MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6 0xc3
MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7 0xc3
MX8MQ_IOMUXC_SD1_RESET_B_GPIO2_IO10 0x41
>;
};
pinctrl_usdhc1_100mhz: usdhc1-100mhzgrp {
fsl,pins = <
MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK 0x8d
MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD 0xcd
MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0 0xcd
MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1 0xcd
MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2 0xcd
MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3 0xcd
MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4 0xcd
MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5 0xcd
MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6 0xcd
MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7 0xcd
>;
};
pinctrl_usdhc1_200mhz: usdhc1-200mhzgrp {
fsl,pins = <
MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK 0x9f
MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD 0xdf
MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0 0xdf
MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1 0xdf
MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2 0xdf
MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3 0xdf
MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4 0xdf
MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5 0xdf
MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6 0xdf
MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7 0xdf
>;
};
pinctrl_usdhc2: usdhc2grp {
fsl,pins = <
MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK 0x03
MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD 0xc3
MX8MQ_IOMUXC_SD2_DATA0_USDHC2_DATA0 0xc3
MX8MQ_IOMUXC_SD2_DATA1_USDHC2_DATA1 0xc3
MX8MQ_IOMUXC_SD2_DATA2_USDHC2_DATA2 0xc3
MX8MQ_IOMUXC_SD2_DATA3_USDHC2_DATA3 0xc
>;
};
pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp {
fsl,pins = <
MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK 0x0d
MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD 0xcd
MX8MQ_IOMUXC_SD2_DATA0_USDHC2_DATA0 0xcd
MX8MQ_IOMUXC_SD2_DATA1_USDHC2_DATA1 0xcd
MX8MQ_IOMUXC_SD2_DATA2_USDHC2_DATA2 0xcd
MX8MQ_IOMUXC_SD2_DATA3_USDHC2_DATA3 0xcd
>;
};
pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp {
fsl,pins = <
MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK 0x1e
MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD 0xce
MX8MQ_IOMUXC_SD2_DATA0_USDHC2_DATA0 0xce
MX8MQ_IOMUXC_SD2_DATA1_USDHC2_DATA1 0xce
MX8MQ_IOMUXC_SD2_DATA2_USDHC2_DATA2 0xce
MX8MQ_IOMUXC_SD2_DATA3_USDHC2_DATA3 0xce
>;
};
pinctrl_wdog: wdoggrp {
fsl,pins = <
MX8MQ_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B 0xc6
>;
};
};
&mipi_dsi {
status = "okay";
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
#address-cells = <1>;
#size-cells = <0>;
reg = <0>;
// We don't want input from LCDIF
/delete-node/ endpoint@0;
mipi_dsi_in: endpoint@1 {
reg = <1>;
remote-endpoint = <&dcss_dsi_out>;
};
};
port@1 {
reg = <1>;
mipi_dsi_out: endpoint {
remote-endpoint = <&edp_bridge_in>;
};
};
};
};
&pcie0 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_pcie0>;
reset-gpio = <&gpio5 7 GPIO_ACTIVE_LOW>;
internal-refclk;
clocks = <&clk IMX8MQ_CLK_PCIE1_ROOT>,
<&clk IMX8MQ_CLK_PCIE1_AUX>,
<&clk IMX8MQ_CLK_PCIE1_PHY>,
<&pcie0_refclk>;
clock-names = "pcie", "pcie_aux", "pcie_phy", "pcie_bus";
assigned-clocks = <&clk IMX8MQ_CLK_PCIE1_CTRL>,
<&clk IMX8MQ_CLK_PCIE1_PHY>;
assigned-clock-parents = <&clk IMX8MQ_SYS2_PLL_250M>,
<&clk IMX8MQ_SYS2_PLL_100M>;
status = "okay";
};
&pcie1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_pcie1>;
reset-gpio = <&gpio3 23 GPIO_ACTIVE_LOW>;
clocks = <&clk IMX8MQ_CLK_PCIE2_ROOT>,
<&clk IMX8MQ_CLK_PCIE2_AUX>,
<&clk IMX8MQ_CLK_PCIE2_PHY>,
<&pcie1_refclk>;
clock-names = "pcie", "pcie_aux", "pcie_phy", "pcie_bus";
status = "okay";
};
&pwm2 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_pwm2>;
status = "okay";
};
&pwm3 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_pwm3>;
status = "okay";
};
// Backlight control
&pwm4 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_pwm4>;
status = "okay";
};
&sai2 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_sai2>;
assigned-clocks = <&clk IMX8MQ_CLK_SAI2>;
assigned-clock-parents = <&clk IMX8MQ_AUDIO_PLL1_OUT>;
assigned-clock-rates = <12288000>;
fsl,sai-asynchronous;
status = "okay";
};
// Don't use i.MX8M internal RTC because we have a dedicated one
&snvs_rtc {
status = "disabled";
};
// Console
&uart1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart1>;
status = "okay";
};
// Auxiliary serial port on motherboard
&uart2 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart2>;
status = "okay";
};
// connected to LPC11U24 chip on the motherboard
&uart3 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart3>;
status = "okay";
};
&usb_dwc3_0 {
status = "okay";
dr_mode = "host";
};
&usb_dwc3_1 {
status = "okay";
dr_mode = "host";
};
&usb3_phy0 {
vbus-supply = <&reg_vref_5v>;
status = "okay";
};
&usb3_phy1 {
vbus-supply = <&reg_vref_5v>;
status = "okay";
};
// eMMC on Nitrogen8M_SOM
// TODO: HS currently doesn't work
&usdhc1 {
bus-width = <8>;
fsl,strobe-dll-delay-target = <5>;
fsl,tuning-start-tap = <63>;
fsl,tuning-step = <2>;
non-removable;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usdhc1>;
vmmc-supply = <&reg_vref_1v8>;
vqmmc-1-8-v;
status = "okay";
};
// SD Card on motherboard
// TODO: check keep-power-in-suspend, cap-sdio-irq
&usdhc2 {
assigned-clocks = <&clk IMX8MQ_CLK_USDHC2>;
assigned-clock-rates = <200000000>;
bus-width = <4>;
no-1-8-v; // We don't support 1.8V signaling
pinctrl-names = "default", "state_100mhz", "state_200mhz";
pinctrl-0 = <&pinctrl_usdhc2>;
pinctrl-1 = <&pinctrl_usdhc2_100mhz>;
pinctrl-2 = <&pinctrl_usdhc2_200mhz>;
vmmc-supply = <&reg_vref_3v3>;
status = "okay";
};
&wdog1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_wdog>;
fsl,ext-reset-output; // TODO check source for what this means
status = "okay";
};

6131
src/kernel-config Normal file
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File diff suppressed because it is too large Load diff

73
src/make_kernel.sh Executable file
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@ -0,0 +1,73 @@
#!/bin/bash
set -e
function usage {
cat <<EOF
Compile Kernel for MNT Reform
---
This script compile Linux kernel for the MNT Reform2 laptop.
USAGE:
make_kernel.sh <version>
<version> : kernel version to compile. This argument is not require if you
define KERNEL_VERSION environment variable.
EOF
}
function error {
>&2 printf "\e[31mE\e[0m %s\n" "$1"
}
export ARCH=arm64
#export LOADADDR=0x40480000
export CROSS_COMPILE=aarch64-linux-gnu-
GIT_URL="https://github.com/torvalds/linux/"
if [ ! -z $1 ]
then
KERNEL_VERSION="$1"
fi
if [ -z "$KERNEL_VERSION" ]
then
error "You need to define KERNEL_VERSION env variable"
usage
exit 10
fi
if [ ! -d linux ]
then
printf "Cloning Linux...\n"
# temporary linux 5.11rc7 commit
if ! git clone --depth 1 --branch=v${KERNEL_VERSION} $GIT_URL
then
error "Can't clone Linux, check version"
exit 11
fi
fi
cp ./dts/*.dts ./linux/arch/arm64/boot/dts/freescale/
cp ./kernel-config ./linux/.config
cd linux
for PATCHFILE in ../patches/*.patch
do
printf "Apply patch %s\n" $PATCHFILE
if git apply --check $PATCHFILE
then
git apply $PATCHFILE
else
error "Kernel patch already applied or cannot apply: $PATCHFILE"
fi
done
make -j$(nproc) Image freescale/imx8mq-mnt-reform2.dtb freescale/imx8mq-mnt-reform2-hdmi.dtb
cd ..
exit 0

37
src/patches/0001-nwl-dsi-fixup-mode-only-for-LCDIF-input-not-DCSS.patch Normal file
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@ -0,0 +1,37 @@
From 7443b914832c05cfe3707555b7d1ca1f3c6d7783 Mon Sep 17 00:00:00 2001
From: mntmn <lukas@mntmn.com>
Date: Tue, 24 Nov 2020 00:49:16 +0100
Subject: [PATCH 1/8] nwl-dsi: fixup mode only for LCDIF input, not DCSS
The inversion of HSYNC and VSYNC should not be done when the input
source is DCSS, or internal display does not work on MNT Reform 2.0.
---
drivers/gpu/drm/bridge/nwl-dsi.c | 12 +++++++++---
1 file changed, 9 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/bridge/nwl-dsi.c b/drivers/gpu/drm/bridge/nwl-dsi.c
index 66b67402f..6735ab2a2 100644
--- a/drivers/gpu/drm/bridge/nwl-dsi.c
+++ b/drivers/gpu/drm/bridge/nwl-dsi.c
@@ -807,9 +807,15 @@ static bool nwl_dsi_bridge_mode_fixup(struct drm_bridge *bridge,
const struct drm_display_mode *mode,
struct drm_display_mode *adjusted_mode)
{
- /* At least LCDIF + NWL needs active high sync */
- adjusted_mode->flags |= (DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC);
- adjusted_mode->flags &= ~(DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC);
+ struct device_node *remote;
+ struct nwl_dsi *dsi = bridge_to_dsi(bridge);
+ remote = of_graph_get_remote_node(dsi->dev->of_node, 0,
+ NWL_DSI_ENDPOINT_LCDIF);
+ if (remote) {
+ /* At least LCDIF + NWL needs active high sync */
+ adjusted_mode->flags |= (DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC);
+ adjusted_mode->flags &= ~(DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC);
+ }
return true;
}
--
2.28.0

99
src/patches/0005-pci-imx6-add-support-for-internal-refclk-imx8mq.patch Normal file
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@ -0,0 +1,99 @@
From 30d25ce7792fd1aa37e839a513b7fcf7447fd813 Mon Sep 17 00:00:00 2001
From: mntmn <lukas@mntmn.com>
Date: Tue, 24 Nov 2020 01:01:42 +0100
Subject: [PATCH 5/8] pci-imx6: add support for internal refclk (imx8mq)
NXP i.MX8MQ supports feeding an internal refclk to the PCIe root
controller(s). This is required to make use of the first PCIe controller
on the Boundary Devices Nitrogen8M SoM, which is the standard processor
module of MNT Reform 2.0.
The patch adds a new boolean property "internal_refclk" for the pcie
nodes.
The actual generation of the clock requires poking a register of ANATOP.
The code for this is taken from the (fsl) vendor kernel.
---
drivers/pci/controller/dwc/pci-imx6.c | 43 ++++++++++++++++++++++++++-
1 file changed, 42 insertions(+), 1 deletion(-)
diff --git a/drivers/pci/controller/dwc/pci-imx6.c b/drivers/pci/controller/dwc/pci-imx6.c
index 5cf1ef12f..2f1ed228d 100644
--- a/drivers/pci/controller/dwc/pci-imx6.c
+++ b/drivers/pci/controller/dwc/pci-imx6.c
@@ -64,6 +64,7 @@ struct imx6_pcie {
struct dw_pcie *pci;
int reset_gpio;
bool gpio_active_high;
+ bool internal_refclk;
struct clk *pcie_bus;
struct clk *pcie_phy;
struct clk *pcie_inbound_axi;
@@ -609,8 +610,45 @@ static void imx6_pcie_configure_type(struct imx6_pcie *imx6_pcie)
regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR12, mask, val);
}
+#define IMX8MQ_ANA_PLLOUT_REG 0x74
+#define IMX8MQ_ANA_PLLOUT_CKE BIT(4)
+#define IMX8MQ_ANA_PLLOUT_SEL_MASK 0xF
+#define IMX8MQ_ANA_PLLOUT_SEL_SYSPLL1 0xB
+#define IMX8MQ_ANA_PLLOUT_DIV_REG 0x7C
+#define IMX8MQ_ANA_PLLOUT_SYSPLL1_DIV 0x7
+
+static void imx6_pcie_enable_internal_refclk(void)
+{
+ uint32_t val;
+ struct device_node* np;
+ void __iomem *base;
+
+ np = of_find_compatible_node(NULL, NULL,
+ "fsl,imx8mq-anatop");
+ base = of_iomap(np, 0);
+ WARN_ON(!base);
+
+ val = readl(base + IMX8MQ_ANA_PLLOUT_REG);
+ val &= ~IMX8MQ_ANA_PLLOUT_SEL_MASK;
+ val |= IMX8MQ_ANA_PLLOUT_SEL_SYSPLL1;
+ writel(val, base + IMX8MQ_ANA_PLLOUT_REG);
+ /* SYS_PLL1 is 800M, PCIE REF CLK is 100M */
+ val = readl(base + IMX8MQ_ANA_PLLOUT_DIV_REG);
+ val |= IMX8MQ_ANA_PLLOUT_SYSPLL1_DIV;
+ writel(val, base + IMX8MQ_ANA_PLLOUT_DIV_REG);
+
+ val = readl(base + IMX8MQ_ANA_PLLOUT_REG);
+ val |= IMX8MQ_ANA_PLLOUT_CKE;
+ writel(val, base + IMX8MQ_ANA_PLLOUT_REG);
+
+ usleep_range(9000,10000);
+}
+
static void imx6_pcie_init_phy(struct imx6_pcie *imx6_pcie)
{
+ if (imx6_pcie->internal_refclk)
+ imx6_pcie_enable_internal_refclk();
+
switch (imx6_pcie->drvdata->variant) {
case IMX8MQ:
/*
@@ -620,7 +658,8 @@ static void imx6_pcie_init_phy(struct imx6_pcie *imx6_pcie)
regmap_update_bits(imx6_pcie->iomuxc_gpr,
imx6_pcie_grp_offset(imx6_pcie),
IMX8MQ_GPR_PCIE_REF_USE_PAD,
- IMX8MQ_GPR_PCIE_REF_USE_PAD);
+ (imx6_pcie->internal_refclk ?
+ 0 : IMX8MQ_GPR_PCIE_REF_USE_PAD));
break;
case IMX7D:
regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR12,
@@ -1087,6 +1126,8 @@ static int imx6_pcie_probe(struct platform_device *pdev)
if (IS_ERR(imx6_pcie->pcie_aux))
return dev_err_probe(dev, PTR_ERR(imx6_pcie->pcie_aux),
"pcie_aux clock source missing or invalid\n");
+ imx6_pcie->internal_refclk = of_property_read_bool(node,
+ "internal-refclk");
fallthrough;
case IMX7D:
if (dbi_base->start == IMX8MQ_PCIE2_BASE_ADDR)
--
2.28.0

52
src/patches/0009-revert-58074b08c04af1817ab34be986a80279e7267d07-edid.patch Normal file
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@ -0,0 +1,52 @@
diff --git a/drivers/gpu/drm/bridge/ti-sn65dsi86.c b/drivers/gpu/drm/bridge/ti-sn65dsi86.c
index f27306c51e4d..42ac796ac053 100644
--- a/drivers/gpu/drm/bridge/ti-sn65dsi86.c
+++ b/drivers/gpu/drm/bridge/ti-sn65dsi86.c
@@ -121,7 +121,6 @@
* @debugfs: Used for managing our debugfs.
* @host_node: Remote DSI node.
* @dsi: Our MIPI DSI source.
- * @edid: Detected EDID of eDP panel.
* @refclk: Our reference clock.
* @panel: Our panel.
* @enable_gpio: The GPIO we toggle to enable the bridge.
@@ -147,7 +146,6 @@ struct ti_sn_bridge {
struct drm_bridge bridge;
struct drm_connector connector;
struct dentry *debugfs;
- struct edid *edid;
struct device_node *host_node;
struct mipi_dsi_device *dsi;
struct clk *refclk;
@@ -269,23 +267,6 @@ connector_to_ti_sn_bridge(struct drm_connector *connector)
static int ti_sn_bridge_connector_get_modes(struct drm_connector *connector)
{
struct ti_sn_bridge *pdata = connector_to_ti_sn_bridge(connector);
- struct edid *edid = pdata->edid;
- int num, ret;
-
- if (!edid) {
- pm_runtime_get_sync(pdata->dev);
- edid = pdata->edid = drm_get_edid(connector, &pdata->aux.ddc);
- pm_runtime_put(pdata->dev);
- }
-
- if (edid && drm_edid_is_valid(edid)) {
- ret = drm_connector_update_edid_property(connector, edid);
- if (!ret) {
- num = drm_add_edid_modes(connector, edid);
- if (num)
- return num;
- }
- }
return drm_panel_get_modes(pdata->panel, connector);
}
@@ -1306,7 +1287,6 @@ static int ti_sn_bridge_remove(struct i2c_client *client)
if (!pdata)
return -EINVAL;
- kfree(pdata->edid);
ti_sn_debugfs_remove(pdata);
of_node_put(pdata->host_node);

30
src/patches/mnt3004-MNT-Reform-imx8mq-add-PHY_27M-clock.patch Normal file
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@ -0,0 +1,30 @@
From b9b161fcc88ab6fa0642aa3f533be3e0aac6978b Mon Sep 17 00:00:00 2001
From: mntmn <lukas@mntmn.com>
Date: Thu, 28 May 2020 22:51:46 +0200
Subject: [PATCH] MNT Reform: imx8mq: add PHY_27M clock
---
drivers/clk/imx/clk-imx8mq.c | 8 +++++++-
1 file changed, 7 insertions(+), 1 deletion(-)
diff --git a/drivers/clk/imx/clk-imx8mq.c b/drivers/clk/imx/clk-imx8mq.c
index fdc68db68de5..a9e2d2f09864 100644
--- a/drivers/clk/imx/clk-imx8mq.c
+++ b/drivers/clk/imx/clk-imx8mq.c
@@ -25,7 +25,7 @@ static u32 share_count_sai6;
static u32 share_count_dcss;
static u32 share_count_nand;
-static const char * const pll_ref_sels[] = { "osc_25m", "osc_27m", "dummy", "dummy", };
+static const char * const pll_ref_sels[] = { "osc_25m", "osc_27m", "phy_27m", "dummy", };
static const char * const arm_pll_bypass_sels[] = {"arm_pll", "arm_pll_ref_sel", };
static const char * const gpu_pll_bypass_sels[] = {"gpu_pll", "gpu_pll_ref_sel", };
static const char * const vpu_pll_bypass_sels[] = {"vpu_pll", "vpu_pll_ref_sel", };
@@ -304,6 +304,7 @@ static int imx8mq_clocks_probe(struct platform_device *pdev)
hws[IMX8MQ_CLK_EXT2] = imx_obtain_fixed_clk_hw(np, "clk_ext2");
hws[IMX8MQ_CLK_EXT3] = imx_obtain_fixed_clk_hw(np, "clk_ext3");
hws[IMX8MQ_CLK_EXT4] = imx_obtain_fixed_clk_hw(np, "clk_ext4");
+ hws[IMX8MQ_CLK_PHY_27MHZ] = imx_clk_hw_fixed("phy_27m", 27000000);
np = of_find_compatible_node(NULL, NULL, "fsl,imx8mq-anatop");
base = of_iomap(np, 0);

27
src/patches/mnt3006-MNT-Reform-imx8mq-add-PHY_27M-clock-missing-define.patch Normal file
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@ -0,0 +1,27 @@
From 5bbfbc478adc68ae7e9fb1d5b0239d3ba93c8471 Mon Sep 17 00:00:00 2001
From: mntmn <lukas@mntmn.com>
Date: Thu, 28 May 2020 23:22:18 +0200
Subject: [PATCH] MNT Reform: imx8mq: add PHY_27M clock: missing define
---
include/dt-bindings/clock/imx8mq-clock.h | 5 ++++-
1 file changed, 4 insertions(+), 1 deletion(-)
diff --git a/include/dt-bindings/clock/imx8mq-clock.h b/include/dt-bindings/clock/imx8mq-clock.h
index 9b8045d75b8b..29b86c579b40 100644
--- a/include/dt-bindings/clock/imx8mq-clock.h
+++ b/include/dt-bindings/clock/imx8mq-clock.h
@@ -431,6 +431,9 @@
#define IMX8MQ_CLK_A53_CORE 289
-#define IMX8MQ_CLK_END 290
+#define IMX8MQ_CLK_PHY_27MHZ 290
+
+#define IMX8MQ_CLK_END 291
+
#endif /* __DT_BINDINGS_CLOCK_IMX8MQ_H */
--
2.26.2

15
src/patches/mnt4000-limit-fslsai-to-48khz.patch Normal file
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@ -0,0 +1,15 @@
diff --git a/sound/soc/fsl/fsl_sai.c b/sound/soc/fsl/fsl_sai.c
index f3d3d20d35d7..449af79e2640 100644
--- a/sound/soc/fsl/fsl_sai.c
+++ b/sound/soc/fsl/fsl_sai.c
@@ -27,9 +27,7 @@
FSL_SAI_CSR_FEIE)
static const unsigned int fsl_sai_rates[] = {
- 8000, 11025, 12000, 16000, 22050,
- 24000, 32000, 44100, 48000, 64000,
- 88200, 96000, 176400, 192000
+ 48000, 96000, 192000
};
static const struct snd_pcm_hw_constraint_list fsl_sai_rate_constraints = {

58
src/patches/mnt4001-lcdif-fix-pcie-interference.patch Normal file
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@ -0,0 +1,58 @@
diff --git a/drivers/gpu/drm/mxsfb/mxsfb_kms.c b/drivers/gpu/drm/mxsfb/mxsfb_kms.c
index 3e1bb0aefb87..13128b6f2770 100644
--- a/drivers/gpu/drm/mxsfb/mxsfb_kms.c
+++ b/drivers/gpu/drm/mxsfb/mxsfb_kms.c
@@ -212,7 +212,7 @@ static void mxsfb_crtc_mode_set_nofb(struct mxsfb_drm_private *mxsfb)
mxsfb_set_formats(mxsfb);
- clk_set_rate(mxsfb->clk, m->crtc_clock * 1000);
+ clk_set_rate(mxsfb->clk, m->crtc_clock * 660);
if (mxsfb->bridge && mxsfb->bridge->timings)
bus_flags = mxsfb->bridge->timings->input_bus_flags;
@@ -540,12 +540,44 @@ static const uint64_t mxsfb_modifiers[] = {
* Initialization
*/
+void imx8mq_pcie_qos_for_lcdif(void)
+{
+ void __iomem *qosc = ioremap(0x307f0000, 0x2100);
+ // clock and unlock QoSC registers
+ writel(0x0, qosc);
+ writel(0x1, qosc);
+ writel(0x0, qosc+0x60);
+
+ // limit number of outstanding transactions for PCIe1
+ writel(0x0, qosc+0x1000);
+ writel(0x1, qosc+0x1000);
+ writel(0x01010100, qosc+0x1050);
+ writel(0x01010100, qosc+0x1060);
+ writel(0x01010100, qosc+0x1070);
+ writel(0x1, qosc+0x1000);
+
+ // limit number of outstanding transactions for PCIe2
+ writel(0x0, qosc+0x2000);
+ writel(0x1, qosc+0x2000);
+ writel(0x01010100, qosc+0x2050);
+ writel(0x01010100, qosc+0x2060);
+ writel(0x01010100, qosc+0x2070);
+ writel(0x1, qosc+0x2000);
+
+ iounmap(qosc);
+}
+
int mxsfb_kms_init(struct mxsfb_drm_private *mxsfb)
{
struct drm_encoder *encoder = &mxsfb->encoder;
struct drm_crtc *crtc = &mxsfb->crtc;
int ret;
+ /*
+ FIXME Workaround to fix PCIe interfering with LCDIF refresh (MNT Reform)
+ */
+ imx8mq_pcie_qos_for_lcdif();
+
drm_plane_helper_add(&mxsfb->planes.primary,
&mxsfb_plane_primary_helper_funcs);
ret = drm_universal_plane_init(mxsfb->drm, &mxsfb->planes.primary, 1,

82
src/patches/mnt4002-imx-gpcv2-wake-smccc.patch Normal file
View file

@ -0,0 +1,82 @@
diff --git a/drivers/irqchip/irq-imx-gpcv2.c b/drivers/irqchip/irq-imx-gpcv2.c
index 7031ef44de4f..9cba81b5050d 100644
--- a/drivers/irqchip/irq-imx-gpcv2.c
+++ b/drivers/irqchip/irq-imx-gpcv2.c
@@ -3,6 +3,7 @@
* Copyright (C) 2015 Freescale Semiconductor, Inc.
*/
+#include <linux/arm-smccc.h>
#include <linux/of_address.h>
#include <linux/of_irq.h>
#include <linux/slab.h>
@@ -17,6 +18,13 @@
#define GPC_IMR1_CORE2 0x1c0
#define GPC_IMR1_CORE3 0x1d0
+#define FSL_SIP_GPC 0xC2000000
+#define FSL_SIP_CONFIG_GPC_MASK 0x00
+#define FSL_SIP_CONFIG_GPC_UNMASK 0x01
+#define FSL_SIP_CONFIG_GPC_SET_WAKE 0x02
+#define FSL_SIP_CONFIG_GPC_PM_DOMAIN 0x03
+#define FSL_SIP_CONFIG_GPC_SET_AFF 0x04
+#define FSL_SIP_CONFIG_GPC_CORE_WAKE 0x05
struct gpcv2_irqchip_data {
struct raw_spinlock rlock;
@@ -76,12 +84,17 @@ static int imx_gpcv2_irq_set_wake(struct irq_data *d, unsigned int on)
unsigned int idx = d->hwirq / 32;
unsigned long flags;
u32 mask, val;
+ struct arm_smccc_res res;
raw_spin_lock_irqsave(&cd->rlock, flags);
mask = BIT(d->hwirq % 32);
val = cd->wakeup_sources[idx];
cd->wakeup_sources[idx] = on ? (val & ~mask) : (val | mask);
+
+ // save wakeup config in vendor tf-a
+ arm_smccc_smc(FSL_SIP_GPC, FSL_SIP_CONFIG_GPC_SET_WAKE, d->hwirq, on, 0, 0, 0, 0, &res);
+
raw_spin_unlock_irqrestore(&cd->rlock, flags);
/*
@@ -97,6 +110,7 @@ static void imx_gpcv2_irq_unmask(struct irq_data *d)
struct gpcv2_irqchip_data *cd = d->chip_data;
void __iomem *reg;
u32 val;
+ struct arm_smccc_res res;
raw_spin_lock(&cd->rlock);
reg = gpcv2_idx_to_reg(cd, d->hwirq / 32);
@@ -105,6 +119,10 @@ static void imx_gpcv2_irq_unmask(struct irq_data *d)
writel_relaxed(val, reg);
raw_spin_unlock(&cd->rlock);
+ // call into vendor tf-a
+ //arm_smccc_smc(FSL_SIP_GPC, FSL_SIP_CONFIG_GPC_UNMASK,
+ // d->hwirq, 0, 0, 0, 0, 0, &res);
+
irq_chip_unmask_parent(d);
}
@@ -113,12 +131,18 @@ static void imx_gpcv2_irq_mask(struct irq_data *d)
struct gpcv2_irqchip_data *cd = d->chip_data;
void __iomem *reg;
u32 val;
+ struct arm_smccc_res res;
raw_spin_lock(&cd->rlock);
reg = gpcv2_idx_to_reg(cd, d->hwirq / 32);
val = readl_relaxed(reg);
val |= BIT(d->hwirq % 32);
writel_relaxed(val, reg);
+
+ // call into vendor tf-a
+ //arm_smccc_smc(FSL_SIP_GPC, FSL_SIP_CONFIG_GPC_MASK,
+ // d->hwirq, 0, 0, 0, 0, 0, &res);
+
raw_spin_unlock(&cd->rlock);
irq_chip_mask_parent(d);

21
src/patches/mnt4003-emmc-clockgate.patch Normal file
View file

@ -0,0 +1,21 @@
diff --git a/drivers/clk/imx/clk-imx8mq.c b/drivers/clk/imx/clk-imx8mq.c
index 779ea69e6..62ba6fb0d 100644
--- a/drivers/clk/imx/clk-imx8mq.c
+++ b/drivers/clk/imx/clk-imx8mq.c
@@ -364,7 +365,6 @@ static int imx8mq_clocks_probe(struct platform_device *pdev)
hws[IMX8MQ_SYS1_PLL_133M_CG] = imx_clk_hw_gate("sys1_pll_133m_cg", "sys1_pll_out", base + 0x30, 15);
hws[IMX8MQ_SYS1_PLL_160M_CG] = imx_clk_hw_gate("sys1_pll_160m_cg", "sys1_pll_out", base + 0x30, 17);
hws[IMX8MQ_SYS1_PLL_200M_CG] = imx_clk_hw_gate("sys1_pll_200m_cg", "sys1_pll_out", base + 0x30, 19);
- hws[IMX8MQ_SYS1_PLL_266M_CG] = imx_clk_hw_gate("sys1_pll_266m_cg", "sys1_pll_out", base + 0x30, 21);
hws[IMX8MQ_SYS1_PLL_400M_CG] = imx_clk_hw_gate("sys1_pll_400m_cg", "sys1_pll_out", base + 0x30, 23);
hws[IMX8MQ_SYS1_PLL_800M_CG] = imx_clk_hw_gate("sys1_pll_800m_cg", "sys1_pll_out", base + 0x30, 25);
@@ -374,7 +374,7 @@ static int imx8mq_clocks_probe(struct platform_device *pdev)
hws[IMX8MQ_SYS1_PLL_133M] = imx_clk_hw_fixed_factor("sys1_pll_133m", "sys1_pll_133m_cg", 1, 6);
hws[IMX8MQ_SYS1_PLL_160M] = imx_clk_hw_fixed_factor("sys1_pll_160m", "sys1_pll_160m_cg", 1, 5);
hws[IMX8MQ_SYS1_PLL_200M] = imx_clk_hw_fixed_factor("sys1_pll_200m", "sys1_pll_200m_cg", 1, 4);
- hws[IMX8MQ_SYS1_PLL_266M] = imx_clk_hw_fixed_factor("sys1_pll_266m", "sys1_pll_266m_cg", 1, 3);
+ hws[IMX8MQ_SYS1_PLL_266M] = imx_clk_hw_fixed_factor("sys1_pll_266m", "sys1_pll_out", 1, 3);
hws[IMX8MQ_SYS1_PLL_400M] = imx_clk_hw_fixed_factor("sys1_pll_400m", "sys1_pll_400m_cg", 1, 2);
hws[IMX8MQ_SYS1_PLL_800M] = imx_clk_hw_fixed_factor("sys1_pll_800m", "sys1_pll_800m_cg", 1, 1);

6877
src/patches/mnt5000-imx8mq-import-HDMI-driver-and-make-DCSS-compatible.patch Normal file
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